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Digital Electronics Section 15
Digital Electronics Section 15
D. none
Answer: Option B
Explanation:
A. 1 sec
B. 1 mili sec
C. 1 μ sec
D. 1 n sec
Answer: Option C
Explanation:
3. In LIFO
Answer: Option A
Explanation:
A. 10100
B. 1100
C. 010111
Answer: Option D
Explanation:
Answer: Option C
6. A 1 ms pulse can be converted into a 10 ms pulse by using which one of the following
A. An astable multivibrator
B. Stable multivibrator
C. A bistable multivibrator
D. A J-K flip-flop
Answer: Option B
Explanation:
7. In the DRAM cell in the figure is the Vt of the NMOSFET is 1 V. For the following three
combinations of WL and BL voltages.
A. 5 V, 3 V, 7 V
B. 4 V, 3 V, 4 V
C. 5 V, 5 V, 5 V
D. 4 V, 4 V, 4 V
Answer: Option C
Explanation:
No answer description available for this question. Let us discuss.
Reason (R): The carry look ahead adder generates the carry and sum digits directly.
C. A is true, R is false
D. A is false, R is true
Answer: Option C
Explanation:
Answer: Option C
Explanation:
1. (BA)16 - (AB)16
2. (BC)16 - (CB)16
3. (CB)16 - (BC)16
4. (CB)16 - (BC)16
A. 1 and 2
B. 1 and 3
C. 2 and 3
D. 1, 2 and 3
Answer: Option A
11. In 8085 microprocessor, how many I/O ports can be accessed by direct method?
A. 8
B. 256
C. 32 K
D. 64 K
Answer: Option B
Explanation:
12. If the mantissa of a digital computer is 37 bit long then the accuracy of the digital computer will
be of
A. 37 decimal places
B. 23 decimal places
C. 11 decimal places
D. accuracy is independent of the length to mantissa
Answer: Option C
Explanation:
Answer: Option A
Explanation:
A. half adder
B. full adder
C. half subtractor
D. full subtractor
Answer: Option A
Explanation:
15. A D-flip-flop is
B. delay flip-flop
C. differential flip-flop
D. digital flip-flop
Answer: Option B
16. The fetching, decoding and executing of an instruction is broken down into several time intervals.
Each of these intervals, involving one or more clock periods, is called a
A. instruction cycle
B. machine cycle
C. process cycle
Answer: Option B
Explanation:
17. The output of the circuit shown below will be of the frequency
A. 125 Hz
B. 250 Hz
C. 500 Hz
D. 750 Hz
Answer: Option B
Explanation:
A. A
B. B
C. A+B+C
D. ABC
Explanation:
C. A is true, R is false
D. A is false, R is true
Answer: Option B
Explanation:
20. If a RAM has 34 bits in its MAR and 16 bits in its MDR, then its capacity will be
A. 32 GB
B. 16 GB
C. 32 MB
D. 16 MB
Answer: Option A
21. DeMorgan's second theorem is
A. A.A=0
B. A=A
C. A+B=A.B
D. AB = A + B
Answer: Option D
Explanation:
22. In a D latch
Answer: Option A
Explanation:
A. excess 3 notation
B. gray code
C. excess 32 notation
D. 2's complement
Explanation:
24. Which of the circuits in the given figure that converts JK flip flop to T flip flop?
A.
B.
C.
D.
Answer: Option A
Explanation:
B. machine cycle time period is shorter than instruction cycle time period
C. instruction cycle time period is exactly half of machine cycle time period
D. instruction cycle time period is exactly equal to machine cycle time period
Answer: Option B
26. Consider the following registers:
Which of these 8-bit registers of 8085 μP can be paired together to make a 16-bit register?
A. 1, 3 and 4
B. 2, 3 and 4
C. 1 and 2
D. 1, 2 and 3
Answer: Option B
Explanation:
C. to write one word into and to read one word from the memory
D. either to write one word or to read one word
Answer: Option D
Explanation:
28. For a D/A converter, inputs and outputs are given. The output corresponding to digital input
01000
A. 2.0 V
B. 2.5 V
C. 3.0 V
D. 4.0 V
Answer: Option A
Explanation:
29. By placing an inverter between both inputs of an S-R flip-flop, the resulting flip-flop becomes
A. J-K flip-flop
B. D-flip-flop
C. T-flip-flop
Answer: Option B
Explanation:
A. T flip-flop
B. D flip-flop
C. JK flip-flop
D. Master-slave flip-flop
Answer: Option D
31. It is desired to route data from many registers to one register. The device needed is
A. decoder B. multiplexer
C. demultiplexer D. counter
Answer: Option B
Explanation:
A. ECL family
B. CMOS family
C. TTL family
Answer: Option C
Explanation:
A. decoder B. encoder
C. CPU D. converter
Answer: Option B
Explanation:
34. It is desired to clean up ragged looking pulsed that have been distorted during transmission from
one place to another, which of the following device will be appropriate?
A. Multiplexer
B. D/A converter
C. JK flip-flop
D. Schmitt trigger
Answer: Option D
Explanation:
A. 1100 B. 1101
C. 110 D. 1111
Answer: Option B
36. In magnetic film memory, the memory element consits of
A. plated wires
B. superconductive material
D. doped aluminium
Answer: Option C
Explanation:
A. Counter
B. Multiplexer
C. Demultiplexer
D. Flip flop
Explanation:
38. CD4010 is a
A. inverting buffer
C. NOR IC
D. NAND IC
Answer: Option B
Explanation:
A. 1579 B. 1681
C. 1881 D. 2014
Answer: Option A
Explanation:
C. 10111012 D. 11111112
Answer: Option A
41. The number of programmable 8 bit registers of 6800 are
A. 2 B. 3
C. 4 D. 5
Answer: Option A
Explanation:
42. The seven bit Hamming code received is 0010001. If even parity has been used, the correct code
is
A. 0010001 B. 1110001
C. 0110001 D. 0011001
Answer: Option D
Explanation:
Answer: Option B
Explanation:
A. 1 and 2
B. 2 and 4
C. 2 and 3
D. 1 and 4
Answer: Option B
Explanation:
Answer: Option D
46. Flash ADC is
A. serial ADC
B. parallel ADC
C. series-parallel ADC
Answer: Option B
Explanation:
A. CMOS
B. TTL
C. 4 n sec ECL
D. 8 sec ECL
Answer: Option A
Explanation:
B. 1
C. CLK
D. none of these
Answer: Option B
Explanation:
49. PROM is
Answer: Option D
Explanation:
A. 888 B. 111
C. 21 D. 27
Answer: Option C