EE370A - Monsoon 2019

Indian Institute of Technology Kanpur

Department of Electrical Engineering

Practice Problems – 3
Due: Friday 23rd August, 2019

For the problems discussed below, assume that for nMOSFETs Kn' = 200 A V-2 and VTn = 1 V, and
for pMOSFETs |Kp'| = 100 A V-2 and |VTp|= 1 V. The supply voltage used is VDD = 5 V. The
minimum size of W and L are Wmin = Lmin = 0.5 m. The capacitive load seen by the inverters
may be taken to be 10 pF. For the circuit in which these inverters are to be placed the period of
switching of the clock used is ten times the inverter tp and the activity factor is 0.1 (i.e., the
probability of energy consuming transition of the input is 0.1). Use reasonable approximation
wherever necessary in your analysis and calculations.

1. For the inverter shown in Fig. 1:

(i) Calculate the VOH, VOL, VIH, VIL and VM. Confirm whether you assumption
for the region of operation of transistor is valid after you obtain the final
result. What design changes will you make to push the parameters you have
obtained to their ideal value.
(ii) Calculate tpHL and tpLH and tp for this inverter. What will be the design
changes you may want to obtain improved performance of the inverter?
(iii) Determine the static and dynamic power dissipation for these circuits.
What design changes would you suggest to minimize power consumption by
the inverter?

2. For the inverter shown in Fig. 2:

(i) What will be your choice for Vbais if you want to achieve maximum
VOH? Give your reasons for your choice.
(ii) Calculate the VOH, VOL, VIH, VIL and VM. Confirm whether you
assumption for the region of operation of transistor is valid after you
obtain the final result. What design changes will you make to push
the parameters you have obtained to their idea value.
(iii) Calculate tpHL and tpLH and tp for this inverter. What will be
design changes you will make to obtain improved performance of the
inverter?
(iv) Determine the static and dynamic power dissipation for these
circuits. What design changes will be you make to minimize power
consumption by the inverter?
 EE370A - Monsoon 2019

3. For the inverter shown in Fig. 3:

(i) What will be your logical choice for Vbais? Give your reasons. What
will be the size of the p-MOSFET that will be reasonable?
(ii) Calculate the VOH, VOL, VIH, VIL and VM. Confirm whether you
assumption for the region of operation of transistor is valid after you
obtain the final result. What design changes will you make to push the
parameters you have obtained to their idea value.
(iii) Calculate tpHL and tpLH and tp for this inverter. What will be design
changes you will make to obtain improved performance of the inverter?
(iv) Determine the static and dynamic power dissipation for these
circuits. What design changes will be you make to minimize power
consumption by the inverter?

4. Consider the inverter shown in Fig. 4.

(i) What will be the values of W and L you will choose for your
transistors to make the PUN and PDN equally strong?
(ii) What are the VOH, VOL, VIH, VIL and VM for this inverter’s VTC?
[Notice the symmetry in the results.]
(iii) Calculate tpHL and tpLH and tp for this inverter.
(iv) Determine the static and dynamic power dissipation for these circuits.

5. Run SPICE simulation for the above inverter circuits. You may use any (open source) SPICE
simulator. Indicate the technology you are using corresponding to the SPICE parameters for the
transistors.

(a) Determine the voltage transfer characteristics as well as the key parameters in the VTC
quantitatively.

(b) Then determine tpHL and tpLH and tp for these invertors (i) no external capacitor attached; (ii) with
an external capacitor of 10 pF attached to the output.

(c) Determine the static and dynamic power dissipation for these inverters.