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Systematic Design Voltage Regulator For Vco
Systematic Design Voltage Regulator For Vco
7, AUGUST 2008
blocking conditions. There are two major sources for VCO implementation gives lower quiescent current and is more
phase noise: VCO circuit device noise and ambient noise such compatible with state-of-the-art CMOS processes.
as supply, ground, and substrate noise. The noise from supply It is desirable to have the voltage regulation on the same chip
lines can be classified as: with the VCO for higher level of integration and reduced inter-
1) switching noise and interference from other circuit blocks ference. The VCO and associated LDO could be optimized to-
on the same IC, such as dividers and modulators; gether for lower noise and a smaller circuit area with a reduced
2) thermal and noise associated with supply regulation number of external components.
circuits and power supply parasitics. In this paper, joint optimization of LDO output-referred noise
The supply noise is becoming a critical bottleneck in and PSR along with an LC-tank VCO low-frequency supply
deep-submicrometer low-noise VCOs due to the reduced power noise sensitivity is proposed. The output noise and PSR profile
supply voltage, reduced clock swings, higher order of digital of typical fully integrated LDOs are analyzed with respect to
integration, and increased number of circuits on the same IC. their loop transmission, and their impact on VCO close-in phase
It has been shown that supply noise has the highest impact noise sensitivity is optimized. With the help of the proposed
on VCO phase noise in terms of deterministic noise [1]. To loop-shaping scheme, VCO spot phase noise can be minimized
reduce the effect of supply ripple, low dropout linear regulators at a given frequency range for a given system specification.
(LDOs) [2], [3] are usually preferred for low-noise voltage Several earlier publications have analyzed VCO noise
regulation. A block-level diagram of a VCO regulated by an up-conversion. In [4], a method using impulse sensitivity
LDO with an inverting pass element is shown in Fig. 1. The function (ISF) to calculate VCO phase noise is presented.
LDO circuit includes a voltage reference, an error amplifier, a In [5], current-limited and voltage-limited VCO operation
is discussed, and various noise sources for phase noise in
Manuscript received February 4, 2007; revised August 13, 2007. First pub- differential cross-coupled LC oscillators are analyzed. The
lished February 7, 2008; last published August 13, 2008 (projected). This paper
was recommended by Associate Editor P. Carbone.
ISF is applied for flicker noise up-conversion minimization in
X. Wang is with Cadence Design Systems, Tempe, AZ 85282 USA (e-mail: [6]. The conversion from low-frequency amplitude noise to
xuwang@cadence.com). phase noise is described as AM–PM noise conversion due to
B. Bakkaloglu is with the Department of Electrical Engineering, Ira A. nonlinear capacitances in [7] and [8]. In [9] and [10], automatic
Fulton School of Engineering, Arizona State University, Tempe, AZ 85287
USA (e-mail: bertan@asu.edu). amplitude control is applied to reduce VCO amplitude variation
Digital Object Identifier 10.1109/TCSI.2008.918004 and AM–PM noise conversion. In [11], phase noise due to
1549-8328/$25.00 © 2008 IEEE
WANG AND BAKKALOGLU: SYSTEMATIC DESIGN OF SUPPLY REGULATED LC-TANK VOLTAGE-CONTROLLED OSCILLATORS 1835
(1)
is the gate oxide capacitance per unit area, and and are
the width and length of M0. The similar expression applies to
the transistor M1 drain current .
KCL on node and results in
Fig. 4. Typical nMOS cross-coupled LC-tank VCO schematic depicting device
nonlinearities and associated small-signal currents.
(9)
supply noise amplitude and the frequency pushing factor
and inversely proportional to the noise frequency . The fre- The MOS transistor drain currents and depend on the
quency characteristics of the transfer function from low-fre- operation region of these transistors, as shown in (8).
quency power supply noise to VCO phase noise is shown in For example, we can assume an LC-tank oscillator with
Fig. 3. nH, pF, A/V V, and
V. The time-domain output voltage waveforms of the
A. LC-Tank VCO Supply Sensitivity output nodes and from a circuit simulation are shown in
Fig. 5.
As seen from this analysis, the power supply noise-induced
At time instant A, the differential output and have the
VCO phase noise can be suppressed by reducing the VCO power
same value , where is decreasing and is increasing. At
supply frequency pushing factor . The VCO phase-noise con-
time instant B, the differential output and are at the same
version and frequency pushing have been viewed as AM–PM
voltage again, where is increasing and is decreasing. The
conversion due to the capacitance nonlinearities in prior lit-
time between A and B is half of the oscillation period.
erature [7], [8]. In addition to capacitance nonlinearities, the
Zooming into the waveform around time instant A, both M0
frequency pushing effect also arises from the nonlinearity of and M1 are in saturation region. At time T1, drops to and
the switching devices. Considering the simplified cross-coupled
M1 turns to the cut-off region. At time T2, increases
LC-tank nMOS VCO (without a current source) as shown in
to , and M0 moves to the linear region. M0 remains in the
Fig. 4, the drain current of the transistor M0 is given by
linear region until time T3, which is close to time instant B. At
time T3, drops back to and M0 changes back to the
saturation region. At time T4, increases to and M1 turns
to the saturation region.
Due to the nonlinear derivative equations, it is difficult to get
a closed-form solution of the oscillation. However, the trend of
the relationship between the oscillation frequency and circuit
(8) parameters can be observed with some approximations.
where is the threshold voltage, the coefficient The time duration between T2 and T3 occupies most of the
is the mobility of charge carriers, oscillation period. Between time T2 and T3, the transistor M1
WANG AND BAKKALOGLU: SYSTEMATIC DESIGN OF SUPPLY REGULATED LC-TANK VOLTAGE-CONTROLLED OSCILLATORS 1837
Fig. 6. Simplified half circuit of the VCO for the switching device in the linear
region. Fig. 7. Oscillation frequency versus and .
(10)
By analyzing the linear region and assuming is small, we
have
(11)
(15)
As seen above, the open-loop LDO system has two poles due
to a two-stage operation and one zero due to the capacitor ESR.
The open-loop transfer function can be expressed as
Therefore, the two poles of PSR are in the range (0,
) and , respectively. With the two zeros at and
(18) , the Bode plot of the PSR is shown in
Fig. 10(a). The open-loop gain is shown in the same plot.
2) In the case of a dominant pole-compensated LDO with a
where
nondominant pole coinciding with the zero from the ca-
pacitor, , the Bode plots of the PSR and
open-loop gain are shown in Fig. 10(b). The pole of PSR(s)
is at . Here we assume
.
3) In the case that the zero from the capacitor is larger than
the poles and the PSR have two real poles,
The pole is associated with the LDO output node . we have
The pole is associated with the error amplifier output node
, and the zero is caused by the bypass capacitor and
the series resistance . The loop is compensated for at the
output node . The size of the compensation capacitor
can be smaller when the output resistance of the error amplifier Starting from , the two poles are at and
is low. . If we assume , as increases
There are two paths for noise to couple from the power supply from to , the two real poles are always greater than .
to the LDO output node: one is through the pMOS pass device Therefore, the Bode plots of the PSR and open-loop gain
directly; the other is through the error amplifier to the gate of for this case are shown in Fig. 10(c).
the pMOS pass device [3]. Assuming the transconductance from 4) In the case that a big zero from the capacitor is larger than
the power supply to the output of the error amplifier is , the the poles and if the zero is big enough, eventually the PSR
PSR can be represented by will have two conjugate complex poles. Let
(19)
The PSR at low frequencies is given by When has no peaking. The PSR
will first increase and then flatten after the two complex poles.
(20) The Bode plot is shown in Fig. 10(d).
When has peaking at
The PSR at high frequencies is given by . The high peaking occurs at . The
peaking frequency is at .
(21) Here, is the open-loop unity gain frequency, and we as-
sume and . The Bode plots of the PSR and
The PSR has two zeros at and (1- and two open-loop gain are shown in Fig. 10(e).
poles determined by the denominator B. Output-Referred Noise of LDOs
Due to a large output pass transistor size and output current,
(22)
the pass transistor transconductance is usually large. The
pass transistor noise density referred to the transistor gate is so
The detailed PSR frequency response for different open loop small that it can be ignored in the noise analysis. In the example
zero-pole locations can be discussed as follows. LDO design, the pass transistor only contributes 0.0002% to the
1) In the case of a typical dominant pole-compensated LDO total LDO output noise. Therefore, there are four noise sources
with a finite zero from the capacitor , we for the LDO, as shown in Fig. 11: the reference voltage noise,
have input-referred error amplifier noise, resistor noise, and re-
sistor noise.
A low-noise voltage reference is required for a low-noise
LDO design. It is not trivial to filter out the flicker noise from
the reference without a low external filter pole. In addition to
1840 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 7, AUGUST 2008
Fig. 10. Bode plot of pMOS LDO open-loop gain, PSR, and output noise for different pole and zero locations.
(23)
(24)
(25)
Fig. 12. Bode plot of VCO LDO power supply sensitivity and LDO PSR.
As shown in (26), the LDO output noise spectrum is shaped 3.1 mA for the pMOS VCO and 1.1 and 3.4 mA for the nMOS
by VCO. Due to the high oscillation frequency and low re-
sistance, a large portion of this high-order harmonic current is
provided by the capacitor . Therefore, only a small portion
of the high-order harmonic current content travels through the
pass device. This high-order harmonic current can up-convert
(27) the low-frequency power supply noise and LDO noise to high
The spectral profile of the LDO output thermal noise can frequency which can be down-converted to the VCO oscillation
be plotted with respect to different pole and zero locations, as frequency by the VCO’s switching devices. However, this effect
shown in Fig. 10. is not significant because the pass device high-order harmonic
current is only a small portion of the total current.
IV. LDO DESIGN FOR LOW-NOISE VCOS
Utilizing the ac analysis from the previous session, a high
In the proposed approach, we presume that the LDO is dedi- open-loop zero may result in peaking of the PSR and output
cated to VCO and associated circuitry, including frequency dou- noise; a low can avoid the peaking and provide good PSR and
blers and LO buffers. Therefore, the LDO is optimized around output noise at low frequencies. However, the PSR and output
the VCO load condition. In case the VCO is adjusted for desired noise at high frequencies worsens with a low . The location
phase noise and power consumption, the LDO needs to be de- of can be adjusted by the series resistance , which is
signed to be able to handle the load change. inversely proportional to . The series resistance should
Assuming , the PSR of the LDO at high be optimized for PSR and noise specification of the VCO.
frequencies can be defined as The overall phase-noise sensitivity to global power supply
noise is the combination of the LDO PSR and VCO phase noise
sensitivity. The low-frequency power supply-induced VCO
phase noise has a 20 dB/dec dependency to the offset fre-
(28) quency . This frequency dependency can be combined with
the LDO PSR, as discussed in Section III, to form the overall
The pass device transconductance increases with the phase noise sensitivity to power supply noise. The plots of the
square root of the increasing load current. Therefore, the overall sensitivity with respect to different LDO ac responses
high-frequency PSR gets worse when the load current in- are shown in Fig. 12. The design choice will be made based on
creases, and the same analysis applies to the LDO output noise. the phase-noise specification of the given power supply noise
As the VCO oscillates, the current drawn from the LDO con- profile. Either spot noise for critical points or integrated phase
tains both dc and even harmonics of the oscillation frequency. noise can be used for the desired band of rejection.
The magnitude of the even harmonic components of the cur- As discussed in Section II, the VCO power supply-induced
rent waveform depends on the VCO oscillation waveform. In phase noise can be reduced by lowering the VCO supply fre-
the implemented designs, the transient currents are 1.5 mA to quency pushing factor. However, there is a tradeoff between
1842 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 7, AUGUST 2008
phase noise is shown in Fig. 17. The VCO spot phase noise from
these two cases is within 0.2-dB error margin, indicating that the
phase-noise contribution from the LDO noise is much less com-
pared with the contribution from the VCO internal noise.
VI. CONCLUSION
In this paper, the design issue of LDO-regulated low-noise
LC-tank VCO has been discussed. The power supply-noise-in-
duced VCO phase noise was analyzed from VCO power supply
frequency pushing. The frequency pushing effect arises from
both capacitance nonlinearities and switching device nonlinear
operations. The VCO power supply frequency pushing and
phase noise AM-PM conversion factor can be lowered by
decreasing the switching device width. The frequency char-
acteristics of LDO PSR and noise were analyzed in detail
regarding the zero and poles of the LDO open loop gain.
Fig. 16. Measured LDO PSR and improvement of VCO phase-noise sensitivity The tradeoff between high-frequency and moderate-frequency
to power supply noise.
LDO PSR and output noise can be made by tuning the series
resistance of the bypass capacitor. The LDO and VCO should
be designed together to meet the phase-noise specifications for
a given power supply noise profile.
ACKNOWLEDGMENT
The authors would like to thank Dr. T. Copani for valuable
technical discussions and suggestions.
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[12] V. Kratyuk, I. Vytyaz, U.-K. Moon, and K. Mayaram, “Analysis of Bertan Bakkaloglu (M’94) received the Ph.D.
supply and ground noise sensitivity in ring and LC oscillators,” in Proc. degree from Oregon State University, Corvallis, in
IEEE Int. Symp. Circuits Syst., May 23–26, 2005, no. 6, pp. 5986–5989. 1995.
[13] A. Maxim, “A multi-rate 9.953-12.5-GHz 0.2- m SiGe BiCMOS LC He then joined the Mixes Signal Wireless Design
oscillator using a resistor-tuned varactor and a supply pushing cancel- Group, Texas Instruments Incorporated, Dallas, TX,
lation circuit,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 918–934, where he was involved with analog, RF, and mixed-
Apr. 2006. signal front-ends for wireless and wireline commu-
[14] D. Leeson, “A simple model of feedback oscillator noise spectrum,” nication integrated circuits. He was a Design Leader
Proc. IEEE, vol. 54, no. 2, pp. 329–330, Feb. 1966. involved with system-on-chip designs with integrated
[15] “SpectreRF User Guide, Product Version 5.0,” Cadence Design Sys- battery management and RF, analog baseband func-
tems, Inc., Sep. 2003. tionality. In 2001, he joined the Broadband Commu-
nications Group, where he was involved with cable modem analog front-end
Xuejin Wang received the B.S. and M.S. degrees designs and gigabit Ethernet front-ends. In 2004, he joined the Electrical En-
from Tsinghua University, Beijing, China, in 1999 gineering Department, Arizona State University, Tempe, as an Associate Pro-
and 2001, respectively. He is currently working fessor. He holds three patents. His research interests include RF and power am-
toward the Ph.D. degree at Arizona State University, plifier supply regulators, RF synthesizers, high-speed RF data converters, and
Tempe. RF built-in self-diagnostic circuits for communication integrated circuits and
His research interests include low-noise VCOs and antennas.
LDOs. He was with Neolinear, Inc., from 2003 to Dr. Bakkaloglu has been a Technical Program chair for the International Sym-
2004. He is now with Cadence Design Systems, Inc., posium on Circuits and Systems (ISCAS) and IEEE Microwave Theory and
Tempe, as a Lead Design Engineer. Techniques (MTT)/RF Integrated Circuit (RFIC) Conference.