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MOS in
MOS in
MOS in
DYNAMIC CHARACTERISTICS
extrinsic
parasitic
caps
n = fan-out ≥ 1
# worst
Cload = C #
dbn
+ #C#
dbp
+#C#gdn
+#C# gdp
+# C int
+ nCgb ≈# C#
i≈i
dbn
#
+ C dbp + Cint + n Cgb case
Cgb = Cgbn+ Cgbp
Kenneth Intrinsic Parasitic
R. Laker, University Caps updated 26Feb15
of Pennsylvania, 2
Cload ≈ Cdbn + Cdbp + Cint + nCgb where n = fan-out ≥ 1
0 t
VDD
V50% = VDD/2
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 4
VDD
VDD
V50% = VDD/2
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 5
VDD
2. DESIGN: For given specs for the propagation delays τPHL and/or τPLH,
OR the rise/fall times τrise and/or τfall + Cload, determine the MOS inverter
schematic.
METHODS:
1. Average Current Model
8V HL 5V OH −V 50%p 6
>PHL ≈C load =C load
I avg , HL I avg , HL
2. Differential Equation Model
d V out d V out
i C =C load ⇒ ∫ dt=C load ∫
dt iC
where dt≈> PHL Assume
Vin ideal
3. 1st Order RC Delay Model
>PHL≈0.69 C load∗Rn
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 7
CALCULATION OF PROPOGATION DELAY TIMES
VDD
0, 0 0, VDD/2)]
(0.9VDD– 0.1VDD)
0, 0, 0.9VDD)]
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 9
Calculating Propagation Delays By Solving
the Circuit Differential Equation
iDP - iDn
i Dp≈0
V out =V DD −V T0n
V50%= VDD/2
d V out −d V out
C load ≈−i Dn ⇒ dt =C load 5 6
dt i Dn
t sat
V50%= VDD/2
d V out −d V out
C load ≈−i Dn ⇒ dt =C load 5 6 t sat
dt i Dn
0.5VDD -
tsat VDD VDD
- 0.5V
Vout = V
tsat 50% DD
VDD VDD/2
VDD VDD/2
VDD
VDD VDD VDD/2
VDD
tt=t
=t'50% −C load V out =0.5 V DD
> PHL=∫t=t dt≈ ∫V
1
dV out
0 kn out =V DD
5V DD −V T0n 62
2
2C load 50.5V DD 6
.≈
k n 5V DD −V T0n 62
C load V DD
> PHL≈ 2
≈ R n C load
k n 5V DD −V T0n 6
t sat
Δ is less than 10%
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 18
VDD = 5 V, VGSn = 5 V and VDSn ≥ 4V => iDn = iDnsat = 5mA
VDDV
V50% = 0.5 VDD = 2.5
1 pF 2V 455−16V
.= −3
[ 1ln 5 −16]
0.625 x 10 A/V 55−16V 55−16V
2
5V
1 pF 2 16
.= −3
[ 1ln 5 −16]=0.52 ns
0.625 x 10 A/V 546 4 5
F F C /V
UNITS: = V= V =s
A/V A C /s
= 0.52 ns
DD DD
0.99 mA A
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 22
Example 6.2 cont.
-3
4.04 ns
0.99 x 10 A
DD
tsat
Vout = 4.0V
tsat -6.25 x 10 -10
s/V Vout |
Vout = 4.5V
tsat
0.31 ns
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 23
Example 6.2 cont.
0.31 ns
tsat
tsat
Vin = 5 V
0.5 V
tsat
0.5 V
Vin = 5 V
3.39 ns
VDD
V50%= VDD/2
i Dn≈0
tsat
d V out d V out
C load ≈i Dp ⇒ dt =C load 5 6
dt i Dp
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 25
CMOS Static Inverter Characteristics Recall
VDD
i Dn≈0
V50%= VDD/2
tsat
d V out d V out
C load ≈i Dp ⇒ dt =C load 5 6
dt i Dp
t=t 50p V out =V50% 1
> PLH =∫t=t dt=C load ∫V
50% 50p
5 6dV out =C load R eff , LH
0 out =0 i Dp
−V T0p 1 V50% 1
.=C load ∫0 6 dV out 1C load ∫−V 5
50p
5 6dV out = t - t
i Dp T0pi Dp 50% 0
VDD
VDD VDD VDD/2
.≈ R p C load
VDD
Recall from static CMOS Inverter:
C load V DD
> PLH ≈ 2
≈ R p C load
tsat k p 5V DD −∣V T0p∣6
2. DESIGN: For given specs for the propagation delays τPHL and/or τPLH,
OR the rise/fall times τrise and/or τfall + Cload, determine the MOS inverter
schematic.
METHODS:
1. Average Current Model
8V HL 5V OH −V 50%p 6
>PHL ≈C load =C load
I avg , HL I avg , HL
2. Differential Equation Model
d V out d V out
i C =C load ⇒ ∫ dt=C load ∫
dt iC
st
Assume
3. 1 Order RC Delay Model Vin ideal
>PHL ≈0.69 C load ∗R n
W =n W
=> 5 L 6 = = 5 L 6
p p n
Wn C load V DD
≈
L n >PHL =n C ox 5V DD −V T0n 62
C load V DD Wp
> PLH ≈ ≈ R p C load k p == p C ox
2 Lp
k p 5V DD −∣V T0p∣6
Wp C load V DD
≈
L p > PLH = p C ox 5V DD −∣V T0p∣62
8.11
8.11 µm = 10.81 µm
(Wn, Wp).
Cdbn (Wn) = [Wn (Y + xj)] Cj0n Keqn + (Wn + 2Y) Cjswn Keqn(sw)
Cdbp (Wp) = [Wp (Y + xj)] Cj0p Keqp + (Wp + 2Y) Cjswp Keqp(sw)
Cload = α0 + αnWn + αpWp
α0 = 2YCjswnKeqn + 2YCjswpKeqp + Cint + Cgb
αn = (Y + xj)Cj0nKeqn + CjswnKeqn
αp = (Y + xj)Cj0pKeqp + CjswpKeqp
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 40
Design for Propagation Delays Using More Realistic Model for Cload cont.
µp
const.
1 =p W p
where R = Wp/Wn = constant (Recall: V th ⇒ = when Lp=Ln)
k R =n W n
5.0
4.5
4.0
3.5
3.0 minimum
2.5
2.0
0 4 8 12 16 20
nMOS Channel Width Wn (µm)
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 45
Taking Into Account Non-Ideal Input Waveform
ideal Vin
non-ideal Vin
Vout to ideal Vin
Vout to non-ideal Vin
Example
Unit
Transistors
κnCd
Rn = Run/κn
κn ON/
OFF
κnCg
κnCd
Where Wn = κnWun
κn ≥ 1, usually κn = 1
C load V DD
Recall: > PHL≈ 2
≈0.69 R n C load
k n 5V DD −V T0n 6
V DD L un
R n=R un≈ 2 iff κn = 1
0.69 =n C ox W un 5V DD−V T0n 6
C load V DD
Recall: > PHL≈ 2
≈0.69 R p C load
k p 5V DD −V T0p 6
R up V DD Lup
R p= ≈
; p 0.69 = p C ox ; p W up 5V DD−∣V T0p∣62
Where, recall Lup = Lun and Wup = Wun
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 50
pMOS 1st Order RC Delay Model – Equiv. Rp → Rn
ASSUME: bulk and s at VDD
s
κpCd
Rp = Rup/κp
W p =n W n
ON/
5 6= 5 6
κp Lp = p Ln
OFF
κpCg L un=Lup
κpCd
Where Wp = κpWup W un =W up
d
κp ≥ 1, usually κp = µn/µp
usually κn = 1
V DD Lup V DD Lun
R p≈ 2 R n≈ 2
0.69= p C ox W p 5V DD−∣V T0p∣6 0.69 =n C ox W un 5V DD−V T0n 6
R up V DD L up
R p= ≈
;p =n 2
0.69 = p C ox W up 5V DD −∣V T0p∣6
=p
.=R n Iff |VT0p| = VT0n SYMMETRIC INVERTER
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 51
st
1 Order Delay Model - τPHL
Estimating τPHL VDD VDD
Cs = Cd
κpCd
1,κp
2R
R = /κ
nu R p
n = fanout
p n
VDD
VDD
VDD VDD nκp Cg
κpCd
κp κp
1,κ
Y 2 Y
A
1 1
1,κ p
1 Rn Cd nCg
where Wn=Wunit => κn=1, Rn=Run τPHL
Wp = κpWunit
κp = µn/ µp = 2 Cd
Rp = Rpu/κp = Rn
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 52
st
1 Order Delay Model - τPHL
Estimating τPHL
Reff,HL = Rn = Rnu
Reff,LH = Rp = Rpu/κp = Rn
κpCd
VDD
Rp VDD
nκpCg
nκpCg κpCd
κpCd
Y
Y
Rn/κ
Rnn CndC
κ
nC
κnCg
Cd nCg
Rn
Cload = (1 + κp)(Cd + nCg)
Rp = Rn
τPHL
Reff,LH = Rp = Rpu/κp = Rn
κpCd
VDD
Rp = Rn VDD VDD
nκpCg
Rp = Rn κpC
τPLH
κpCd nκpCg
Y
Y κnC
C
nC
κnCg
Cd nC
Rn Cg
Cload = (1 + κp)(Cd + nCg)
> PHL
Differential
Equation
Model > PLH
C load V DD C load V DD
APPROX: > PHL≈ > PLH ≈ 2
k p 5V DD −∣V T0p∣6
2
k n 5V DD −V T0n 6
= SYM INV
t
τPHL2 τPHL1 τPHL3
τPLH3 τ τPLH2 PLH1
where
1 1
f= =
T 6 >p
Ideal FF value: FF = 1
FF -> Increase as t/h -> Increase, W/h <- Decrease and W/L Increase
(See plot of FF in Fig. 6.18 of V3 & V4 of Text) Actual(1FF< value:
FF < 200)
1 < FF ≤ 20
(PP + FF)
0.3 = m
0.9 = m
0.6 = m
2
0.6 = m C gb =1800 aF / = m
0.3 = m
0.6 = m
0.3 = m
Cm2d 0.6 = m
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 61
DIGITAL CIRCUIT PATH DELAY
O1
3 4
2
5 O2
1
S1 S2
Step Source 2
> PHL 1 −> / R C V DD−V 50 %p 1
0 0 t e PLH 1
= 1
=
V DD 2
V 1 506=V DD
V6(0) C6 C7 C8
1. Lump total wire resistance of each wire segment into single Rj between nodes in network.
2. Lump total capacitance into single node capacitor to GND.
3. Model RC tree Topology:
(a) Single input node “S”;
(b) All Ci between node i and GND;
4. Unique resistive path from source node S to any node k (k ≠ S).
C1 C2 C3 CN
Let the RC Ladder Network be uniform, i.e. Ri = rL/N for all i ≤ N and Cj = cL/N
for all j ≤ N such that
N j 2
cL rL L 2 N 11
> DN =∑ 5 6 ∑ 5 6= 2 5rc12 rc13 rc1...1N rc6=rc L 5 6
j=1 N k =1 N N 2N
rc L 2
For large N, as N 3 ∞ (distributed RC line) > DN 3
2
> PLH =0.69 > DN ≈0.35 r c L 2
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 68
Practical Interconnect Length Rule-of-Thumb
> PHLinv =0.69C load R n > PLHwire =0.35 r c L 2
Let the goal be for the layout to enable > PLHtotal ≈> PLHinv
L≪
4
> PLHinv
0.35 r c
=
0.35 r c4
0.69 C load R n
L≤
4
1 > PLHinv
=
10 0.35 r c 10 4
1 0.69 C load R n
0.35 r c
vin
vout
0
1 T
P avg = ∫0 v 5t 6i 5t 6dt
T
v DSn 5t 6=v out 5t 6 v SDp 5t 6=V DD −v out 5t 6
1 T /2 1 T dt
P avg ≈ ∫0 v DSn 5t 6 i Dn 5t 6 dt1 ∫T /2 v SDp 5t6 i Dp 5t 6 dt
T T
dv out dv out
i Dn 5t 6=−C load i Dp 5t 6=C load
dt dt
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 71
1 T /2 d v out 1 T d v out
P avg ≈ ∫0 v out 5−C load 6dt 1 ∫T /2 5V DD −v out 65C load 6 dt
T dt T dt
vin, vout
VDD
1 0 1 V
P avg ≈ ∫V −C load v out 5t 6dv out 1 ∫0 C load 5V DD −v out 5t 66 dv out
DD
T DD T
2 v out =0 2 v out =V DD
1 v out 1 v out
.= [−C load ] 1 [C load 5V DD v out − 6]
T 2 v out =V DD T 2 v out =0
1 2
.= C load V DD
T P avg ≈C load V 2DD f
f = operating frequency or switching frequency
Units calculation
2 Q −1
f = F∗V ∗Hz= ∗V 2∗s
2
P avg ≈C load V DD In = A∗V =W
General:
V
C load 3C total
Ctotal = total chip capacitance
standard
CMOS
logic on
INV1 Buffer
die CLOAD
standard
CMOS
logic on
INV1 Buffer
die CLOAD
Cin
standard
CMOS INV1
logic on
die CLOAD
CLOAD
when i = N: CloadN = aN Cload0 = aN (Cd + aCg) => let CLOAD = aN(aCg) = aN+1Cg
ln 5C LOAD / C g 6 N is rounded up to nearest
CLOAD/Cg = a N+1
=> N = −1 integer value.
ln a
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 78
Super-Buffer to Drive Large CLOAD cont.
CLOAD
CLOAD
NOTE: ALL inverters Stage-0 through Stage-N have the same gate delay
> PHL 1> PLH C load
> p= =7
2 W
Let τ0 = gate delay for INV1 (with a = 1) in a ring oscillator with load Cload = Cd + Cg
>d0 C load0 /W 0 Cdd1a C g
C Cdd 1a C g
For Stage-0: = = ⇒> p0 =>0
>0 5C Cdd 1C g 6/ W 0 C dd 1C g Cdd 1C g
> pN C load1 /a N W 0 5a N C
Cdd 1a N 11 C g 6/a N Cd 1a C g
C
For Stage-N: = = ⇒ > pN =>0 => p0
>0 5C
Cdd1C g 6/ W 0 C dd
1C g C dd
1C g
Cdd 1a C g Choose N and a
TOTAL DELAY >total =5 N 116⋅> p0 =5N 116⋅>0⋅ C
C dd 1C g to minimize τtotal
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 80
Super-Buffer to Drive Large CLOAD cont.
CCdd 1a C g
>total =5 N 116⋅>0⋅ ln 5C LOAD /C g 6 CCd 1a C g
CCdd 1C g >total = ⋅>0⋅
ln a C dd 1C g
ln 5C LOAD / C g 6
N 11=
ln a Wni = aiWn0 Wpi = aiWp0
TO MINIMIZE τtotal:
d >total C LOAD −1/a CCdd1a C g 1 Cg
=>0 ln 5 6⋅[ 1 ]=0
da Cg 2
5ln a6 C Cdd 1C g ln a CCdd1C g
=0
Cdd
aopt [ln a opt −1]=
Cg
Cd ln a opt =1⇒ a opt =e 1 =2.718
ln 5C /C g 6
Since Cd > Cg, Cd =N0=is onlyLOAD −1 N
an academic is rounded
special up to nearest
case.
integer value.
ln aopt
Since Cd > Cg, then Cd = 0 is only an academic special case.
aaopt ≥ e=2.718
opt 2e=2.718