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16 SequentialVerilog PDF
16 SequentialVerilog PDF
16 SequentialVerilog PDF
◆ Logistics ◆ wire
■ HW5 due today ■ Connects components together
■ HW6 due next Friday
◆ reg
■ Saves a value
◆ Last lecture µ Part of a behavioral description
■ Finish basic latches and Flip-flops ■ Does NOT necessarily become a register when you synthesize
■ Registers µ May become a wire
µ Shift registers
µ Counters ◆ The rule
■ Basic state machine design ■ Declare a variable as reg if it is a target of an assignment
statement inside an always block
◆ Today µ Continuous assign doesn’t count
■ Sequential Verilog
Synthesis examples
wire [3:0] x, y, a, b, c, d;
==
==
b
b
CSE370, Lecture 16 23 CSE370, Lecture 16 24
Constants: 32 bits, decimal Truncation
wire [7:0] a = 8’hAB;
• wire [7:0] foo = 127; // synthesis warning!
wire b; // oops! forgot width
• wire [7:0] foo = 8’d127;
wire [7:0] c;
• wire [7:0] foo = 8’b11111111;
assign b = a; // synthesis warning if lucky.
• wire [7:0] foo = 8’hff;
assign c = a;
• wire [7:0] foo = 8’hFF;
• watch out: 1010 looks like 4’b1010!
within a block,
blocking
assignments,
are in order
CSE370, Lecture 16 29