Professional Documents
Culture Documents
Layout Tutorial
Layout Tutorial
Layout Tutorial
1) Consider the schematic below. M=2 for each transistor, and W=3µm. It means we have:
NMOS: 2x3 µm
PMOS: 2x3 µm
2) Open LayoutXL
3) Do not import the transistors automatically. In the LayoutXL window, click on Create
pick from schematic, and import the pins.
4) Instantiate the transistors manually. Connect the gates of the nmos transistors using the
poly layer. Drains should be connected together through M1, and also sources should be
connected in the same manner. Do the same for PMOS transistors.
Each NMOS in the Layout:
Please note that you need to include the body connection yourself. Here is the final layout:
Vdd contact
Gate contact
gnd contact
5) Verify DRC
DRC clean
6) Verify extract
7) Verify LVS
Pay attention that the provided layout is not common centroid. To realize that, you can change
the placement and arrangement of the transistors while keeping the gate, source and drain
connections.