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Analog performance of double gate junctionless tunnel field effect transistor

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Vol. 35, No. 7 Journal of Semiconductors July 2014

Analog performance of double gate junctionless tunnel field effect transistor

M. W. Akram1; Ž and Bahniman Ghosh1; 2; Ž
1 Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, Uttar Pradesh, 208016, India
2 Microelectronics Research Center, 10100 Burnet Road, Bldg. 160, University of Texas at Austin, Austin, TX, 78758, USA

Abstract: For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field
effect transistor (DG-JLTFET) and the results are compared with the conventional n-type double gate tunnel field
effect transistor (DG-TFET) counterpart. Using extensive device simulations, the two devices are compared with
the following analog performance parameters, namely transconductance, output conductance, output resistance,
intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is
found to have significantly better analog performance as compared to DG-TFET.

Key words: junctionless field effect transistor; tunnel field effect transistor; subthreshold slope
DOI: 10.1088/1674-4926/35/7/074001 PACC: 7340Q; 7280C; 7340L

In this paper, for the first time, we investigate the analog

1. Introduction
The metal oxide semiconductor field effect transistors
(MOSFETs) suffer increased short channel effects (SCEs) and
higher leakage current when it is continuously scaled down.
This is due to the fact of reduced gate controllability over
the channelŒ1 3 . Due to the excellent immunity of SCEs,
double-gate or multi-gate devices offer better scalability op-
tionsŒ4 6 . However, the device with a channel length of less
than 22 nm still shows significant drain induced barrier low-
ering (DIBL) and threshold voltage roll-off effects. Recently,
tunnel field effect transistors (TFETs)Œ7 11 have been given
a lot of attention as they provide a subthreshold slope (SS)
of less than 60 mV/dec at very low VDD ; this is because of
the different conduction mechanism. TFETs also show very
much less SCEs as compared to the inversion-mode device
(MOSFETs)Œ1 3 . However, TFETs also suffer because of a
low ON-currentŒ1; 12; 13 . In the sub-22 nm regime (for both
conventional MOSFETs and the conventional TFETs), fabri-
cation of such a small device becomes very challengingŒ3 .
Very recently, a new transistor called the junctionless field
effect transistor (JLFET)Œ14; 15 has been proposed and suc-
cessfully fabricated, and is based on Lilienfeld’s first tran-
sistor architectureŒ16 . This device is simpler to fabricate and
has less variability and better electrical properties than MOS-
FETŒ14; 15; 17 21 ; however, the SS is still limited, as in the
MOSFETsŒ14; 15 . To overcome the limit of the subthreshold
slope and fabrication challenge, recently a new transistor called
the junctionless tunnel field effect transistorŒ22 has been pro-
posed, which gives the combined advantages of both the tech-
nologies, namely, junctionless field effect transistors and the
tunnel field effect transistors. Using 2D device simulation, the
author in Ref. [22] has achieved ION of 1 mA/m, a point
subthreshold slope of 33 mV/decade, and an average sub-
threshold slope of 34 mV/decade at a supply voltage of 1 V
and at room temperature for channel length of 20 nm, an iso-
lation thickness of 2 nm, and high-k gate dielectric material as
TiO2 .
performance of n-type double gate junctionless tunnel field ef-
fect transistor (DG-JLTFET), and the results are compared with
the conventional TFETs. The performance evaluation para-
meters under consideration are drain current (ID /, transconduc-
tance (gm /, output conductance (gd /, output resistance (RO /,
intrinsic gain (gm /gd /, total gate capacitance (CGG /, and unity
gain frequency (fT /.
2. Device structure and their operation
Figure 1 shows the simulated n-type double gate tun-
nel field effect transistor (DG-TFET) structureŒ1 . The device
structure parameters used for the simulation of DG-TFET are
shown in Table 1. Here, silicon (Si) is taken as the channel ma-
terial with a channel length of 20 nm. The thicknesses of silicon
film and gate oxide are 5 nm and 2 nm, respectively. To get an
optimized value of ON-current, OFF-current, and ION /IOFF ra-
tio, and also to compare the results of n-type double gate tunnel
field effect transistor (DG-TFET) with the n-type double gate
junctionless tunnel field effect transistor (DG-JLTFET) struc-
tureŒ22 , the optimized doping levels for the source, intrinsic,
and drain regions are chosen to be 5  1019 (p-type), 1  1015
(p-type), and 1  1019 (n-type) atoms/cm3 , respectively. Two
devices are compared for the same value of threshold voltage
(VTH /Œ23 . To get improved results of the ON-current (ION /,
OFF-current (IOFF /, and the subthreshold slope (SS), the high-
k dielectric material HfO2 with a dielectric constant value of 29
is taken as the gate oxide material. For the gate metal contact, a
work function of 4.15 eV is chosen to achieve the comparable
threshold voltage of 0.40 V, compared to the DG-JLTFET.
The device parameters of DG-TFET are taken to be the same as
those proposed in Ref. [1], except for 20 nm of channel length
and doping level for the source region of 5  1019 atoms/cm3
(p-type), instead of 50 nm of channel length and doping level
of 1  1020 atoms/cm3 (p-type) for the source region, just in
order to compare the results of DG-TFET with the results of
DG-JLTFET. The double-gate technology is used to improve

† Corresponding author. Email: mwakram@iitk.ac.in, bghosh@utexas.edu

Received 4 January 2014, revised manuscript received 29 January 2014 © 2014 Chinese Institute of Electronics

074001-1
J. Semicond. 2014, 35(7) M. W. Akram et al.

Fig. 1. The simulated n-type double gate tunnel field effect transistor Fig. 2. The simulated n-type double gate junctionless tunnel field ef-
(DG-TFET)Œ1 . fect transistor (DG-JLTFET)Œ22 .

the controllability over the channel as compared to the single- Table 1. Parameters used for the DG-TFET simulation.
gate technologyŒ1 . Parameter DG-TFET, Value
The simulated DG-JLTFET is shown in Fig. 2. In this Gate length (LG / 20 nm
case, Si is also taken as the channel material, throughout the Silicon thickness (Tsi / 5 nm
source, intrinsic, and drain regions with a doping concentra- Gate dielectric thickness 2 nm
tion of 1  1019 cm 3 (n-type). Table 2 shows the parameters Width of the device 1 m
Drain doping concentration 1  1019 cm 3 , n-type
used for the simulation of DG-JLTFET. The channel length of
Channel doping concentration 1  1015 cm 3 , p-type
DG-JLTFET is taken to be the same as in the DG-TFET. The
Source doping concentration 5  1019 cm 3 , p-type
thicknesses of silicon film and gate oxide are 5 nm and 2 nm, Gate material work function 4.15 eV
respectively. 2 nm of isolation layer between the two gate elec- Supply voltage (VDD / 1V
trodes (gate (G) and P-gate (PG)) is taken, which works to iso- High-k gate dielectric material 29
late the gates and as a spacer. Here also high-k gate and P- permittivity
gate dielectric material with a dielectric constant value of 29
are taken to get an optimized value of ION , IOFF , and also the
subthreshold voltage (SS). The simulated device structure is Table 2. Parameters used for the DG-JLTFET simulation.
a lateral n-type double gate junctionless field effect transistor Parameter DG-JLFET, Value
(DG-JLFET)Œ1 , which uses two isolated gates (gate, P-gate) Gate length (LG / 20 nm
with different metal work-functions. This makes the layer be- Silicon thickness (Tsi / 5 nm
neath the gates intrinsic and p-type. We have taken 4.3 eV and Isolation thickness (Tiso / 2 nm
5.93 eV as the work function for the gate and P-gate electrodes, Gate dielectric thickness 2 nm
P-gate dielectric thickness 2 nm
respectively. The value of work function 5.93 eV corresponds
Width of the device 1 m
to the metal platinum (Pt)Œ24 .
Drain doping concentration 1  1019 cm 3 , n-type
The simple knowledge applied here is to translate the (NC – Channel doping concentration 1  1019 cm 3 , n-type
N –NC / drain, channel and source of JLFET into an (NC –I–
C
Source doping concentration 1  1019 cm 3 , n-type
PC / structure of a JLTFET without any physical doping. In- Gate material work function 4.3 eV
trinsically, the proposed device would show less variability P-gate material work function 5.93 eV
and short channel effects compared to the conventional TFET, Supply voltage (VDD / 1V
since the proposed device is principally based on the junction- High-k gate dielectric material 29
less channel. The shortcomings of junctionless tunnel field ef- permittivity
fect transistor concepts is that it would require a few more fab- High-k P-gate dielectric mate- 29
rication steps, such as the formation of an extra gate, gate con- rial permittivity
tact, and an isolation layer.
This model has already been used in other works to predict
3. Simulation results the performance of TFETŒ1 . To take the effect of the high
doping in the channel, a band-gap-narrowing model (BGN)
In this section, we discuss the simulation results ob- is used. The trap assisted tunneling model (TAT) given by
tained using a 2D device simulator, Silvaco Atlas, version SchenkŒ25; 26 is used to include the interface trap effect on
5.15.32.RŒ25 . Here we have shown the analog performance of BTBT for the devices. Consideration of an interface trap (or
an n-type double gate junctionless tunnel field effect transis- defect) effectŒ25; 26 and the presence of a high impurity atom
tor and the results are compared with the conventional n-type in the channel is modeled with the Shockley-Read-Hall re-
double gate tunnel field effect transistor counterpart. To take combination model (SRH). The complete mobility model for
account of the band-to-band tunneling process along the lateral concentration dependent, parallel electric field dependent, per-
direction of the device, we have used the non-local band-to- pendicular electric field dependent, and temperature dependent
band tunneling (BTBT) model available in Silvaco AtlasŒ25 . model (CVT)Œ25 is used. The gate leakage current model is

074001-2
J. Semicond. 2014, 35(7) M. W. Akram et al.

Fig. 3. Drain current (ID / versus gate voltage (VGS / for the DG-TFET Fig. 4. Transconductance (gm / versus VGS for the DG-TFET and DG-
and DG-JLTFET at drain voltage (VDS / D 1 V. JLTFET at VDS D 1 V.

also enabled, and to include the effect of the quantum tun-

neling current through an oxide, the direct quantum tunnel-
ing model for electrons, holes, and the band-to-band tunneling
model (QTUNN) available in SilvacoŒ25 is used.

3.1. Transfer characteristics

Figure 3 shows the subthreshold characteristics (ID ver-
sus VGS / for the DG-TFET and DG-JLTFET at VDS D 1 V.
Two devices are compared for the comparable value of the
threshold voltageŒ23 . The threshold voltages of two devices
are matched primarily by adjusting the work function differ-
ence of gate to channel and p-gate to channel. From the figure,
we observe that for the comparable value of threshold volt-
age, the DG-JLTFET gives better performance in terms of ON-
current and also OFF-current. Moreover, it is also found that
the point subthreshold slope (SS) of the DG-JLTEFT is bet-
ter than the DG-TFET. The point subthreshold slope (SS) of
DG-JLTEFT and DG-TFET are found to be 35.36 mV/decade
and 40.38 mV/decade, respectively. The threshold voltage is
extracted using the constant-current method of value 10 7
A/mŒ1 . The ON-current (ION / and OFF-current (IOFF / are
measured at the supply voltages of (VD D 1 V, VMG D 1 V)
and (VD D 1 V, VMG D 0 V), respectively. The point SS is
measured from the (inverse of the) maximum slope of the log
of the drain current versus gate voltageŒ1; 14 .
The effect of gate voltage variation on transconductance
(gm / is shown in Fig. 4. The value of transconductance is cal-
culated, as given in Eq. (1)Œ27 34 . The value of transconduc-
tance (gm / is directly extracted from Fig. 3 using Eq. (1). The
gm is an important analog performance parameter, which is a
measure of the amplification given by that device. The higher
gm means more efficient amplification and more suitability for
analog applicationsŒ32 34 . ID gives the amount of power dis-
sipated to obtain that amplification. From the figure, it is ob-
served that for the comparable value of threshold voltage, the
transconductance (gm / of the DG-JLTFET is better than that of
the DG-TFET counterpart. As the gate voltage increases from 0
to 1 V, continuous increase in transconductance of both the de-
vices is observed, this is because of the continuous increase in
the differential drain current of both the devices, keeping the
differential gate voltage constant. Similar kinds of transcon-
Fig. 5. ID versus VDS for the DG-TFET and DG-JLTFET at VGS D
1 V.
ductance (gm / characteristics are also observed in Refs. [12,
32–34].
gm D @ID =@VGS : (1)
3.2. Output characteristics
The output characteristic (ID versus VDS / is shown in
Fig. 5. From the figure, we observed that as the drain voltage
increases from 0 to 1 V, the drain current also increases and fi-
nally saturates; the effect of saturation occurs because of the ve-
locity saturation, and also pinch-off mechanism for both of the
devices. Higher ON-current for the DG-JLTFET is observed
compared to the DG-TFET; this is because of the higher tunnel
coupling effect offered by the DG-JLTFET. The reason for the
higher ID (VDS D 0 V, VGS D 1 V) in the DG-JLTFET com-
pared to the DG-TFET is also because of the same reason of the
higher tunnel coupling effect offered by the DG-JLTFET for
equal threshold voltage. The variation of output conductance
(gd / with respect to gate voltage for equal threshold voltage is
shown in Fig. 6. The value of output conductance is calculated
as given in Eq. (2)Œ27 34 . The value of output conductance is
directly extracted from Fig. 5 using Eq. (2). From Fig. 6, we
observed that the value of output conductance increases up to

074001-3
J. Semicond. 2014, 35(7) M. W. Akram et al.

Fig. 6. Output conductance (gd / and output resistance (RO / for dif- Fig. 7. Voltage gain (AV / versus VGS for the DG-TFET and DG-
ferent drain voltages at VGS D 1 V. JLTFET at VDS D 1 V.

the drain voltages of 0.8 V and then decreases for both the de-
vices. Here we also observed that the output conductance of
DG-JLTFET is higher than that of DG-TFET, the higher value
of output conductance for the DG-JLTFET is achieved, and this
is because of the higher differential drain current offered by
DG-JLTFET for the same differential change in drain voltage
compared to the DG-TFET. Similar kinds of output conduc-
tance (gd / characteristics are also observed in Refs. [12, 32].

gd D @ID =@VDS : (2)

The variation of output resistance (RO / with respect to the

variation in drain voltage is also shown in Fig. 6. The value
of RO is calculated as the inverse of the output conductance
given in Eq. (3). The value of RO is extracted from Fig. 5 us-
ing Eq. (3). From Fig. 6, we observe that the DG-JLTFET has Fig. 8. Total gate capacitance (CGG / versus VGS for the DG-TFET and
a lower value of output resistance compared to the DG-TFET, DG-JLTFET at VDS D 1 V.
since the output conductance of the DG-JLTFET is higher than
that of the DG-TFET for all values of drain voltages, as ob-
served from the same figure.
1
RO D .@ID =@VDS / : (3)

The variation of intrinsic gain (gm /gd /Œ27 34 with respect
to gate voltage is shown in Fig. 7, and the intrinsic gain (gm /gd /
is directly extracted from Figs. 4 and 6. The DG-JLTFET shows
the improved value of intrinsic gain compared to the DG-
TFET, which implies that the DG-JLTFET is the better option
for analog application compared to the DG-TFETŒ32 34 .

3.3. C –V characteristics and unity gain frequency

The intrinsic gate capacitance is an important parameter
for the RF performance analysisŒ32 . The intrinsic gate capac-
itance is extracted from small signal AC device simulation at
an operating frequency of 1 MHz. The total gate capacitance
consists of gate to channel capacitance plus gate to source/drain
capacitance. The variation of total gate capacitance (CGG / with
respect to gate voltage is plotted in Fig. 8. From Fig. 8, we
observe that the value of gate capacitance (CGG / for the DG-
JLTFET is higher than that of the DG-TFET for all values of
gate voltages, this is because of the increase in capacitance due
to the inter-gate capacitance offered by the extra P-gate. Gate
Fig. 9. Unity gain frequency (fT / versus VGS for the DG-TFET and
DG-JLTFET at VDS D 1 V.
capacitance increases as the gate voltage increases; a similar
kind of trend is also observed in Ref. [32]. The DG-JLTFET
shows a better unity gain frequency (fT / response as com-
pared to the DG-TFET, as shown in Fig. 9. The higher value of
fT in the DG-JLTFET makes it more suitable for RF applica-

074001-4
J. Semicond. 2014, 35(7)
Œ34; 37
tions . The value of unity gain frequency (fT / is extracted
from Figs. 4 and 8 using Eq. (4)Œ35 37 .
fT D gm =2 CGG : (4)
4. Conclusion
In this work, we have investigated the analog perfor-
mances of an n-type double gate junctionless tunnel field effect
transistor (DG-JLTFET) and the results are compared with the
conventional n-type double gate tunnel field effect transistor
(DG-TFET). The DG-JLTFET is found to have a better drain
current (ID /, transconductance (gm /, output conductance (gd /,
intrinsic gain (gm /gd / and unity gain frequency (fT / as com-
pared to the DG-JLTFET. Hence, in terms of analog behavior,
the DG-JLTFET is superior to the DG-TFET.
References
[1] Boucart K, Ionescu A M. Double-gate tunnel FET with high-k
gate dielectric. IEEE Trans Electron Devices, 2007, 54: 1725
[2] Koswatta S O, Lundstrom M S, Nikonov D E. Performance com-
parison between p–i–n tunneling transistors and conventional
MOSFETs. IEEE Trans Electron Devices, 2009, 56(3): 456
[3] Nikam V, Bhuwalka K K, Kottantharayi A. Optimization of n-
channel tunnel FET for the sub-22 nm gate length regime. Device
Research Conference, Santa Barbara, CA, 2008
[4] Chaudhary A, Kumar M J. Controlling short-channel effects in
deep-submicron SOI MOSFETs for improved reliability: a re-
view. IEEE Trans Device Mater Reliab, 2004, 4: 99
[5] Colinge J P. Multiple gate SOI MOSFETs. Solid-State Electron,
2004, 48: 897
[6] Chen Q, Bowman K A, Harrell E M, et al. Double jeopardy in
the nanoscale court. IEEE Circuits Devices Mag, 2003, 19(1): 28
[7] Reddick W, Amaratunga G A J. Silicon surface tunnel transistor.
Appl Phys Lett, 1995, 67: 494
[8] Appenzeller J, Lin Y M, Knoch J, et al. Band-to-band tunneling
in carbon nanotube field-effect transistors. Phys Rev Lett, 2004,
93(19): 196805
[9] Bhuwalka K, Sedlmaier S, Ludsteck A, et al. Vertical tunnel field-
effect transistor. IEEE Trans Electron Devices, 2004, 51: 279
[10] Zhang Q, Zhao W, Seabaugh A. Low-subthreshold-swing tunnel
transistors. IEEE Electron Device Lett, 2006, 27(4): 297
[11] Choi W Y, Park B G, Lee J D, et al. Tunneling field-effect transis-
tors (TFETs) with subthreshold swing (SS) less than 60 mV/dec.
IEEE Electron Device Lett, 2007, 28(8): 743
[12] Boucart K, Ionescu A M. Length scaling of the double gate tunnel
FET with a high-k gate dielectric. Solid-State Electron, 2007, 51:
1500
[13] Bjork M T, Knoch J, Schmid H, et al. Silicon nanowire tunneling
field-effect transistors. Appl Phys Lett, 2008, 92: 193504
[14] Colinge J P, Lee C W, Afzalian A, et al. Nanowire transistors
without junctions. Nat Nanotechnol, 2010, 5: 225
[15] Lee C W, Afzalian A, Akhavan N D, et al. Junctionless multigate
field-effect transistor. Appl Phys Lett, 2009, 94: 053511
[16] Lilienfeld J E. Method and apparatus for controlling electric cur-
rent. US Patent, No.1745175, Oct. 22, 1925
[17] Colinge J P, Kranti A, Yan R, et al. Junctionless nanowire transis-
tor (JNT): properties and design guidelines. Solid-State Electron,
2011, 65/66: 33
074001-5
M. W. Akram et al.
[18] Park C H, Ko M D, Kim K H, et al. Electrical characteristics of
20-nm junctionless Si nanowire transistors. Solid-State Electron,
2012, 73: 7
[19] Lee C W, Ferain I, Afzalian A, et al. Performance estimation of
junctionless multigate transistors. Solid-State Electron, 2010, 54:
97
[20] Leung G, Chui C O. Variability impact of random dopant fluctu-
ation on nanoscale junctionless FinFETs. IEEE Electron Device
Lett, 2012, 33: 767
[21] Akhavan N D, Ferain I, Razavi P, et al. Random dopant varia-
tion in junctionless nanowire transistors. IEEE International SOI
Conference (SOI), Tempe, Arizona, USA, 2011
[22] Ghosh B, Akram M W. Junctionless tunnel field effect transistor.
IEEE Electron Device Lett, 2013, 34: 584
[23] Bal P, Akram M W, Mondal P, et al. Performance estimation of
sub-30 nm junctionless tunnel FET (JLTFET). J Computational
Electron, 2013, 12(4): 782
[24] Lide D R. CRC handbook on chemistry and physics. 89th ed.
London, UK: Taylor & Francis, 2008: 12
[25] Silvaco, Version 5.15.32.R. (2009) [Online]. Available:
http://www.silvaco.com
[26] Schenk A. A model for the field and temperature dependence of
SRH lifetimes in silicon. Solid-State Electron, 1992, 35: 1585
[27] Flandre D, Raskin J P, Vanhoenacker D. SOI CMOS transistors
for RF and microwave applications. Int J High Speed Electron
Syst, 2001, 11: 1159
[28] Eggermont J P, Flandre D, Raskin J P, et al. Potential and model-
ing of 1m SOI CMOS operational transconductance amp lifiers
for applications up to 1 GHz. IEEE J Solid-State Circuits, 1998,
33: 640
[29] Silveira F, Flandre D, Jespers P G A. A gm /ID based methodol-
ogy for the design of CMOS analog circuits and its application to
the synthesis of a silicon-on-insulator micropower OTA. IEEE J
Solid-State Circuits, 1996, 31: 1314
[30] Flandre D, Ferreira L, Jespers P G A, et al. Modeling and applica-
tion of fully-depleted SOI MOSFET’s for low-voltage low-power
analog CMOS circuits. Solid-State Electron, 1996, 39: 455
[31] Kilchytska V, Nève A, Vancaillie L, et al. Influence of device en-
gineering on the analog and RF performances of SOI MOSFETs.
IEEE Trans Electron Devices, 2003, 50(3): 577
[32] Gupta S K, Baishya S. Analog and RF performance evaluation of
dual metal double gate high-k stack (DMDG-HKS) MOSFETs.
J Nano Electron Phys, 2013, 5(3): 03008
[33] Narang R, Saxena M, GuptaR S, et al. Linearity and analog per-
formance analysis of double gate tunnel FET: effect of tempera-
ture and gate stack. International Journal of VLSI Design & Com-
munication Systems (VLSICS) 2011, 2(3): 185
[34] Baruah R K, Paily R P. Analog performance of bulk planar junc-
tionless transistor (BPJLT). Third International Conference on
Computing, Communication and Networking Technologies (IC-
CCNT’12), Coimbatore, India, 2012
[35] Mohankumar N, Syamal B, Sarkar C K. Investigation of novel
attributes of single halo dual-material double gate MOSFETs for
analog/RF applications. Microelectron Rel, 2009, 49: 1491
[36] Esame O, Gurbuz Y, Tekin I, et al. Performance comparison of
state-of-the-art heterojunction bipolar devices (HBT) based on
AlGaAs/GaAs, Si/SiGe and InGaAs/InP. Microelectron J, 2004,
35: 901
[37] Fobelets K, Calvo-Gallego J, Vel’azquez-P’erez J E. Effect of the
gate scaling on the analogue performance of s-Si CMOS devices.
Semicond Sci Technol, 2011, 26: 095030