Multiplexer (Mux)

A multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the
selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which
input line to send to the output. A multiplexer is also called a data selector

Block diagram of 2n:1 MUX Switch Diagram of 2n:1 MUX

Block diagram of 2:1 MUX Truth Table K-Map & Gate Level Circuit:
Output
Expression:

Block diagram of 4:1 MUX Truth Table: K-Map & Gate Level Circuit:
Output
Expression:

Block diagram of 8:1 MUX Truth Table: K-Map & Gate Level Circuit:
Output
Expression:
Problem 1: Design 8:1 MUX using 4:1 MUX

Problem 2: Implement the Boolean function y(a, b, c)   m 1,3,4,5,7  using 4:1 MUX
a) Keeping “a” as input & “b”, “c” as select line
Mapping and Simplification Logic Circuit

b) Keeping “b” as input & “a”, “c” as select line

Mapping and Simplification Logic Circuit

c) Keeping “c” as input & “a”, “b” as select line

Mapping and Simplification Logic Circuit

Problem 3: Implement the function f (a, b, c, d )   M 1,5,7,9,10,11,12  using a) 16:1 MUX, b) 8:1 MUX and
c) 4:1 MUX

Using 16:1 MUX Using 8:1 MUX Using 4:1 MUX

Problem 4: Realize the full adder using 4:1 MUX

 Demultiplexer (DEMUX)

A Demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-
output-lines, which is connected to the single input. A demultiplexer as a single-input, and multiple-
output switch.

Block diagram of 1:2n DE-MUX Switch Diagram of 1:2n DE-MUX

Block diagram of 1:2 MUX Truth Table Gate Level Circuit:

& Output Expression:

Block diagram of 1:4 MUX Truth Table: Gate Level Circuit:

& Output Expression:

Block diagram of 1:8 MUX Truth Table: Gate Level Circuit:

& Output Expression:
Problem 5: Design the Boolean function y(a, b, c)   m 1,3,4,5,7  using 1:8 DE-MUX

Problem 6: Design 1:8 DE-MUX using 1:4 DE-MUX

 Decoder:

A binary decoder is a combinational logic circuit that converts binary information from the n coded
inputs to a maximum of 2n unique outputs. They are used in a wide variety of applications, including
data demultiplexing, seven segment displays, and memory address decoding.

Block diagram of n x 2n Decoder:

Block diagram 2 x 4 Decoder Truth Table Gate Level Circuit:

& Output Expression:

Block diagram 4 x 8 Decoder Truth Table Gate Level Circuit:

& Output Expression:

Problem 7: Implement the function using Decoder F1   m 1,2,3,4  , F 2   m  0,5,7  and F 3   m 1,6,7 
Problem 8: Implement the divisible by 3 function with four variables using 4 x 16 Decoder

Problem 9: Realize the function F   m 1,2,3,6  using a) 3 x 8 decoder b)2 x 4 decoder

 Encoder:

An encoder in digital electronics is a one-hot to binary converter. That is, if there are 2n input lines,
and at most only one of them will ever be high, the binary code of this 'hot' line is produced on the n-
bit output lines. For example, a 4-to-2 simple encoder takes 4 input bits and produces 2 output bits.

Block diagram of 2n x n Encoder:

Block diagram 4 x 2 Encoder Truth Table Gate Level Circuit:

& Output Expression:

Block diagram 8 x 3 Truth Table Gate Level Circuit:

Encoder & Output Expression:
 Priority Encoder:

If two or more inputs are given at the same time, the input having the highest priority will
take precedence.

Truth Table of 4 x 2 Encoder Truth Table of 4 x 2 Priority Encoder

Simplification of 4 x 2 Priority Encoder Logic circuit for 4 x 2 Priority Encoder

Problem 10: Design a 4 to 2 Priority encoder

(a) with “I3” has highest priority and rest “I2”,”I1” and “I0”

(b) with “I0” has highest priority and rest “I1”,”I2” and “I3”

(c) Suppose the priority (2,1,0,3)

 Four bit Adder/Subtractor with over flow:

Problem 11: Draw the logic circuit of four bit adder with example

Problem 12: Draw the logic circuit of four bit subtractor with example

Problem 13: Draw the logic circuit of four bit adder/subtractor with example
Problem 12: When overflow will occur and how to find?

Problem 13: Draw the logic circuit of four bit adder/Subtractor with overflow

Binary Multiplier:

Problem 16: Let A= (10)2 and B=(11)2 show that results of A x B

Problem 17: Design the logic circuit & write a Verilog code for two-bit by two-bit binary multiplier

Problem 18: Design the logic circuit & write a Verilog code for four-bit by three-bit binary multiplier
4-bit Magnitude Comparator:
Problem: write a Verilog code for 4-bit magnitude comparator
 Verilog HDL

Verilog means “Verification of Logic”. HDL is acronym of “Hardware Description Language”. There are so
many HDL, among them Verilog HDL and VHDL are familiar for digital circuit design.
Types of Modeling:
1.
2.
3.
module: It is a keyword, Verilog program starts with this keyword. Each module should have a separate
name & endmodule.
Ex: module and_gate(); // where “and_gate” is module name
………….;
endmodule
Port list: input & output signals/variables are declared in port list.
Ex: module and_gate(A,B,out); // where “and_gate” is module name
………….; // (A,B,out) is a port list of and_gate
endmodule

Port list Declaration:

1st method 2nd method
module and_gate(A,B,out); module and_gate(input A,B,output out);
input A,B; ………….;
output out;
………….; endmodule
endmodule

Note: There (In Port list) is a space between “input” and “A”. There is no space between “A” and “,”
Try this:
module and_gate(input A,input B,output out);

………….;

endmodule

Reserved words/Keywords in Verilog:

Identifiers: The identifier is a unique name, which identifies an object, which is created by user.
Ex: module name and input/output variable names are identifiers.
An identifier can contain a sequence of letters, digits, underscores (_) and dollar signs ($). The first character
of an identifier can only be a letter or an underscore. Identifiers are case sensitive.

Identifier / Comment

17BEC0000

“A17bec” and “a17bec” are same?

_12sa

S_$&ab

$sad

cAs$_123

Gate level / Structural modeling

Only gate primitives are used to describe the logic circuit.
List of Gate primitives:

Problem 1: Write a Verilog code for a 2-input AND gate in Structural modeling

Problem 2: Write a Verilog code for the following circuit in Gate level modeling

wire:
wire elements are used to connect input and output ports of a module instantiation together with some other
element in your design.
wire elements are used as inputs and outputs within an actual module declaration
wire elements must be driven by something, and cannot store a value without being driven.
wire elements cannot be used as the left-hand side of an = or <= sign in an always@ block.
wire elements are the only legal type on the left-hand side of an assign statement.
wire elements are a stateless way of connecting two pieces in a Verilog-based design.
wire elements can only be used to model combinational logic.

Try this:
module my_module (a, b, c); Draw the logic diagram If A = 01 & B = 11 then c?
input [1:0]a, b;
output [1:0]c;
and x[1:0](c,a,b);
endmodule
One module cannot be defined in another module: YES / NO

Ex: / Comment

module gate1(input a,b,output c);
and x1(c,a,b);
module gate2(input d,e,output f);
or x2(f,d,e);
endmodule
endmodule

Can one module call another module? YES / NO

Types of module instantiation:

1. Instantiation by Name
2. Instantiation by Order
Problem 3: Write a Verilog code for a full adder using half adder in Structural modeling
Instantiation by Name Instantiation by Order

module ha(input a,b, output sum,carry); module ha(input a,b, output sum,carry);
xor x1(sum,a,b); xor x1(sum,a,b);
and x2(carry,a,b); and x2(carry,a,b);
endmodule endmodule

module fa(input a,b,cin,output sum,carry); module fa(input a,b,cin,output sum,carry);

wire s1,c1,c2; wire s1,c1,c2;
ha x1(.a(a),.b(b),.sum(s1),.carry(c1)); ha x1(a,b,s1,c1);
ha x2(.carry(c2),.a(s1),.b(cin),.sum(sum)); ha x2(s1,cin,sum,c2);
or x3(carry,c1,c2); or x3(carry,c1,c2);
endmodule endmodule

Note: Declaration port variable order can be Note: Declaration port variable order should not be
changed. changed.

Problem 4: Write a Verilog code for a 4-input binary adder gate in Structural modeling
// Half Adder
module ha(input a,b, output sum,carry);
xor x1(sum,a,b);
and x2(carry,a,b);
endmodule

//Full Adder
module fa(input a,b,cin,output sum,carry);
wire s1,c1,c2;
ha x1(a,b,s1,c1);
ha x2(s1,cin,sum,c2);
or x3(carry,c1,c2);
endmodule

//4-bit Adder
module fourbit_adder(a,b, sum,carry);
input [3:0]a,b;
input cin;
output [3:0]sum;
output carry;
wire Carryc1,Carryc2,Carryc3;
fa x1(a[0],b[0],cin,sum[0],Carryc1);
fa x2(a[1],b[1],Carryc1,sum[1],Carryc2);
fa x1(a[2],b[2],Carryc2,sum[2],Carryc3);
fa x2(a[3],b[3],Carryc3,sum[3],carry);
endmodule
Try this:
module my_module (a, b, c);
input a, b;
output c;
and x(c,a,b);
endmodule

module top (a, b, c) ;

input [3:0] a, b;
output [3:0] c;
my_module inst [3:0] (a, b, c);
endmodule
Draw the logic diagram for “top” If A = 0101 & B = 0011 then c?

Design the circuit & write the Verilog code (structural / Gate level modeling) for obtaining the above waveform
and give the truth table, Canonical and Standard form of Boolean expression for the above waveform with X,Y
and Z as inputs and P, C as outputs
 Data flow modeling
Operators and assign (it is a keyword) are used (not gate primitives).

List of Operators in Verilog:

1. Arithmetic Operators.
2. Logical Operators and Relational Operators.
3. Bitwise Operators.
4. Assignment Operators and Equality Operators.
5. Shift and Rotate Operators.
6. Concatenation and Replication Operators
7. Reduction Operators
8. Conditional Operators

Arithmetic Operators:
There are two types of arithmetic operators: binary and unary

Binary operators(Arithmetic): +, -, *, /, %, **
Try this: a=4‟b0011, b=4‟b0100, c=6, d=4 and e=2.

Function Operator name Result Comment

a+b
b-a

a*b

c/d

d ** e

3%2

16 % 4

-7 % 2

7 % -2

Unary operators(Arithmetic): +,-

+2
-3
Logical Operator: &&, ||, !
A = 3, B = 0, C = 2‟b0X, D =2‟10;
Function Operator name Result Comment (SIZE & Function)
A && B
!A
!B
C && D
(U == 2) && (V ==3)
!0000
!1000
0000 && 1101
0010 && 1101
0000 || 0110
Relational Operator: >, <, >=, <=
Let A=4, B=3, X=4’b1010, Y=4’b1101, Z=4’b1xxx
Function Operator name Result Comment (SIZE)

A <= B

A>B
Y >= X

Y< Z

Bitwise Operator: &, |, ~, ^, ^ ~, ~ ^,

Perform bit-by-bit operation on two operands (except ∼). Mismatched length operands are zero extended. “x”
and “z” treated the same.

A = 4‟b1010, B = 4‟b0000
Function Operator name Result Comment (SIZE)

A|B

A || B
A^B

4'b0001 & 4'b1001

4'b0001 ~^ 4'b1001

4'b0z01 ^ 4'bx001
4'b0z01 & 4'bx001

4'b0z01 && 4'bx001

Assignment (Operator): assign, <=, =

“assign” (Continuous assignment) : The continuous assignment is typically used with wires and other
structures that do not have memory. A continuous assignment is happening continuously and in
parallel to all other computational tasks. The order of continuous assignments, or their location in
the code do not matter.

“<=” (Non-blocking assignment): Non-blocking assignments are assignments that occur once, but
which can all happen at the same time. These assignments are typically used with registers and
integer data types, and other data types with memory.

“=” (Blocking assignment): Blocking assignments are also used with registers and integers (and
other memory data types). Blocking assignments occur sequentially, and the code after the
assignment will not execute until the assignment has occurred.

Problem 5: Write a Verilog code for a 2-input AND gate in dataflow modeling
Problem 6: Write a Verilog code for the following circuit in Dataflow modeling

Problem 7: Write a Verilog code for a 4-input binary adder gate in Dataflow modeling

a) without full adder module instantiation: b) with full adder module instantiation:

Problem 7: Write a Verilog code for full adder in Dataflow modeling

a) without half adder b) with half adder

Equality Operators: “= = =”,”! = =”,”= =”,”! =”

a === b a equal to b, including x and z (Logical Case equality)

a !== b a not equal to b, including x and z (Logical Case inequality)
a == b a equal to b, result may be unknown (Logical equality)
a != b a not equal to b, result may be unknown (Logical equality)

Output Comment
4'bx001 === 4'bx001
4'bx0x1 === 4'bx001
4'bz0x1 === 4'bz001
4'bx0x1 !== 4'bx001
4'bx0x1 !== 4'bx001
5 == 10
5 == 5
5 != 5
5 != 6
4’b1xxz == 4’b1xxx

Shift Operator: >>, <<

“>>” shift right

“<<” left right
“>>>” arithmetic shift right
“<<<” arithmetic shift left

Arithmetic right shift (>>>). Shift right specified number of bits, fill with value of sign bit if
expression is signed, othewise fill with zero.
Arithmetic right shift (<<<). Shift left specified number of bits, fill with value of sign bit if expression
is signed, othewise fill with zero.

Let a=8'b10011011 Output: Comment:

assign x = a >> 1

Let b=8'b10011011 Output: Comment:

assign y = b << 3

Concatenation Operator: { , }

Let a = 1‟b1, b = 2‟b00, Output Comment

c = 2‟b10, d = 3‟b110
y = {b, c} 4‟b0010
y = {a, b, c, d, 3‟b001} 11‟b10010110001
y = {a, b[0], c[1]} 3‟b101
Replication Operator: { { } }

Let a = 1‟b1, b = 2‟b00, Output Comment

c = 2‟b10, d = 3‟b110

y = { 4{a} } 4‟b1111
y = { 4{a}, 2{b} } 8‟b11110000
y = { 4{a}, 2{b}, c } 10‟b1111000010

Conditional Operator: ( ? : )

(conditional expression ? true expression : false expression) ;

module logic( input sel, d_in1, d_in0, output d_out ); Comment (Name of the Circuit):
assign d_out = sel ? d_in1 : d_in0;
endmodule

Problem: Write 4:1 and 8:1 MUX using conditional Operator:

4:1 MUX using conditional Operator 8:1 MUX using conditional Operator

Reduction Operator: &, ~&, |, ~|, ^, ~^, ^~

(Unary Operator)

A = 4‟b1010, B = 4‟b0000
Function Operator name Result Comment (SIZE)

A|B Bitwise OR 4‟b1010

|A Reduction OR 1 One bit size (i.e 1|0|1|0)

&A Reduction AND 0 One bit size (i.e 1 & 0 & 1 & 0)
^A Reduction XOR 0

~^A Reduction XNOR 1

Problem: Write a Verilog code for 4 bit odd parity checker and generator
With Reduction operator Without Reduction operator

Problem: Write a Verilog code for 4 bit even parity checker and generator
With Reduction operator Without Reduction operator

Behavioural modeling:

Behavioral models in Verilog contain procedural statements, which control the simulation and
manipulate variables of the data types. These all statements are contained within the procedures. Each
of the procedure has an activity flow associated with it.

During simulation of behavioral model, all the flows defined by the „always‟ and „initial‟ statements
start together at simulation time „zero‟. The initial statements are executed once, and the always
statements are executed repetitively.

Problem : Draw the wave form for the following program

module behave;
reg a,b;

initial
begin
a = 1’b1;
b = 1’b0;
end

always
begin
#50 a = ~a;
end

always
begin
#100 b = ~b;
end
endmodule
Procedural assignments:

Blocking and Non-blocking assignment:

module block_nonblock();
reg a, b, c, d , e, f ;

// Blocking assignments
initial begin
a = #10 1'b1;// The simulator assigns 1 to a at time 10
b = #20 1'b0;// The simulator assigns 0 to b at time 30
c = #40 1'b1;// The simulator assigns 1 to c at time 70
end

// Nonblocking assignments
initial begin
d <= #10 1'b1;// The simulator assigns 1 to d at time 10
e <= #20 1'b0;// The simulator assigns 0 to e at time 20
f <= #40 1'b1;// The simulator assigns 1 to f at time 40
end

endmodule

Conditions:

if ( ) if ( ) if ( ) if ( )
……. begin begin begin
else if ( ) if ( ) ……
….. ….. ….. end
else( ) end
….. else else if ( )
end ….. begin
else …..
….. end
else if ( )
begin
…..
end
else( )
end
else
…..

Problem write a Verilog program for comparator using if and else

Problem: Explain the following program with inputs and why we declared result as “reg” data type?

module addsub (a, b, addnsub, result);

input[7:0] a;
input[7:0] b;
input addnsub;
output[8:0] result;

reg[8:0] result;

always @(a or b or addnsub)

begin
if (addnsub)
result = a + b;
else
result = a - b;
end
endmodule

Problem: 4:1 MUX using case statement

module mux (a,b,c,d,sel,y); module mux (a,b,c,d,sel,y); module mux (a,b,c,d,sel,y);

input a, b, c, d; input a, b, c, d; input a, b, c, d;
input [1:0] sel; input [1:0] sel; input [1:0] sel;
output y; output y; output y;

reg y; reg y; reg y;

always @ (a | b | c | d | sel) always @ (a,b,c,d,sel) always @(a or b or c or d or sel)

bgein bgein bgein
case (sel) case (sel) case (sel)
0 : y = a; 2‟b00 : y = a; 2‟b00 : y = a;
1 : y = b; 2‟b01 : y = b; 2‟b01 : y = b;
2 : y = c; 2‟b10 : y = c; 2‟b10 : y = c;
3 : y = d; 2‟b11 : y = d; 2‟b11 : y = d;
default : $display("Error"); default : $display("Error"); default : $display("Error");
endcase endcase endcase
end end end
endmodule endmodule endmodule

Explain it: Explain it: Explain it:

Problem: Write a Verilog 2 x 4 Decoder and 4 x 2 Encoder using case statement

2 x 4 Decoder 4 x 2 Encoder

Example: 4:1 MUX using case statement without default

module mux_without_default (a,b,c,d,sel,y);

input a, b, c, d;
input [1:0] sel;
output y;

reg y;

always @ (a or b or c or d or sel)
case (sel)
0 : y = a;
1 : y = b;
2 : y = c;
3 : y = d;
2'bxx,2'bx0,2'bx1,2'b0x,2'b1x,
2'bzz,2'bz0,2'bz1,2'b0z,2'b1z : $display("Error in SEL");
endcase

endmodule

Special versions of the case statement allow the x ad z logic values to be used as "don't care":

casez : Treats z as don't care.

casex : Treats x and z as don't care.

module case_xz(enable); Find-out the for “1”,”0”,”x” and “z”
input enable; inputs:
always @ (enable)
case(enable)
1'bz : $display ("enable is floating");
1'bx : $display ("enable is unknown");
default : $display ("enable is
%b",enable);
endcase

endmodule

module case_xz(enable); Find-out the for “1”,”0”,”x” and “z”

input enable; inputs:
always @ (enable)
casex(enable)
1'bz : $display ("enable is floating");
1'bx : $display ("enable is unknown");
default : $display ("enable is
%b",enable);
endcase

endmodule

module case_xz(enable); Find-out the for “1”,”0”,”x” and “z”

input enable; inputs:
always @ (enable)
casez(enable)
1'bz : $display ("enable is floating");
1'bx : $display ("enable is unknown");
default : $display ("enable is
%b",enable);
endcase

endmodule
Example : 8 x 3 priority encoder using casex

module priority_encoder (code, valid_data, data);

output [2:0] code;
output valid data;
input [7:0] data;
reg [2:0] code;

assign valid_data= |data; // Use of "Reduction or" operator

always @ (data)
begin
casex (data)
8'b1xxxxxxx : code=7;
8'b01xxxxxx : code=6;
8'b001xxxxx : code=5
8'b0001xxxx : code=4;
8'b00001xxx : code=3;
8'b000001xx : code=2;
8'b0000001x : code=1;
8'b00000001 : code=0;
dafault : code=3'bx;
endcase
endmodule
 Test bench:

module andgate (a, b, y); Test bench for “andgate”:

input a, b;
output y; module andgate_tb;
assign y = a & b; wire t_y;
endmodule reg t_a, t_b;
andgate my_gate( .a(t_a), .b(t_b), .y(t_y) );
initial
begin
t_a <= 1'b0;
t_b <= 1'b0;
#5
t_a <= 1'b0;
t_b <= 1'b1;
#5
t_a <= 1'b1;
t_b <= 1'b0;
#5
t_a <= 1'b1;
t_b <= 1'b1;
$monitor(t_a, t_b, t_y);
end
endmodule

Output of andgate Test bench file:

In Transcript window
Test bench for Four bit Adder: Output of Test bench of Four bit
adder:
module fourbit_ adder_tb;
reg [3:0]a,b;
reg cin;
wire cout;
wire [3:0]sum;
integer i,j,k;
fourbit_adder s1(a,b,cin,cout,sum);

initial
begin
a=0;b=0;cin=0;

for(i=0;i<16;i=i+1)
for(j=0;j<16;j=j+1)
for(k=0;k<2;k=k+1)
begin
a=i;
b=j;
cin=k;
$monitor("a=%d,b=%d,cout=%d,sum=%d",a,b,c4,sum);
#100;
end
end
endmodule
Problem: write a Verilog code for 2 x 4 decoder & test bench for 2 x 4 decoder
4 x 4 Binary Multiplier: