CMOS INTEGRATED CIRCUIT DESIGN TECHNIQUES

University of Ioannina
University of Ioannina

Scan Testing

Dept. of Computer Science and Engineering

Y. Tsiatouhas

CMOS Integrated Circuit Design Techniques
Overview

1. Scan testing: design and application
2. At speed testing
3. The scan‐
The scan‐set design technique
4. Scan testing power issues
5. The scan‐
The scan‐hold design technique
g q
6. Level sensitive scan design

VLSI Systems
7. Broadcast and Illinois scan design
and Computer Architecture Lab

Scan Testing 2

1
 Sequential Circuits Testing
In sequential circuits the initial state
(register’s values) is not by default known.
outputs = f(inputs, state) Consequently, the sensitization of faults
and the propagation of the corresponding
erroneous responses may turn to be a hard
Inputs task.
Combinational  Outputs
Logic A solution is to use techniques for the
proper initialization of the circuit state to
known values.
• Application of proper test vector
sequences and/or the use of Set/Reset
Registers signals to setup the required state.
• Development of efficient techniques to
Clock set the initial state and observe the
“State
State””
subsequent state after the response of
the circuit.

Scan Testing 3

General Scan Testing Scheme
Registers Logic
Scan‐In

Inputs Outputs

Clock
Scan‐Out
Scan
Register
The memory elements (latches or Flip‐Flops) in a design are properly connected to form
a unified shift register (scan register or chain). This way the internal state of the circuit is
determined (controlled) by shifting in (scan‐in) to the scan register the required test data
to be applied to the combinational logic. Moreover, the existing internal state (previous
logic response) can be observed by shifting out (scan‐out) the data stored into the scan
register.

Scan Testing 4

2
 Scan Testing Design (Ι)
Scan Testing Design  (Ι)
Primary Inputs

PI Combinational PO Primary Outputs

Logic
Pseudo‐Primary Outputs

Full Scan

Register
PI PO
Combinational
PPI Logic PPO
Original Circuit
S
Scan‐In
I

Pseudo‐Primary Inputs

Scan
Register

Scan‐Out

Scan Testing 5

Scan Testing Design (Ι
Scan Testing Design  (ΙII)

Multiple Scan Chains Partial Scan

PI Combinational PO PI Combinational PO
Logic Logic
Scan‐In_1

Scan
Register
Register

Scan‐Out_1
S
Scan‐In_N
I N .
.
Scan‐In
.
Scan Scan
Register Register

Scan‐Out_N Scan‐Out

Scan Testing 6

3
 Scan Path Design (I)

utputs
nputs

X1 Z1
Combinational

Primary Ou
Primary In

X2 Z2
. . . Logic . . .
XK ZN

Scan FF D Flip‐Flop
0 0 0 0 SO
D Q D Q D Q
MUX

MUX

MUX

MUX
SI 1 2 M
1 1 1 1
CLK CLK . . . CLK
Scan Chain
SE
“1”
CLK

Scan Mode
SE=“1”

Scan Testing 7

Scan Path Design (II)
utputs
nputs

X1 Z1
Combinational
Primary Ou
Primary In

X2 Z2
. . . Logic . . .
XK ZN

0 0 0 0 SO
D Q D Q D Q
MUX

MUX

MUX

MUX

SI 1 2 M
1 1 1 1
CLK CLK . . . CLK
Scan Chain
SE
“0”
CLK

Normal Mode
SE=“0”

Scan Testing 8

4
Primaary Inputs
. . .
Test Sequences During Scan Testing

Test Vector

. . .
SI
clock cycles
1st sequence 2nd sequence 3rd sequence 4th sequence th (Ν+1)th sequence
. . . Ν sequence
Outputs
. . .

Test Response

.
. . .
Primary O

SO
clock cycles

Scan Testing 9

Scan Application (Ι)

1 Scan cells testing

2 SE = “1”

Scan‐in of alternating
3  Μ+1 clock cycles
“0” and “1” from the SI input

Response observation
4
at the SO output

Μ = # of scan cells

Scan Testing 10

5
 Scan Application (ΙI
(ΙI)

5 Logic testing
g g

SE = “1”: Test data scan‐in
6 Μ clock cycles (scan‐in cycles)
from the SI inputs

SE = “0”: Test pattern
7
application from the PI inputs

Single clock pulse and
8 single clock cycle (capture cycle)
response observation at the POs

Scan Testing 11

Scan Application (ΙII
(ΙII))

SE = “1”: New test data 
scan‐in from the SIs Μ clock cycles
9
and simultaneous scan‐out of 
the test responses from the SOs

Exists another YES
10 7
test vector;

No

11 End

Scan Testing 12

6
 Delay Fault Testing
11 In1 1 Out1
D Q D Q
CLK
side path
CLK
1
01 In2 D Q D Q Out2

CLK CLK
Logic
CLK path under test CLK

V1 = <10> ←  Ini alizing test vector

V2 = <11> ←  Path ac va on test vector
A path delay fault requires a pair of subsequent test vectors to be detected. 
The first test vector initializes the circuit while the second test vector activates the path under test. 
The first test vector initializes the circuit while the second test vector activates the path under test.
How scan testing facilities can be exploited for delay fault testing ? 
Initializing Launch Test
Vector Activation Response
Application Vector Capture
CLK At speed clocking!
t
Scan Testing 13

At Speed Scan Testing (I)
(Skewed‐‐load or Launch
(Skewed load or Launch‐‐on
on‐‐shift Technique)

X1 Z1
Combinational
X2 Z2
Logic . . .
. . .
XK ZN

0 0 0 0 SO
MUX

MUX
MUX

MUX

SI D Q D Q D Q
1 1 1 2 1 M 1
CLK CLK . . . CLK
Scan Chain

SE
CLK
pture
unch
Lau
Cap

Shift Shift Shift Shift

Delay fault oriented 
CLK
scan testing 
technique

SE

Fast Transition
t
Scan Testing 14

7
 At Speed Scan Testing (II)
(Double Capture or Launch
(Double Capture or Launch‐‐on
on‐‐Capture Technique)

X1 Z1
Combinational
X2 Z2
Logic . . .
. . .
XK ZN

0 0 0 0 SO

MUX

MUX
MUX

MUX
SI D Q D Q D Q
1 1 1 2 1 M 1
CLK CLK . . . CLK
Scan Chain

SE
CLK

pture
unch
Lau
Cap
Shift Shift Shift
Delay fault oriented 
CLK
scan testing 
technique

SE Dead
Time
t
Scan Testing 15

Fast Clock Pulses Generation
SE
D Q
Scan_CLK
Q1 Q2 Q3 Q4 Q5
Shift Register

PLL Clock_Gating
PLL_CLK 0 CLK
1
Scan_CLK
_

SE
PLL_CLK

Clock_Gating

CLK
t
Scan Testing 16

8
 The Clocked‐‐Scan Technique
The Clocked
X1 Z1

X2 Combinational Z2
Logic
PI . . . . . . PO
XK ZN

D Q D Q D Q
DCK DCK DCK
SI SI SI
. . . SI SO
1 2 M
SCK SCK SCK
Flip‐Flop
DCK
SCK

Scan Testing 17

The Scan
Scan‐‐Set Technique (I)
X1 Z1

X2 Combinational Z2
PI . . . Logic . . . PO
XK ZN

0 0 0
D Q D Q D Q
1 1 1 2 1 M
CLK CLK . . . CLK
SE1 “0”
SCLK

0 0 0
D Q D Q D Q SO
SI 1 1 1 2 1 M
CLK CLK . . . CLK
SE2 “1”
Test Data Scan‐In
TCLK SE1=“0” ‐ SE2=“1”

Scan Testing 18

9
 The Scan
Scan‐‐Set Technique (II)
X1 Z1

X2 Combinational Z2
PI . . . Logic . . . PO
XK ZN

0 0 0
D Q D Q D Q
1 1 1 2 1 M
CLK CLK . . . CLK
SE1 “1”
SCLK

0 0 0
D Q D Q D Q SO
SI 1 1 1 2 1 M
CLK CLK . . . CLK
SE2 “0”
Test Data Application
TCLK SE1=“1” ‐ SE2=“0”

Scan Testing 19

The Scan
Scan‐‐Set Technique (III)
X1 Z1

X2 Combinational Z2
PI . . . Logic . . . PO
XK ZN

0 0 0
D Q D Q D Q
1 1 1 2 1 M
CLK CLK . . . CLK
SE1 “0”
SCLK

0 0 0
D Q D Q D Q SO
SI 1 1 1 2 1 M
CLK CLK . . . CLK
SE2 “0”
Test Response Capture
TCLK SE1=“0” ‐ SE2=“0”

Scan Testing 20

10
 The Scan
Scan‐‐Set Technique (IV)
X1 Z1

X2 Combinational Z2
PI . . . Logic . . . PO
XK ZN

0 0 0
D Q D Q D Q
1 1 1 2 1 M
CLK CLK . . . CLK
SE1 “0”
SCLK

0 0 0
D Q D Q D Q SO
SI 1 1 1 2 1 M
CLK CLK . . . CLK
SE2 “1”
Test Response Scan‐Out
TCLK SE1=“0” ‐ SE2=“1”

Scan Testing 21

Dual Flip
Dual Flip‐‐Flops Scan Architecture
Flip‐Flop
SCB
Scan FF
SI
from scan FF D1 Master C Slave 
SCA Latch L t h
Latch
C1 Q SO
D Q to scan FF
D2
CUPTURE
C2

System FF
D1 Slave
UPDATE Latch
C1
Q Q
D to logic
from logic D Q D2
Master  C2
C Latch
CLK

Intel

Scan Testing 22

11
 Scan Testing Impact

• Silicon area and pin count cost.

• Speed performance degradation.
• Test application time cost.
• Excess power consumption (usually outside circuit’s
specifications) during the scan‐in/out operations and the
capture
p of the test response
p in the scan chain.

Scan Testing 23

Scan Chain Shift Power Consumption (I)
Test Vector Scan Chain Response
Capture 0  1   1   0   1   0 1  0   0    0    1   0

Cycle 1 0  1   1   0   1 0 1   0    0    0   1 0

Cycle 2 0  1   1   0 1 0 1    0    0   0 1  0

Cycle 3 0  1   1 0 1 0 1    0   0 0  1   0

Cycle 4
y 0  1 1 0 1 
1 0 
0 1   0
1 0 0  0   1   0

Cycle 5 0 1 1 0  1  0 1 0   0   0   1   0

Cycle 6 0 1 1 0  1 0 1  0   0   0   1   0

Scan Testing 24

12
 Scan Chain Shift Power Consumption (II)
Test Vector Scan Chain Response
0  1   1   0   1   0 1  0   0    0    1   0

0  1   1   0   1 0 # Transitions
# Transitions = 
0 1   0    0    0   1
Distance from 1st scan‐out bit 

0  1   1   0 1 0 1    0    0   0 1  0

0  1   1 0 1 0 1    0   0 0  1   0

0  1 1 0 1 0 
0 1   0
1 0 0  0   1   0

# Transitions = 
0 1 1 0 1  0 1 0   0   0   1   0
L – (Distance from 1st scan‐in bit)
0 1 1 0  1 0 1  0   0   0   1   0
L  =  scan chain length

Scan Testing 25

Scan Chain Capture Power Consumption
1  0   1   0    0   0 New Response

Previous Test Vector 0  1   1    1    0   1
Previous Scan Chain State
Previous Scan Chain State Scan Chainh

1  0   1    0    0   0 New Scan Chain State
Scan Chain

Power consumption during scan testing procedures is a major concern since it can be several
times higher
g than this duringg the normal mode of operation.
p This can affect the reliabilityy of
the circuit under test (CUT) due to overheat and electromigration phenomena.
The excessive switching activity of the CUT during the scan operations may violate the power
supply IR and Ldi/dt drop limitations and increase the probability of noise induced test
failures. In addition, the elevated temperature can degrade the speed performance of the
CUT and result to erroneous test responses that will invalidate the testing process and lead
to yield loss.

Scan Testing 26

13
 X‐bit Assignment
• A large number of bits in a test cube that is generated by
an ATPG tool are don’t care bits (X‐bits).
• In order to apply a test cube for circuit testing, specific
values must be assigned to the X‐bits (test vector
formation). This task is called X‐filling.
• The X‐filling process can be oriented for shift and/or
capture power reduction.

Scan Testing 27

Low Power Scan
from logic to logic

Scan FF
DI
0 Original Topology
Original Topology
D Q
MUX

1
SI CLK

from scan FF to scan FF
SE CLK SE to logic
from logic Scan FF

Use of Data Gating (φραγμός δεδομένων)

t h i
techniques att the
th output
t t off the
th scan cells
ll in
i DI
0
D Q
MUX

order to eliminate the signal transitions at

the inputs of the combinational logic during 1
SI CLK
the scan‐in/out operations.
Dynamic power reduction.
from scan FF CLK to scan FF

Scan Testing 28

14
 Scan‐‐Hold Flip
Scan Hold Flip‐‐Flop
from logic to logic

Scan FF
DI
0 Original Topology
Original Topology
MUX D Q
1 FF
SI
CLK

from scan FF to scan FF
SE CLK

from logic to logic
Scan‐Hold FF
DI
Delay testing oriented Flip‐Flop! 0

MUX
D Q D Q
1 FF Latch
+ Dynamic power reduction. SI
CLK C

from scan‐hold FF
SE CLK Hold
to scan‐hold FF

Scan Testing 29

The Scan
Scan‐‐Hold Technique
X1 Z1

X2 Combinational Z2
Logic
PI . . . . . . PO
XK ZN

D Scan D Scan D Scan

C FF C FF C FF
SI SI SI
. . . SI SO
A Q A Q A Q
1 2 M
D D D
Latch Latch Latch
C Q C Q C Q
Scan‐Hold FF
CLK
SE
Intel
Hold

Scan Testing 30

15
 Level Sensitive Scan Design (I)
X1 Z1

X2 Combinational Z2
Logic
PI . . . . . . PO
XK ZN

D D D
C L C L C L
SI SI
1
SI
1 . . . SI
1
SO
A Q A Q A Q
1 2 M
D D D
L2 L2 L2
B Q B Q B Q
Latches Pair
C
A LSSD Design
B IBM

Scan Testing 31

Level Sensitive Scan Design (II)
X1 Z1

X2 Combinational Z2
Logic
PI . . . . . . PO
XK ZN

D D D
C L C L C L
SI SI
1
SI
1 . . . SI
1

A Q A Q A Q
1 2 M
D D D
L2 L2 L2
B Q B Q B Q SO

C1 . . . Latches Pair
C2
A LSSD Design
B IBM

Scan Testing 32

16
 Level Sensitive Scan Design (III)
D D Q Q_Latch D D Q Q_FF

CLK CLK CLK CLK

D Latch Edge Triggered
D Flip‐Flop
l l
D‐Latch and D‐Flip‐Flop operation
D
CLK
Q_Latch

Q_FF

C ή A

SI
B

Non overlapping  t
Latches Pair clocks
Scan Testing 33

Test Data Compression
Typically, ATPG tools generate test vectors where only 1% to 5% of the bits 
have specified values! 

On the other hand, test data volume is a major concern for the available bandwidth and the 
ATEs’ storage capabilities. 

Scan Chains
Compressed
Deccompressor

Tesst Responses
Compactor

Test Compacted
.
Stimuli

Data Response
Test Patterns .
.
C

Low Cost ATE

Expected Responses
CUT
Comparator Chip

Scan Testing 34

17
 Linear Decompression
Decompressor

X1 Scan Chains

Z9 Z5 Z1
X9 X7 X5

X2
Z 9  X1  X 4  X 9 Z5  X3  X7 Z1  X 2  X 5
Z10 Z6 Z2
Z 10  X 1  X 2  X 5  X 6 Z 6  X1  X 4 Z2  X3
X3
Z 11  X 2  X 3  X 5  X 7  X 8 Z 7  X1  X 2  X 5  X 6 Z 3  X1  X 4
Z11 Z7 Z3
Z 12  X 3  X 7  X 10 Z 8  X2  X 5  X8 Z 4  X1  X6

X4
Z12 Z8 Z4
X10 X8 X6
XOR

Scan Testing 35

Broadcast & Illinois Scan Design
SI

SC1 SC2 . . . SCn

B d tS
Broadcast Scan Design
D i
C1 C2 . . . Cn
Combinational Logic   C

SO1 SO2 SO3 SO4

B‐S_Mode

SI Segment 1
g
0
Segment 2
0
1 Segment 3
Illinois Scan Design 0
1 Segment 4
1

Combinational Logic   C

Scan Testing 36

18
 Reconfigurable Broadcast Scan Design
Pin1 Pin2 Pin3 Pin4 Control

0
Scan_Chain 1
1

0
Scan_Chain 2
1
Dynamic
Reconfiguration
0
Scan_Chain 3
1

0
Scan_Chain 4
1
Scan_Chain 5

Scan_Chain 6

Scan Testing 37

Space Compaction
Scan‐Chain 1

Scan‐Chain 2

Scan‐Chain 3

Scan‐Chain 4

Scan‐Chain 5

Scan‐Chain 6

Scan‐Chain 7

Scan‐Chain 8

SCO1 SCO2 SCO3 SCO4 SCO5 SCO6 SCO7 SCO8

Scan‐chains’ 
outputs

Linear 
Phase
Compactor

Out1 Out2 Out3 Out4

Scan Testing
X‐Compact 38

19
 Random––Access Scan Design
Random
X1 Z1
X2 Z2
PI . . . Combinational Logic . . . PO
XK ZN

SC SC … SC
Row (X) Decoder

CLK

SC SC … SC Scan Cell
SI
.. .. ..
. . .
R

SO
0 Q
SC SC … SC SI 1
SI Q

TM SE
Column (Y) Decoder D CLK
SC
Address Shift Register AI
AS CLK

Scan Testing 39

Reordering of Scan Chain Flip
Reordering of Scan Chain Flip‐‐Flops (Ι)
Typical Scan Chain

SI 8FF 4FF

50 TV  300TV
50 300
2FF

Test Test ΙΝ
Vectors Vectors

4FF 2FF SO
“Random” register
Test Application: 300(20+1)+20 = 6320 clock cycles connection

Improvement
1st Alternative Test Application: 300(14+1)+8 = 4508 clock cycles 29% !

Scan Testing 40

20
 Reordering of Scan Chain Flip
Reordering of Scan Chain Flip‐‐Flops (II)
II)
2nd Alternative Scan Testing Application

SI 8FF 4FF

50 300

2FF
Test Test ΙΝ
Vectors Vectors

4FF 2FF SO

Test Application: 50(14+1)     =   750 clock cycles
250(12+1)+8 = 3258 clock cycles Improvement
37% !
4008 clock cycles

Scan Testing 41

Reordering of Scan Chain Flip
Reordering of Scan Chain Flip‐‐Flops (III)
III)
3rd Alternative Scan Testing Application with cell reordering

8FF 4FF SI

50 300
2FF

Διανύσματα Διανύσματα ΙΝ
Ελέγχου Ελέγχου

4FF 2FF SO

Test Application: 50(18+1)     =   950 clock cycles
In addition, test power 250(4+1)+4 = 1254 clock cycles Improvement
reduction is achieved! 65% !
2204 clock cycles

Scan Testing 42

21
 References

• “Principles of Testing Electronics Systems,” S. Mourad and Y. Zorian, John Wiley

& Sons, 2000.
• “Essentials
Essentials of Electronic Testing: for Digital,
Digital Memory and Mixed‐Signal VLSI
Circuits,” M. Bushnell and V. Agrawal, Kluwer Academic Publishers, 2000.
• “Power‐Constrained Testing of VLSI Circuits,” N. Nicolici and B. Al‐Hashimi,
Kluwer Academic Publishers, 2003.
• “Digital Systems Testing and Testable Design,” M. Abramovici, M. Breuer and A.
Friedman, Computer Science Press, 1990.
• “System‐on‐Chip Test Architectures,” L‐T Wang, C. Stroud and N. Touba,
Morgan‐Kaufmann, 2008.
• “VLSI Test Principles and Architectures,” L‐T Wang, C‐W. Wu and X. Wen,
Morgan‐Kaufmann, 2006.

Scan Testing 43

22