EXPERIMENT NO.

1:

Objective
To characterize an n-channel MOSFET by measuring the device parameters
 Transconductance parameter (Kn)
 Threshold voltage (Vt)
 Channel length modulation coefficient (λ)
 Verify Gm vs Id to be parabolic
 Drain output resistance
Theory
Let VDS ,VGS from 0 – 1.8V in 0.01V increments.
In the saturation mode (that is VDS> (VGS –Vt)), neglecting the channel length
modulation, the drain current is described by,
𝐾𝑛 𝑊
𝐼𝐷 = (𝑉𝐺𝑆 − 𝑉𝑡 )2 (1)
2 𝐿

Now the square root of the drain current can be written as a linear function of gate
to source voltage.

𝐾 𝑊
√𝐼 𝐷 = √ 2𝑛 𝐿
(𝑉𝐺𝑆 − 𝑉𝑡 ) (2)

𝐾𝑛 𝑊
The slope of linear curve of squareroot Id vs Vgs is equal to√ from this the
2 𝐿
transconductance parameter Kn can easily be calculated. The voltage axis
intercept of the resulting curve can determine the threshold voltage (V t). By
extrapolating the curves to zero drain current the threshold voltage V t can be
computed. The voltage axis intercept of curve with Vsb = 0, gives the zero bias
threshold volt (Vto).

The experimental measurement of the channel length modulation coefficient

lambda requires a different test circuit setup. The drain to source voltage is chosen
sufficiently large (VDS>VGS-Vt) that the transistor operation in saturation region. The
saturation drain current is then measured for two different drain voltages values V DS1, VDS2. Note that
the drain current in the saturation mode is given by

𝐾𝑛 𝑤
𝐼𝐷 = (𝑉𝐺𝑆 − 𝑉𝑡 )2 (1 + 𝜆𝑉𝐷𝑆 ) (3)
2 𝑙

The ratio of ID1, ID2 is

𝐼𝐷2 (1+ 𝜆𝑉𝐷𝑆2 )
= (4)
𝐼𝐷1 (1+ 𝜆𝑉𝐷𝑆1 )

Which can be used to calculate the λ .This is in fact equivalent to calculating the
slope of drain current versus drain voltage curve in the saturation region.

Observations

1. NMOS

Plots

1. Id vs Vds
 2. Id vs Vgs

3. Root Id vs vgs

4.Gm vs Id
CALCULATIONS

1. Vt = 0.4 V (from graph)

2.Kn = 2Id (L/W)/ (Vgs-Vt)2

Now, W= 3u, L=1u, Vgs = 0.9 V, Id = 80.5 uA, Vt = 0.4 V

Kn = 13.4166 uA/V2

3. λ,We know that current in saturation region follows the relation,

Id1=79.178 uA , Vds1=750 mV

Id2=81.179 uA, Vds2=1.78 V

 81.179/19.178=(1+ƛ1.78)/(1+ ƛ0.75)
 ƛ=0.024 V-1

4.ro

𝑟𝑜 = (Vds1-Vds2) / (Id1-Id2)

ro = 58.55 K Ω

5. 𝑔𝑚 = √(2𝑘n / 𝐷)

As expected from the equation, the graph came out to be parabolic in nature
which can be observed above.
2.PMOS

Circuit diagram

Plots

1. Id vs Vsg
2. Id vs Vsd

3. Root Id vs Vsg
 4. Gm vs Id

CALCUALTIONS

1. Vt = -0.42 V (from graph)

2. Kp = 2Id (L/W)/ (Vsg-|Vt|)2

Now, W= 3u, L=1u, Vsg = 1.35 V, Id = 55uA, |Vt| = 0.42 V

Kn = 31.53 uA/V2

3.λ,We know that current in saturation region follows the relation,

Id1=100.707 uA , Vd1=920 mV

Id2=107.03114 uA ,Vd2=1.09 V

107.0311/100.707=(1+ ƛ1.09)/(1+ ƛ0.920)

ƛ=0.0548 V-1.
4..ro

𝑟𝑜 = (|Vds1|-|Vds2|) / (Id1-Id2)

ro = 121.64 K Ω

5. 𝑔𝑚 = √(2𝑘𝑝 / 𝐷)

As expected from the equation, the graph came out to be parabolic in nature
which can be observed above

Results

NMOS

1. Vt=0.4 V
2. Kn=13.4166 uA/V2
3. ƛ=0.024 V-1
4. ro=58.55 K ohm

PMOS

1. Vt=-0.42 V
2. Kn=31.53 uA/V2
3. ƛ=0.0548 V2
4. ro=121.64 K ohm
Analog Circuit : Design to Layout (EC361)
Practical File

Submitted to: Prof. Rajeshwari Pandey

Prof. Neeta Pandey

Submitted by: Nitin Rajput

2K17/EC/115