PDN Laborator 1

Introducere,
Arhitectura PSoC 3, PSoC 5LP
MCU
PSoC 3 / PSoC 5 LP
 PSoC 3 / PSoC 5LP Feature Set
Single-cycle 8051 CPU ARM® CortexTM-M3 CPU
• Up to 64 KB of flash • Up to 256 KB of flash
• Up to 8 KB of RAM • Up to 64 KB of RAM
• Up to 2 KB EEPROM • Up to 2 KB EEPROM
Digital Subsystem Digital Subsystem
• Up to 24 Universal Digital Blocks of programmable • Up to 24 Universal Digital Blocks of programmable
logic logic
• CAN 2.0 • DMA
• Full-speed USB 2.0 • Full-speed USB 2.0
• Digital Filter Block (48-bit digital signal co- • Digital Filter Block (48-bit digital signal co-
processor) processor)
• Up to four configurable timer/counter/PWMs • Up to four configurable timer/counter/PWMs
Analog Subsystem Analog Subsystem
• Up to four configurable analog blocks • Up to four configurable analog blocks
• 8-bit to 20-bit configurable delta-sigma ADC • 8-bit to 20-bit configurable ∆Σ ADC
• Up to four 8-bit current DACs • Up to two 12-bit 1MSPS SAR ADCs
• Up to four fast analog comparators • Up to four 8-bit DACs
• Up to four fast opamps • Up to four fast analog comparators
• CapSense • Up to four fast opamps
I/O Subsystem • CapSense
• Analog or digital on any GPIO fully routable I/O Subsystem
• Four I/O Voltage Domains • Analog or digital on any GPIO fully routable
• Up to 5.5 V I/O • Four I/O Voltage Domains
• 25mA drive capability • Up to 5.5 V I/O
• Configurable pull-up/down, open drain high/low, • 25 mA drive capability
push-pull, high-z
• Configurable pull-up/down, open drain high/low,
push-pull, high-z
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