ECE-290

Unit 1 Combinational logic circuit and sequential

logic
Half Adder
 S=a’b+ab’
 C=a.b
Full Adder
 S=a’bc’+ab’c’+a’b’c+abc
 C=a’bc’+ab’c’+abc’+abc
WAP for full adder
module Fulladder(Sum, Cout, a,b,Cin);
output Sum, Cout;
input a,b,Cin;
wire S1, C1,C2;
xor X1(S1,a,b);
and A1(C1,a,b);
xor X2(Sum, S1, Cin);
and A2(C2,S1,Cin);
xor X3(Cout, C2,C2);
endmodule
Half Subtractor
 Diff=x’y+xy’
 Bout=x’y
Full subtractor
 Diff=a’bc’+ab’c’+a’b’c+abc
 Bout=a’b’c+a’bc’+a’bc+abc
Multiplexer
 A multiplexer or data selector is a logic circuit that accepts
several data inputs and allows only one of them at time to get
through the output.
 A general multiplexer (MUX) with n – input signals, m –
data select inputs or control signals and one output signal is
shown in the figure.
Contd.
 2x1 Multiplexer: out=S’.I0+S.I1

 4x1 Multiplexer out=s0’.s1’.c0+

s0.s1’c1+s0’s1.c2+s0s1c3
Contd.
De-multiplexer
Decoder
Contd.
Contd.
Encoder
Contd.
Contd.
 An encoder is a digital circuit that performs the inverse
operation of a decoder. An encoder has 2power n (or fewer)
input lines and n output lines.
 The output lines, as an aggregate, generate the binary code
corresponding to the input value
 Eg. Octal to binary
z = D1 + D3 + D5 + D7
y = D2 + D3 + D6 + D7
x = D4 + D5 + D6 + D7
Octal to binary
Decimal to BCD
Priority Encoder
 A priority encoder is an encoder circuit that includes the
priority function.
 The operation of the priority encoder is such that if two or
more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence.
 Finite State Machine
(Mealy and Moore machine)
Finite State Machine
Moore:
 Output depends only on present state of memory element
 No of states are more in comparison to Mealy Model
 Output transition occurs

Mealy
 Output depends only on present state of memory element and external input.
 No of states are less in comparison to Moore Model
 Output transition occurs only after the clock edge.
Synchronous Sequence Circuits
1) Moore circuit:
The sequential circuit is called as a Moore circuit if the
output depends only on the present state of the flip flops.
2) Mealy circuit:
The circuit is called as a Mealy circuit if the output depends
on the present state of the flip flops and the external
inputs.
 A: Designate carry 0
B: Designate carry 1

Serial Binary Adder x1

Serial S
adder
x2
Pattern or Sequence detector
 The stream of bit has been taken as input, when the clock is high and a particular
pattern/sequence is detected.
 As soon as sequence is detected the output becomes high and then again becomes low.

 X = 0110010100......
 Y = 0000001010
1) Overlapping
2) Non overlapping
 Let us input sequence is = 010
 State diagram:
 S0= Reset(power-up)
 S1= 0
 S2= 01
Sequence Detector
 Sequence : 1010
 Sates are A 00 ; B 01 ; C 10 ; D 11
Contd.
Excitation Table: Sequence Detector for 1010
Sequence Detector: Logic Diagram
LFSR(Linear Feedback Shift Register)

LFSR Types
Standard LFSR
 An n-stage standard LFSR. It consists of n D flip-flops and a
selected number of exclusive-OR (XOR) gates.
 XOR gates are placed on the external feedback path
 standard LFSR is also referred to as an external-XOR LFSR
Modular LFSR
 A n-stage modular LFSR with each XOR gate placed between
two adjacent D flip-flops, also known as an internal-XOR LFSR
 The modular LFSR runs faster than its corresponding standard
LFSR, because each stage introduces at most one XOR-gate delay.
LFSR
Example LFSR
Design a sequence detector to detect three or more consecutive 1’s
in a string of bits coming through an input line

 X= 00111011110.....
 Y= 00001000110...... Overlapping
 Y= 00001000100.......Non overlapping
 States:

 S0=Reset
 S1=1
 S2=11
 S3=111
  State table:

P.S. X N.S. Y
Qa Qb Qa+ Qb+
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Seq. Detection 011 using Mealy
4 bit Ripple/Parallel carry full adder
WAP for 4 bit ripple carry full adder
module fulladder4(Sum, Cout, a,b, Cin);
output [3:0] Sum;
output Cout;
input [3:0] a,b;
input Cin;
wire c1,c2,c3;
Fulladder fa1(Sum[0],c1,a[0],b[0],Cin);
Fulladder fa2Sum[1],c2,a[1],b[1],c1);
Fulladder fa3(Sum[2],c3,a[2],b[2],c2);
Fulladder fa4(Sum[3],Cout,a[3],b[3],c3);
endmodule