Vivekanand Education Society’s Institute of Technology

Department of Computer Engineering

CSC302 – Digital Logic Design and Analysis

REFERENCE LAB MANUAL

S.E.(CMPN) /SEM III/D7
ACADEMIC YEAR: 2018-2019
 Vivekanand Education Society’s Institute of Technology
Department of Computer Engineering

SUBJECT:DLDA SUBJECT CODE:CSC302

CLASS : SE SEM :III

Sr. No. List of Experiments COs

1 To study and verify the truth table of various logic gates CO2
using ICs and realize Boolean expressions using gates
2 To realize basic gates using universal gates to realize CO2
Boolean expression using universal gates
3 To realize binary to gray code and gray code to binary CO2, CO3
converter.
4 To realize arithmetic circuits CO2, CO3
i) Half adder ii) Full adder
iii) Half subtractor iv) Full subtractor
5 To realize parity generator and detector. CO2, CO3

6 To Study multiplexer IC and realization of full adder using CO2, CO3

multiplexer IC
7 To Study decoder IC and realization of combinational logic CO2, CO3
using decoder IC
8 Study of flip-flops using IC’s CO4

9 To realize asynchronous 3 bit up counter. CO4

10 To realize shift registers using flip flops CO4

11 To realize basic gates using VHDL CO3,CO5

12 To realize 4 bit counter using VHDL CO4, CO5

Hardware and software used :

● Digital IC’s
● Digital trainer kits
● Xilinx simulation/synthesis software
 Experiment No.1

Aim:
A) To study and verify the truth table of various logic gates using ICs
B) Realize Boolean expressions using gates.

Apparatus:
S.
COMPONENT SPECIFICATION QUANTITY
No

1. OR GATE IC 7432 1

2. NOT GATE IC 7404 1

3. AND GATE IC 7408 1

4 NOR GATE IC 7402 1

5 NAND GATE IC 7400 1

6 EX-OR GATE IC7486 1

7. TRAINER KIT - 1

CONNECTING
5. - -
WIRES

Theory:
A) To study and verify the truth table of various logic gates using ICs
Logic Gates are electronic circuits that operate on one or more input signals to produce an output signal. The
form the building blocks of all digital systems.OR, NOT and AND are basic gates. All the logic functions are
commercially available in integrated circuit (IC) form.
AND GATE (IC 7408):
The AND Gate performs logical multiplication known as AND operation. The output is high when all outputs
are high and low if any one of the inputs is low. IC 7408 is Quad 2-Input AND gate. Logical AND function is
given by:
Y = A AND B = A.B
NOT GATE (IC 7404):
The NOT Gate performs inverting or complementing operation. It is thus called as an inverter. The output is
high when the input is low and it is low when the input is high. IC 7404 has hex inverters. Logical NOT
function is given by:
Y = NOT A = A’
The OR GATE (IC 7432):
The OR Gate performs logical addition known as OR operation. The output is low when all inputs are low and
high when any one of the inputs is high. IC 7432 is Quad 2-Input OR gate.

Logical OR function is given by:

Y= AOR B= A+B

The NAND Gate(IC 7400)

The NAND gate implements the NAND function, which is exactly inverted from the AND function
you already examined. With the gate shown to the left, both inputs must have logic 1 signals applied
to them in order for the output to be a logic 0. With either input at logic 0, the output will be held to
logic 1.
The NOR Gate(IC 7402)
The NOR gate is an OR gate with the output inverted. Where the OR gate allows the output to be
true (logic 1) if any one or more of its inputs are true, the NOR gate inverts this and forces the output
to logic 0 when any input is true.

The EX-OR Gate(IC 7486)

The EX-OR gate produces an output as 1, when number of 1’s at it’s input is odd otherwise output is
0.

Procedure:

1) Mount the basic gate IC on the breadboard of the trainer kit.

2) Apply Vcc(+5V) and ground to the IC.

3) Connect input switches to the inputs of the IC and connect output of the gate to the
output LEDs.
4) Verify the truth table of all the gates by applying inputs the gates.
 B)Implementation of Boolean expressions using gates

After understanding the implementation of basic gates using IC’s, We can able to realize Boolean
expression with the help of basic gates. An example for the realization of Boolean expression is as
follow:

Procedure:

1) Make the connections basic gate IC on the breadboard as per the given boolean expression.

2) Apply Vcc(+5V) and ground to the IC.

3) Connect input and output as per the diagram.
4) Verify the truth table by applying different inputs the circuit.

Conclusion :
A) Truth table, Symbols and pin diagram of Logic Gates:-
1) Inverter/ NOT Gate (IC 7404):

2) AND Gate (IC 7408):

3) OR Gate (IC 7432):

4) NAND Gate (IC7400):
5) NOR Gate(IC7402):-
 IC 7402

5) EX-OR Gate (IC 7486):-

B) The circuit diagram and its truth table to implement the expression
X= (A+B)(B’+C)
 Truth Table

A B C B’ A+B B’+C Output X

0 0 0 1 0 1 0

0 0 1 1 0 1 0

0 1 0 0 1 0 0

0 1 1 0 1 1 1

1 0 0 1 1 1 1

1 0 1 1 1 1 1

1 1 0 0 1 0 0

1 1 1 0 1 1 1
 Experiment No. 2
Aim:
A) Realization of basic gates using universal gates
B) To realize Boolean expressions using universal gates.

Apparatus:
S. No COMPONENT SPECIFICATION QUANTITY

1. NAND GATE IC 7400 1

2. NOR GATE IC 7402 1

3. TRAINER KIT - 1

4. CONNECTING WIRES - -

Theory:
A) Realization of basic gates using universal gates
The NAND and NOR are called as universal gates because we can built any function using only
NAND gates or only NOR gates.
NAND GATE :
i) NAND AS NOT : The output expression of the NAND gate is Y = A.B The fig 1 shows the
implementation of the NOT gate using NAND gate. As both the inputs are connected together we can
write

A=B
Y = A.B
Y = A.A
Y = Ā this is the Boolean expression for the NOT gate.

ii) NAND AS AND : The output expression of the NAND gate is Y = A.B The fig 2 shows the
implementation of the AND gate using NAND gate. The Boolean expression for the AND gate is

Y = A.B taking double inversion of R.H. S. and from figure

Y = A.B

This is the expression for AND gate.

 iii) NAND AS OR : Fig 3 shows the implementation of OR gate using NAND gate.
From figure
________ ________
________ __ __
Y= A + B = A B=A+B
This is the expression for the OR gate.

NOR GATE : All gates can be implemented using NOR similar to NAND gates.

Procedure:
1) Mount the required IC on the bread board and make the connections as per the diagram.
2) Give the + 5 Vcc supply to IC pin no. 14 and Gnd to IC pin no.7 with the help
of connecting wires.
3) With the connecting wires give the logical inputs to the required pins.
4) Connect the output pin across the logical terminal to check.
5) Vary the inputs and record the corresponding outputs in tabular form.
6) Compare the output with the corresponding truth table.

B) To realize Boolean expressions using universal gates.

After understanding the implementation of basic gates using Universal gate, We can able to realize
Boolean expression with the help of universal gates.
1) An example for the realization of Boolean expression using NAND is as follow:
F = A B + CD

2) An example for the realization of Boolean expression using NOR is as follow:

Y = A B + CD
 .. Using Demorgan's theorem

Conclusion :
B) 1) The truth table to implement the expression Z = A.B + C.D

2) The circuit diagram to implement the expression Z = A.B + C.D using NAND gate
3) The circuit diagram to implement the expression Z = A.B + C.D using NOR gate
 Experiment No-3

Aim: To realize binary to gray code and gray code to binary converter.
Apparatus: Ic Trainer kit, IC7486,Single stand wires
Theory:
It is a logic circuit whose inputs are bit patterns representing the numbers in one and
whose outputs are corresponding representations in different codes.
E.g. A binary to gray code converter has 4 binary input lines B3, B2, B1, and B0. When input is
0010 for instance the output should be 0011.
To design code converter, we use Code Table to express each output as Boolean Algebraic
Function of all the inputs.
The logic expression entered for code conversion can be simplified using usual
techniques including unweighted code. Some cell numbering methods, which we used earlier,
can be used but cell number must correspond to input combinations as if they were an 8421 code.
Integrated circuits are available to convert data from one form to another. Binary or BCD
conversions are most often encountered in connections with computer applications. Numerical
data is transmitted in BCD form from the input devices. The data must be converted to Binary so
that arithmetic operations convert it to BCD for transmission to the output devices. Therefore,
conversions are often accomplished by using major components of computer itself rather than
special converter circuits. In some systems, conversions are accomplished by the system itself
through execution of specially designed.
1) Binary to gray code conversion is a very simple process. There are several steps to do
this types of conversions. Steps given below elaborate on the idea on this type of
conversion.
1. The M.S.B. of the gray code will be exactly equal to the first bit of the given binary
number.
2. Now the second bit of the code will be exclusive-or of the first and second bit of the
given binary number, i.e if both the bits are same the result will be 0 and if they are
different the result will be 1.
3. The third bit of gray code will be equal to the exclusive-or of the second and third bit
of the given binary number. Thus the Binary to gray code conversion goes on. One
example given below can make your idea clear on this type of conversion.
Thus the equivalent gray code is 01101.
Now concentrate on the example where the M.S.B. of the binary is 0 so for it will be 0 for the
most significant gray bit. Next, the XOR of the first and the second bit is done. The bits are
different so the resultant gray bit will be 1. Again move to the next step, XOR of second and
third bit is again 1 as they are different. Next, XOR of third and fourth bit is 0 as both the bits are
same. Lastly the XOR of fourth and fifth bit is 1 as they are different. That is how the result of
binary to gray code conversion of 01001 is done whose equivalent gray code is 01101.

2) Gray code to binary conversion

Gray code to binary conversion is again very simple and easy process. Following steps can
make your idea clear on this type of conversions.
1. The M.S.B of the binary number will be equal to the M.S.B of the given gray code.
2. Now if the second gray bit is 0 the second binary bit will be same as the previous or
the first bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0
and if it was 0 it will be 1.
3. This step is continued for all the bits to do Gray code to binary conversion.
One example given below will make your idea clear.

The M.S.B of the binary will be 0 as the M.S.B of gray is 0. Now move to the next gray bit. As it
is 1 the previous binary bit will alter i.e it will be 1, thus the second binary bit will be 1. Next
look at the third bit of the gray code. It is again 1 thus the previous bit i.e the second binary bit
will again alter and the third bit of the binary number will be 0. Now, 4th bit of the given gray is
0 so the previous binary bit will be unchanged, i.e 4th binary bit will be 0. Now again the 5th
grey bit is 1 thus the previous binary bit will alter, it will be 1 from 0. Therefore the equivalent
Binary number in case of gray code to binary conversion will be (01001).

Procedure:
1 The circuit Diagram and the connections are as shown in the figure.
2. Use the IC 7486
3. Connect pin 14 to the VCC and Pin 7 to the Ground
4. In case of Binary to Gray conversion the inputs are B0 to B3. Are given at the respective
inputs pins and output G0to G3 are taken for all the 16 combination of the inputs.
5. .In case of Gray to Binary conversion the inputs are G0 to G3. Are given at the respective
inputs pins and output B0 to B3 are taken for all the 16 combination of the inputs.

Conclusion:
(To be write on blank side)
Truth Table-

Decimal Binary Gray code

0 0000 0000

1 0001 0001

2 0010 0011

3 0011 0010

4 0100 0100

5 0101 0111

6 0110 0101
 7 0111 0100

8 1000 1100

9 1001 1101

10 1010 1111

11 1011 1110

12 1100 1010

13 1101 1011

14 1110 1001

15 1111 1000

K-MAPS:
K-MAP FOR G3:

Equation for G3= B3

K-MAP FOR G2:

Equation for G2= B3’ B2 + B3 B2’= B3 XOR
B2 K-MAP FOR G1:

Equation for G1= B1’ B2 + B1 B2’= B1 XOR

B2 K-MAP FOR G0:
Equation for G0= B1’ B0 + B1 B0’= B1 XOR B0

K-MAP FOR Binary code:

Circuit Diagram for Binary to gray code

Circuit Diagram for gray to Binary code

 Experiment No. 4

Aim:- Realization of arithmetic circuits

i) Half adder ii) Full adder
iii) Half subtractor iv) Full subtractor

Apparatus:
S. No COMPONENT SPECIFICATION QUANTITY

1. AND GATE IC 7408 1

2 EX-OR GATE IC 7486 1

3 OR GATE IC 7432 1

4 NOT GATE IC 7404 1

5. TRAINER KIT - 1

6. CONNECTING WIRES - -

Theory:

1)Half-Adder

Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum bit (S) and
carry bit (C) as the output. If A and B are the input bits, then sum bit (S) is the X-OR of A and B and the
carry bit (C) will be the AND of A and B. From this it is clear that a half adder circuit can be easily
constructed using one X-OR gate and one AND gate. Half adder is the simplest of all adder circuit, but it
has a major disadvantage. The half adder can add only two input bits (A and B) and has nothing to do
with the carry if there is any in the input. So if the input to a half adder have a carry, then it will be
neglected it and adds only the A and B bits. That means the binary addition process is not complete and
that’s why it is called a half adder.
From the truth table the expression for sum and carry bits of the output can be obtained
as, Sum, S = A xor B
Carry, C = A . B
2)Full-Adder
A full-adder is a logic circuit having 3 inputs A,B and C ( which is the carry from the previous stage) and
2 outputs (Sum and Carry), which will perform according to table 3. The full-adder can handle three
binary digits at a time and can therefore be used to add binary numbers in general. The simplest way to
construct a full adder is to connect twohalf- adder and an OR gate as shown in Fig. The full-adder

is then the fundamental logic circuit incorporated in digital computers to perform arithmetic
functions.

From the truth table the expression for sum and carry bits of the output can be obtained as,

SUM = A XOR B XOR C

CARRY = AB + BC +AC

Subtractor
The arithmetic operation, subtraction of two binary digits has four possible elementary operations,
namely,

0-0=0
0 - 1 = 1 with 1 borrow
1-0=1
1-1=0
In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the second operation
the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.
3) Half subtractor:
A combinational circuit which performs the subtraction of two bits is called half sub tractor. The input
variables designate the minuend and the subtrahend bit, whereas the output variables produce the
difference and borrow bits.
From the truth table the expression for difference and borrow bits of the output can be obtained as,
Difference, DIFF = A XOR B
Borrow, BORR = A’ . B
4) Full subtractor:
The half subtractor can be used only for subtraction of the least significant bit of two n-bit binary nos.
since they can operate on only two bits. For higher columns a circuit known as full subtractor is
required which operates on three bits. The third bit is borrow bit from the minuend of the next column
of bits. Hence a full subtractor is a logic circuit with three inputs and two outputs.
DIFF = AB’C’ + A’B’C + A’BC’ + ABC = A XOR B XOR C
BORR = A’B + A’C + BC
Procedure:
1) Mount the required IC’s on the bread board and make the connections as per the diagram.
2) Give the + 5 Vcc supply to IC pin no. 14 and Gnd to IC pin no.7 with the help of
connecting wires.
3) With the connecting wires give the logical inputs to the required pins.
4) Connect the o/p pin across the logical o/p terminal.
5) Vary the inputs and record the corresponding outputs in tabular form.
6) Compare the output with the corresponding truth table.

.Conclusion:
1)Half adder
Truth table

Input to adder Output

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

2) Full adder

INPUT OUTPUT
S.No
A B C SUM CARRY
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
Design using k-map
SUM

SUM = A XOR B XOR C

CARRY

CARRY = AB + BC +AC

3) Half subtractor
INPUT OUTPUT
S.No
A B DIFF BORR
 1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0

DIFF = A XOR B
BORR = A’ . B
4) Full subtractor
Truth Table

INPUT OUTPUT
S.No
A B C DIFF BORR
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
Difference

DIFF = A XOR B XOR C

Borrow

BORR = A’B + A’C + BC

 Experiment No-5
Aim: To realize parity generator and detector.
Apparatus:
S. No COMPONENT SPECIFICATION QUANTITY

1. EX-OR GATE IC 7486 1

2 EX-NOR GATE IC 74266 1

3. TRAINER KIT - 1

4. CONNECTING WIRES - -

Theory:

A parity generator is a combinational logic circuit that generates the parity bit in the transmitter.
On the other hand, a circuit that detects the parity in the receiver is called parity detector. A
combined circuit or devices of parity generators and parity detectors are commonly used in
digital systems to detect the single bit errors in the transmitted data word.

The sum of the data bits and parity bits can be even or odd . In even parity, the added parity bit
will make the total number of 1s an even amount whereas in odd parity the added parity bit will
make the total number of 1s odd amount.

The basic principle involved in the implementation of parity circuits is that sum of odd number
of 1s is always 1 and sum of even number of 1s is always zero. Such error detecting and
correction can be implemented by using Ex-OR gates (since Ex-OR gate produce zero output
when there are even number of inputs).

1)Parity Generator

It is combinational circuit that accepts an n-1 bit stream data and generates the additional bit that
is to be transmitted with the bit stream. This additional or extra bit is termed as a parity bit.

In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data stream
and the parity bit is ‘1’ if there are odd number of 1s in the data stream.
In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data stream and
the parity bit is ‘0’ if there are odd number of 1s in the data stream. Let us discuss both even and
odd parity generators.

a)Even Parity Generator

Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the three
inputs A, B and C are applied to the circuits and output bit is the parity bit P. The total number of
1s must be even, to generate the even parity bit P.

The K-map simplification for 3-bit message even parity generator is shown

From the above Kmap, the simplified expression of the parity bit can be written as

The above expression can be implemented by using two Ex-OR gates.

b)Odd Parity Generator

Let us consider that the 3-bit data is to be transmitted with an odd parity bit. The three inputs are
A, B and C and P is the output parity bit. The total number of bits must be odd in order to
generate the odd parity bit.

The truth table of the odd parity generator can be simplified by using K-map as
The output parity bit expression for this generator circuit is obtained as

P = A ⊕ B Ex-NOR C

The above Boolean expression can be implemented by using one Ex-OR gate and one Ex-NOR
gate in order to design a 3-bit odd parity generator.

The logic circuit of this generator is shown in below figure , in which . two inputs are applied at
one Ex-OR gate, and this Ex-OR output and third input is applied to the Ex-NOR gate , to
produce the odd parity bit. It is also possible to design this circuit by using two Ex-OR gates and
one NOT gate.

2) Parity Detector

It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even
parity checker or odd parity checker depending on the type of parity generated at the
transmission end. When this circuit is used as even parity checker, the number of input bits must
always be even.

When a parity error occurs, the ‘sum even’ output goes low and ‘sum odd’ output goes high. If
this logic circuit is used as an odd parity checker, the number of input bits should be odd, but if
an error occurs the ‘sum odd’ output goes low and ‘sum even’ output goes high.

a) Even Parity Detector

Consider that three input message along with even parity bit is generated at the transmitting end.
These 4 bits are applied as input to the parity checker circuit which checks the possibility of error
on the data. Since the data is transmitted with even parity, four bits received at circuit must have
an even number of 1s.

If any error occurs, the received message consists of odd number of 1s. The output of the parity
checker is denoted by PEC (parity error Detect).
The above truth table can be simplified using K-map as shown below.

b) Odd Parity Detector

Consider that a three bit message along with odd parity bit is transmitted at the transmitting
end. Odd parity checker circuit receives these 4 bits and checks whether any error are present in
the data.

If the total number of 1s in the data is odd, then it indicates no error, whereas if the total number
of 1s is even then it indicates the error since the data is transmitted with odd parity at
transmitting end.

After simplification of Kmap, the final expression for the PEC is obtained as

PEC = (A Ex-NOR B) Ex-NOR (C Ex-NOR D)

Conclusion:
 1) Even Parity Generator

The figure below shows the truth table of even parity generator in which 1 is placed as parity bit
in order to make all 1s as even when the number of 1s in the truth table is odd.

The K-map simplification for 3-bit message even parity generator is shown

The logic diagram of even parity generator with two Ex – OR gates is shown below.
 2) Odd Parity Generator

In the given truth table below, 1 is placed in the parity bit in order to make the total number of
bits odd when the total number of 1s in the truth table is even.

The truth table of the odd parity generator can be simplified by using K-map as
The logic diagram of odd parity generator with two Ex – OR gates is shown below.

3) Even Parity Detector

The above truth table can be simplified using K-map as shown below.

The above logic expression for the even parity checker can be implemented by using three Ex-
OR gates as shown in figure.
3) Odd Parity Detector

The below figure shows the truth table for odd parity generator

The expression for the PEC in the above truth table can be simplified by K-map as shown below.
The expression for the odd parity checker can be designed by using three Ex-NOR gates as
shown below.
 Experiment No. 6
Aim: ToStudy multiplexer IC and Realization of full adder using multiplexer IC.
Apparatus:

S. No COMPONENT SPECIFICATION QUANTITY

1. Multiplexer IC 74151 1

4. TRAINER KIT - 1

5. CONNECTING WIRES - -

Theory:

A multiplexer (MUX) is a digital switch which connects data from one of n sources to the output. A
number of select inputs determine which data source is connected to the output. The block diagram of
MUX with n data sources of b bits wide and s bits wide select lines.

MUX acts like a digitally controlled multi-position switch where the binary code applied to the select
inputs controls the input source that will be switched on to the output as shown in the figure below. At
any given point of time only one input gets selected and is connected to output, based on the select input
signal.

IMPLEMENTATION OF FULL ADDER USING 74151 IC (8x1MUX)

MUX:
2n ->1.
n = No. of select lines.
2n = No. of inputs of MUX
if n = 3, size of MUX is 8x1 i.e.

The output expressions of full adder are as follows:

S(x,y, z)= m(1, 2, 4, 7)
C(x,y, z)= m(3, 5, 6, 7)

First of all we check/implement Carry of Full Adder (having 3 inputs) using 8X1 Mux, for this take :

I0 = 0, I1 = 0, I2 = 0, I3 = 1, I4 = 0, I5 = 1, I6 = 1, I7 = 1, from Carry column of Truth table of Full Adder

and then select x,y,z from Function table of 8X1 Mux and then observe outputs at Y Pin of 74151 IC, that
should be equal to Carry of Full Adder for combination of x,y,z at select lines, which is inserted through
data switches, this step is repeated for all x,y,z combinations, at select lines to observe Carry of Full
Adder.

Then we check/implement Sum of Full Adder for 3 input variables, using 8X1 Mux for this, we take :

I0 = 0, I1 = 1, I2 = 1, I3 = 0, I4 = 1, I5 = 0, I6 = 0, I7 = 1, from Sum column of Truth Table of Full Adder,

as data inputs to 8X1 Mux, and then for each combination of x,y,z at select lines from Function table. We
see output at Y Pin of 74151 IC, which should be equal to value of Sum of Full Adder for x,y,z
combination at select lines, which is inserted through data switches, this step is repeated for all x,y,z
combinations, at select lines to observe Sum of Full Adder.

Procedure :-
1) Mount the required IC’s on the bread board and make the connections as per the diagram.
2) Give the + 5 Vcc supply and Gnd to IC pins with the help of connecting wires.
3) With the connecting wires give the input to the required pins.
4) Connect the o/p pin across the logical o/p terminals
5) Verify the truth table of full adder.

Conclusion:
.
Block diagram of 8:1 multiplexer

Function Table

Pin Configuration of 74151 MUX

 Experiment No 7
Aim: To Study decoder IC and realization of combinational logic using decoder IC
Apparatus:

S. No COMPONENT SPECIFICATION QUANTITY

1. Decoder IC 74138 1

2 OR GATE IC 7432 1

3. TRAINER KIT - 1

4. CONNECTING WIRES - -

Theory:
Decoder:-
A decoder is a device which does the reverse of an encoder, undoing the encoding so that the original
information can be retrieved. The same method used to encode is usually just reversed in order to decode.

In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs, where the input and output codes are different. e.g. n-to-2n ,
binary coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise its
outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data
multiplexing, 7 segment display and memory address decoding.

Example: A 2-to-4 Line Single Bit Decoder

A slightly more complex decoder would be the n-to-2n type binary decoders. These types of decoders are
combinational circuits that convert binary information from 'n' coded inputs to a maximum of 2n unique
outputs. We say a maximum of 2n outputs because in case the 'n' bit coded information has unused bit
combinations, the decoder may have less than 2n outputs. We can have 2-to-4 decoder, 3-to-8 decoder or
4- to-16 decoder. We can form a 3-to-8 decoder from two 2-to-4 decoders (with enable signals).

Similarly, we can also form a 4-to-16 decoder by combining two 3-to-8 decoders. In this type of circuit
design, the enable inputs of both 3-to-8 decoders originate from a 4th input, which acts as a selector
between the two 3-to-8 decoders. This allows the 4th input to enable either the top or bottom decoder,
which produces outputs of D(0) through D(7) for the first decoder, and D(8) through D(15) for the second
decoder.

A decoder that contains enable inputs is also known as a decoder-demultiplexer. Thus, we have a 4-to-
16decoder produced by adding a 4th input shared among both decoders, producing 16 outputs.

Design a Full Adder using Decoder IC.

A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three inputs
and two outputs. IC 74138 is a 3:8 line decoder IC.

The minterms for sum and carry are as follows

S= Σm (1,2,4,7)

C= Σm (3,5,6,7)

To get the Sum OR the min terms 1,2,4,7 and to get Carry the minterms 3,5,6,7 are ORed.

Procedure :-
1) Mount the required IC’s on the bread board and make the connections as per the diagram.
2) Give the + 5 Vcc supply and gnd to IC pins with the help of connecting wires.
3) With the connecting wires give the input to the required pins.
4) Connect the o/p pin across the logical o/p terminals
5) Verify the truth table of full adder.

Conclusion:
Pin diagram of 74138

TRUTH TABLE OF FULL ADDER:

From the truth table, we get:-

S= Σm (1,2,4,7)
C= Σm (3,5,6,7)
Full adder using 74138
 Experiment No 8
Aim:Study of flip flops using IC's
Apparatus:

S. No COMPONENT SPECIFICATION QUANTITY

1. D flip flop IC 7474 1

2 JK flip flop IC 7476 1

3. TRAINER KIT - 1

4. CONNECTING WIRES - -

Theory:
Flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two
inputs/outputs, designed using individual logic gates and feedback loops.

JK flip flop

The JKflip-flop augments the behavior of the SR flip-flop by interpreting the S = R = 1 condition as a
"flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop;
the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a
command to toggle the flip-flop, i.e., change its output to the logical complement of its current value.

The characteristic equation of the JK flip-flop is:

The 74F76 is a dual negative edge-triggered JK flip-flop featuring individual J, K, clock, preset, and
clear inputs; also true and complementary outputs. Preset (PRE) and clear (CLR) are asynchronous active
low inputs and operate independently of the clock input.

D flip flop
The Q output always takes on the state of the D input at the moment of a rising clock edge, and never at
any other time. It is called the Dflip-flop for this reason, since the output takes the value of the Dinput or
Datainput, and Delaysit by one clock count.
The characteristic equation of the D flip-flop is:
Q =D
next

The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, preset, and
clear inputs; also true and complementary outputs. Preset (PRE) and clear (CLR) are asynchronous active
low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the
D input is transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be
stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the transition time of the positive-going
pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of
the output.

Procedure :-
1) Mount the required IC’s on the bread board and make the connections as per the diagram.

2) Give the + 5 Vcc and Gnd to IC with the help of connecting wires.

3) With the connecting wires give the logical inputs to the required pins.
4) Connect the o/p pin across the logical output terminals.(Q, Q ).
bar

5) Apply different inputs and verify the truth table..

Conclusion :
JK Flip-flop

The Truth Table for the JK Function

Input Output
Description
J K Q Q
0 0 0 0 Memory
same as
for the 0 0 0 1 no change
SR Latch 0 1 1 0
Reset Q » 0
0 1 0 1
1 0 0 1
Set Q » 1
1 0 1 0
toggle 1 1 0 1
Toggle
action 1 1 1 0
 Experiment No 9

Aim: To realize asynchronous 3 bit up counter.

Implementation of 3-bit up asynchronous counter using JK flip flop..

Apparatus:

S. No COMPONENT SPECIFICATION QUANTITY

1 JK flip flop IC 7476 1

3. TRAINER KIT - 1

4. CONNECTING WIRES - -

Theory:

Asynchronous counter: The state change of one flip-flop triggers the next flip-flop in line.
The circuit below is a 3-bit up counter. J-K flip-flops connected in such a way to always be in the “toggle”
mode. The main clock is applied to the first flip- flop and Q output of first flip-flop will serve as clock to
next flip –flop. Same way the Q output of second flip flop serve as a clock to third flip flop. The output
for the counter is taken from output Q of each flip-flop.

Procedure :-
1) Mount the required IC’s on the bread board and make the connections as per the diagram.

2) Give the + 5 Vcc and Gnd to IC with the help of connecting wires.

3) With the connecting wires give the clock input and up/down input to the required pin.

4) Connect the o/p pin across the logical o/p terminals

5) Apply the clock and up/down input and verify the up and down counter operation.

Conclusion :
3 bit (MOD-8) UP COUNTER CIRCUIT DIAGRAM:

Timing diagram :
 Experiment No. 10

Aim :-To realize shift registers using flip flops

Apparatus:

S. No COMPONENT SPECIFICATION QUANTITY

1 D flip flop IC 7474 1

2 AND Gate IC 7408 1

3 OR Gate IC 7432 1

4. TRAINER KIT - 1

5. CONNECTING WIRES - -

Theory:
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of
flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-
flop. Most of the registers possess no characteristic internal sequence of states.

All flip-flop is driven by a common clock, and all are set or reset simultaneously.

Types of shift registers are

1.Serial In - Serial Out

2.Serial In - Parallel Out

3. Parallel In – Serial Out

4.Parallel In - Parallel Out

Serial In - Serial Out Shift Registers

The serial in/serial out shift register accepts data serially – that is, one bit at a time on a single line. It
produces the stored information on its output also in serial form.

A basic four-bit shift register can be constructed using four D flip-flops.

Serial In - Parallel Out Shift Registers

For this kind of register, data bits are entered serially in the same manner as discussed in the last section.
The difference is the way in which the data bits are taken out of the register. Once the data are stored,
each bit appears on its respective output line, and all bits are available simultaneously. A construction of
a four-bit serial in - parallel out register is shown below.

Parallel In - Serial Out Shift Registers

A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-flops and NAND
gates for entering data (ie writing) to the register. D0, D1, D2 and D3 are the parallel inputs, where D0 is
the most significant bit and D3 is the least significant bit. To write data in, the mode control line is taken
to LOW and the data is clocked in. The data can be shifted when the mode control line is HIGH as
SHIFT is active high. The register performs right shift operation on the application of a clock pulse.

Procedure :-
4) Mount the required IC’s on the bread board and make the connections as per the diagram.
5) Give the + 5 Vcc and Gnd to IC with the help of connecting wires.
6) With the connecting wires give the clock input the required pin.
7) Connect the o/p pin across the logical o/p terminals
8) Apply the clock verify the shift register operation.

Conclusion :
1) SERIAL IN SERIAL OUT (SISO) (Right Shift)

2) SERIAL IN PARALLEL OUT

3) PARALLEL IN PARALLEL OUT
4:1 multiplexer
 Experiment No. 11
Aim: To realize basic gates using VHDL

Software:XILINX ISE 92.i

Theory:
VHDL is a hardware description language. It stands for VHSIC Hardware Description Language. VHSIC itself
stands for Very High Speed Integrated Circuits. It describes the behaviour of an electronic circuit or system,
from which the physical circuit or system can be attained (implemented). VHDL is intended for circuit
synthesis as well as circuit simulation. VHDL is a standard, technology/ vendor independent language, and is
therefore portable and reusable. The two main immediate applications of VHDL are in the field of
Programmable Logic Devices and ASICs (Application Specific Integrated Circuits). Once the VHDL code has
been written, it can be used either to implement the circuit in a programmable device (from Altera, Xilinx,
Atmel etc.) or can be submitted to a foundry for fabrication of an ASIC chip. Contrary to regular computer
programs which are sequential, its statements are inherently concurrent (parallel). For that reason, VHDL is
usually referred to as a code rather than a program.

1). AND Gate

Y=A.B
INPUT OUTPUT
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

Code:
----------------------------------------------------------------------------------
library IEEE; ----- library declaration
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ANDgate is ---- entity declaration

PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
 Y:OUT STD_LOGIC);
end ANDgate;

architecture Behavioral of ANDgate is ----architecture data flow modelling

begin
Y <= A and B;
end Behavioral;

2). OR Gate
Y=A+.B
INPUT OUTPUT
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1

Code:
----------------------------------------------------------------------------------
library IEEE; ----- library declaration
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ORgate is ---- entity declaration

PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y:OUT STD_LOGIC);
end ORgate;

architecture Behavioral of ORgate is ----architecture data flow modelling

begin
Y <= A or B;
end Behavioral;

3). NOT Gate

Z = NOT A
INPUT OUTPUT
A Y
0 1
0 0
 Code:
----------------------------------------------------------------------------------
library IEEE; ----- library declaration
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity NOTgate is ---- entity declaration

PORT (A: IN STD_LOGIC;
Y:OUT STD_LOGIC);
end NOTgate;

architecture Behavioral of NOTgate is ----architecture data flow modelling

begin
Y <= not A;
end Behavioral;

4). NAND Gate

Y=A NAND B
INPUT OUTPUT
A B Y=(A.B)\
0 0 1
0 1 1
1 0 1
1 1 0

Code:
----------------------------------------------------------------------------------
library IEEE; ----- library declaration
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity NANDgate is ---- entity declaration

PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y:OUT STD_LOGIC);
end NANDgate;

architecture Behavioral of NANDgate is ----architecture data flow modelling

begin
Y <= A nand B;
end Behavioral
5). NOR Gate
Z=A NOR B
INPUT OUTPUT
A B Z=(A+B)\
0 0 1
0 1 0
1 0 0
1 1 0

Code:
----------------------------------------------------------------------------------
library IEEE; ----- library declaration
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity NORgate is ---- entity declaration

PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y:OUT STD_LOGIC);
end NORgate;

architecture Behavioral of NORgate is ----architecture data flow modelling

begin
Y <= A nor B;
end Behavioral;

Conclusion:
Conclusion:
 Experiment No. 12
Aim:To realize 4 bit counter using VHDL

Software -XILINX ISE 92.i

Theory
Counters

A counter is a device which stores the number of times a particular event or process has occurred, often in
relationship to a clock signal. There are two types of counters:
● up counters
● down counters

Code for 4 bit up counter with asynchronous reset

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; -- library declaration

entity counter is
port(CLK, RST : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter; -- entity declaration

architecture archi of counter is

signal tmp: std_logic_vector(3 downto 0); --Behavioral modeling
begin
process (CLK, RST)
begin
if (RST='1') then
tmp <= "0000";
elsif (CLK'event and CLK='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;

Conclusion:
4 bit counter