ARMv8-A: Meet the Experts –

A Tour of the New GICv3 Architecture

Speakers:

Chris Shore, Training Manager, ARM

Martin Weidmann, Principal Applications Engineer, ARM

Moderator:

Brandon Lewis, OpenSystems Media

 Agenda

 Housekeeping
 Presentation
 Questions and Answers
 Wrap-up
 A tour of the new GICv3
architecture

GICv3/GICv4 Webinar
Introducing ourselves

Chris Shore Martin Weidmann

Training Manager Principal Applications Engineer

GICv3/GICv4 Webinar
GICv3/GICv4 Webinar
Where to find ARM documentation
 ARM’s documentation can be found at http://infocenter.arm.com/

 Useful sections:
 ARM architecture – ARM and GIC architecture reference manuals
 ARM Technical Support Knowledge Articles – FAQs
 Cortex-A/R/M series processors – Technical Reference Manuals
 Developer Guides and Articles – Detailed discussions of TrustZone, barriers…

GICv3/GICv4 Webinar
Global ARM support

GICv3/GICv4 Webinar
Active Assist

GICv3/GICv4 Webinar
ARM training

GICv3/GICv4 Webinar
Training options from ARM

Onsite, anywhere delivery ARM hosted Live broadcast from ARM

Face-to-face with ARM experts Public schedule Distributed teams
Customized agendas Open enrolment Targeted, agile delivery

GICv3/GICv4 Webinar
…and now available online

GICv3/GICv4 Webinar
 A tour of the new GICv3
architecture

GICv3/GICv4 Webinar
Generic Interrupt Controller
 ARM’s GIC architecture provides an efficient and standardized approach
for handling interrupts in multi-core ARM based systems

Generic Interrupt Controller

IRQ FIQ IRQ FIQ IRQ FIQ IRQ FIQ IRQ FIQ IRQ FIQ

Core Core Core Core …. Core Core

Cortex-A MPCore Cortex-A MPCore Cortex-A MPCore

 The GIC architecture provides:

 Controls for software to prioritize and target interrupts
 Private (per-core) and Shared peripheral interrupts
 Software generated interrupts, for inter-core/processor communication

 ARM has recently released the first public beta of the GICv3 and GICv4
specification

GICv3/GICv4 Webinar
GIC versions
GICv2 GICv3 GICv4

 Features:  Adds:  Adds:

 Up to 8 cores
 Up to 1020 interrupts
IDs
 Up to 8 bits of priority
 Software Generated
Interrupts
 TrustZone support
 Support for
virtualization
 Implemented by:  Implemented by:
 CoreLink™ GIC-400
 Support for many more  Direct injection of
than 8 cores virtual interrupts
 Support for message
based interrupts
 Enhanced security
model
 System register access
 Vastly expanded
interrupt ID space
 Support for legacy
operation giving
compatibility with GICv2
 CoreLink™ GIC-500

GICv3/GICv4 Webinar
Agenda

 System registers & Security

Support for large systems

Legacy operation

GICv4 virtualization

GICv3/GICv4 Webinar
System register interface
CPU interface registers  In GICv1/v2, all registers are memory
ICC_IGRPENn_EL1 mapped

ICC_PMR_EL1
 In GICv3, the CPU Interface registers can
ICC_BPRn_EL1 be accessed as ARM system registers
ICC_IARn_EL1  These are the GIC registers used when
handling interrupts
ICC_EOIRn_EL1
ICC_DIR_EL1  System register access requires the
ICC_RPR_EL1 processor implement to support
GICv3/GICv4
ICC_SGInR_EL1  ARM’s Cortex®-A53, Cortex-A57 and
Cortex-A72 all have the required support

GICv3/GICv4 Webinar
Security & group
 GICv3 supports three group/security settings
 Configured individually for each interrupt
 Provides better match with ARMv8-A security and exception model

 Group 0
 Group 0 interrupts are always secure
 Signalled as FIQ, regardless of current Security state
 Typically used for interrupts for the firmware running at EL3

 Secure Group 1
 Signalled as FIQ if core is in Non-secure state
 Signalled as IRQ if core is in Secure state
 Typically used for interrupts for the trusted OS

 Non-secure Group 1
 Signalled as FIQ if core is in Secure state
 Signalled as IRQ if core is in Non-secure state
 Typically used for interrupts for the rich OS or Hypervisor

GICv3/GICv4 Webinar
Routing example
Non-secure Secure
Non-secure Group 1 Secure Group 1

Secure Group 1 Trusted Non-secure Group 1

App EL0
Service
Group 0 Group 0

Trusted
Rich OS
OS
EL1

IRQ Vector IRQ Vector

Secure Monitor
EL3
FIQ Vector

SCR_EL3.FIQ=1 SCR_EL3.IRQ=0

GICv3/GICv4 Webinar
Agenda

System registers & Security

 Support for large systems

Legacy operation

GICv4 virtualization

GICv3/GICv4 Webinar
Redistributors
 GICv3 introduces Redistributors

GICv3/GICv4
Distributor

Redistributor Redistributor Redistributor Redistributor

CPU Interface CPU Interface CPU Interface CPU Interface

IRQ FIQ IRQ FIQ IRQ FIQ IRQ FIQ

Core Core Core Core

Multi-Core Processor Multi-Core Processor

 There is a Redistributor per-connected core, holding settings for private

interrupts (PPIs and SGIs)
 Allows for distributed designs with Redistributors kept close to target core

GICv3/GICv4 Webinar
Affinity levels and routing
 There is increasingly demand for systems with higher core counts

 GICv3 increases the number of cores that can be connected

 Connected cores identified by an affinity value, matching system used in ARMv8-A

Interrupt Distributor

Level 3 0.x.x.x

0.0.x.x 0.255.x.x
Level 2

0.0.0.x … 0.255.255.x
Level 1

Level 0 0 ..... 15 0 ..... 15

CPU Interface CPU Interface CPU Interface CPU Interface

0.0.0.0 0.0.0.15 0.255.255.0 0.255.255.15

 Each Shared Peripheral Interrupts can be separately configured as:

 Send to any connected core (referred to as “1 of N”)
 Send to one specific core (affinity coordinates of core written to register)
GICv3/GICv4 Webinar
Message based
 GICv3 adds support for message based interrupts
 Instead of requiring a dedicated signal, a peripheral writes a register in the GIC to
register an interrupt

IRQ

Peripheral GIC ARM

FIQ

Interrupt Interconnect
message

 Why?
 Can reduce the number of wires needed and ease routing
 Increasingly important as systems become larger, and number of interrupt sources increase
 Matches model used by PCIe

GICv3/GICv4 Webinar
LPIs
 GICv3 adds a new interrupt type – Locality-specific Peripheral Interrupt

 LPIs greatly expand the available interrupt ID range

 Use INTIDs 8192 to 16,777,216

 In order to provide a scalable solution, LPIs are different in a number of

ways to SPIs, PPIs and SGIs
 Configuration and state held in memory rather than registers
 Can only be Non-secure Group 1, and Active state not recorded
 Software is responsible for allocating and initializing the memory used
 Always message-based

 LPIs can be sent by a peripheral to the GIC in two ways:

 Directly to the Redistributor of the target core
 Via an ITS…

GICv3/GICv4 Webinar
 What is an ITS?
 An Interrupt Translation Service maps
interrupts to INTIDs and Redistributors

 How is an interrupt translated?

Device
Interrupt
Interrupt
Interrupt
Translation
Translation Collection
 Peripheral sends interrupt as a message to
Tables
Translation
Table Tables
Tables
Table the ITS
 The message specifies the DeviceID (which
peripheral) and an EventID (which interrupt
from that peripheral)
Redistributor  ITS uses the DeviceID to index into the
Peripheral Device Table
sends ITS Redistributor  Returns pointer to a peripheral specific Interrupt
interrupt as Translation Table
message to :
ITS  ITS uses the EventID to index into the
Redistributor
Interrupt Translation Table
 Returns the INTID and Collection ID
 ITS uses the Collection ID to index into the
Collection Table
 Returns the target Redistributor
 ITS forwards interrupt to Redistributor

GICv3/GICv4 Webinar
Controlling the ITS
 The ITS is controlled by a command queue (circular buffer) in memory
 Software maps/remaps interrupts by adding commands to the queue

 Example:
 A timer has DeviceID 5 and sends EventID 0
 We decide to map the interrupt to INTID 8725 and deliver it to Redistributor 6
 The per-device translation table for the timer is at physical address 0x84500000
 We decide to use collection number 3

 The command sequence we need is:

MAPD 5, 0x84500000, 2 Map DeviceID 5 to an Interrupt Translation Table,
with 2-bit EventID width
MAPTI 5, 0, 8725, 3 Map EventID 0 to INTID 8725 and collection 3
MAPC 3, 6 Map collection 3 to Redistributor number 6
SYNC 6 Synchronize changes on the Redistributor

GICv3/GICv4 Webinar
Agenda

System registers & Security

Support for large systems

 Legacy operation

GICv4 virtualization

GICv3/GICv4 Webinar
Legacy operation
 GICv3 optionally supports legacy operation, for compatibility with GICv2
 Can be configured separately for each Security state
 But only certain combinations are permitted

Non-secure Secure Non-secure Secure Non-secure Secure

ARE_NS=1 ARE_S=1 ARE_NS=1 ARE_S=0 ARE_NS=0 ARE_S=0

ICC_SRE_EL1.SRE=X ICC_SRE_EL1.SRE=1 ICC_SRE_EL1.SRE=X ICC_SRE_EL1.SRE=0 ICC_SRE_EL1.SRE=0 ICC_SRE_EL1.SRE=0 EL1

ICC_SRE_EL2.SRE=1 ICC_SRE_EL2.SRE=1 ICC_SRE_EL2.SRE=0

EL2

ICC_SRE_EL3.SRE=1 ICC_SRE_EL3.SRE=1 ICC_SRE_EL3.SRE=0 EL3

All GICv3 Legacy S.EL1 All legacy

(Virtual machines running at NS.EL1 can (Virtual machines running at NS.EL1 can
also optionally use legacy interface) also optionally use legacy interface)

GICv3/GICv4 Webinar
Agenda

System registers & Security

Support for large systems

Legacy operation

 GICv4 virtualization

GICv3/GICv4 Webinar
Virtualization in GICv4
 GICv4 adds support for direct injection of virtual interrupts
 Reduces the need to enter the Hypervisor, and so can reduce run-time overhead
 Only supported for LPIs
 Requires an ITS, and inclusion of at least one ITS is mandatory in GICv4

 Hypervisor tells the ITS in advance about mappings between virtual and
physical interrupts
 Mapping includes:
 EventID/Device of physical interrupt
 Virtual INTID
 Which virtual core the virtual interrupt belongs to
 Which physical core the virtual core is expected to be running on

 If the virtual core is running when the interrupt occurs, the hardware
generates a virtual interrupt
 If not, a physical door-bell interrupt can optionally be sent instead

GICv3/GICv4 Webinar
 GICv4 example (1)
 Hypervisor issues ITS commands to map interrupts
 VMAPI and VMAPTI used to map EventID/DeviceID to virtual INTID and virtual core
 Can optionally specify a physical doorbell interrupt
 VMAPP used to map virtual core to a physical core

Redistributor Virtual Virtual

CPU core
Interface
GICR_VPENDBASER
ITS
GICR_VPROPBASER
Physical
CPU Hypervisor
Interface
Translation
Virtual
Tables PE
table
VMAPP, VMAPTI

GICv3/GICv4 Webinar
 GICv4 example (2)
 When interrupt occurs, ITS uses EventID/DeviceID to retrieve translation
 Returns virtual INTID and virtual core
 Physical INTID of doorbell interrupt (if applicable)
 Redistributor where the virtual core is scheduled

Redistributor Virtual Virtual

CPU core
Message from Interface
peripheral GICR_VPENDBASER
ITS
GICR_VPROPBASER
Physical
CPU Hypervisor
Interface
Translation
Virtual
Tables PE
table

GICv3/GICv4 Webinar
 GICv4 example (3)
 Redistributor checks whether the target virtual PE is currently scheduled

 If check passes, virtual interrupt forwarded to CPU interface

 Virtual CPU Interface raises a virtual interrupt (subject to enables/priority checks)

Redistributor Virtual Virtual

CPU PE
Interface Virtual IRQ
GICR_VPENDBASER
ITS
GICR_VPROPBASER
Physical
CPU Hypervisor
Interface
Translation
Virtual
Tables PE
table

GICv3/GICv4 Webinar
 GICv4 example (4)
 If virtual core not currently scheduled, physical doorbell interrupt
forwarded instead
 Physical interrupt handled by Hypervisor running at EL2

Redistributor Virtual Virtual

CPU PE
Interface
GICR_VPENDBASER
ITS
GICR_VPROPBASER
Physical
CPU Hypervisor
Interface Physical IRQ

Translation
Virtual
Tables PE
table

GICv3/GICv4 Webinar
 Any Questions?

GICv3/GICv4 Webinar
 Back-up

GICv3/GICv4 Webinar
CoreLink™GIC-500

Feature Design Time Options

Number of CPU interfaces 1 – 128

(32 clusters, 8 CPUs per cluster)

Number of SPIs 32 – 960

Number of PPIs 16

Programming port AXI4 bus width 32-bit

LPIs supported Yes

up to 56K LPIs (optional)
Support for two security states Yes
(optional)
Legacy operation supported Yes
(optional)
CPU Architecture Support ARMv8

GICv3/GICv4 Webinar
 Audience Q & A
Chris Shore,
Training Manager,
ARM

Martin Weidmann,
Principal Applications Engineer,
ARM
 Thanks for joining us

Event archive available at:

http://ecast.opensystemsmedia.com/

E-mail us at: jgilmore@opensystemsmedia.com