Code No: R1621042 R16 SET - 1

II B. Tech I Semester Regular/Supplementary Examinations, October/November - 2018

SWITCHING THEORY AND LOGIC DESIGN
(Com to ECE, EIE and ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Convert the following numbers with the given radix to decimal. (2M)
i. 61 ii. 1
b) Prove that NAND gates are universal gates. (3M)
c) Define Decoder? List out the applications of it? (3M)
d) Draw the basic architecture of a PAL? (2M)
e) Give the Excitation table for J-K Flip-flop (2M)
f) Compare Melay and Moore models (2M)
PART -B
2. a) Perform the subtraction using 1’s complement and 2’s complement methods. (8M)
(i)11010 – 10011 (ii)11000 – 1011 (iii)111 - 110000
b) A 7 bit Hamming code is received as 1110101.Is there any error? If yes, locate (6M)
the position of the error bit. Parity checks are created by odd parity.

3. a) Reduce the following function using k-map technique (7M)

F(A,B,C,D)=ΠM(1,2,3,5,6,7,8,9,12,13) .
b) Design a combinational circuit that converts four bit binary number into gray (7M)
code

4. a) Perform the realization of full subtractor and full adder using decoders and (6M)
logic gates
b) Realize the function f(A,B,C,D) = ∑ (1,2,5,6,7,8,10,14,15) using (8M)
i) 8:1 MUX ii) 4:1 MUX

5. a) Discuss how PROM, EPROM and EEPROM technologies differ from each (6M)
other.
b) Realize the following four Boolean functions using PAL. (8M)
F1(w,x,y,z) = ∑m(1,2,3,7,9,11) F2(w,x,y,z) = ∑m(0,1,2,3,10,12,14)
F3(w,x,y,z) = ∑m(4,5,6,7,9,15) F4(w,x,y,z)=∑m(1,2,3,10,13,15)

6. a) Convert T flip-flop into D and JK flip-flops (6M)

b) Design a mod-12 Ripple counter using T flip flops and explain its operation. (8M)

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Code No: R1621042 R16 SET - 1

7. a) Draw the diagram of Mealy type FSM for serial adder. (7M)
b) Find the equivalence partition and a corresponding reduced machine in a (7M)
standard form for a given machine.

PS NS , Z
X=0 X=1
A C,1 E,1
B A,0 D,1
C E,0 D,1
D F,1 A,1
E B,1 F,0
F B,1 C,1

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Code No: R1621042 R16 SET - 2

II B. Tech I Semester Regular/Supplementary Examinations, October/November - 2018

SWITCHING THEORY AND LOGIC DESIGN
(Com to ECE, EIE and ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Convert the following numbers with the given radix to decimal. (2M)
i. 61 ii. 2
b) Prove that NOR gates are universal gates. (3M)
c) Define Multiplexer? (2M)
d) Draw the basic architecture of a PLA? (2M)
e) Give the Excitation table for R-S Flip-flop (2M)
f) Distinguish between synchronous and asynchronous machines. (3M)
PART -B
2. a) Determine the canonical sum-of-products representation of the following (7M)
functions
i) f(A,B,C) =C+ (̅+B)(A+)

ii) f(A,B,C) =A +( ̅  + ̅C)
b) Given the 8bit data word 01001001, generate the 12 bit composite word for the (7M)
hamming code that corrects and detects single error

3. a) Reduce using mapping the following expression and implement the real (7M)
minimal expression using logic gates.
f(A,B,C,D)= ∏M (1,3, 5, 9, 11, 14)
b) Using the Quine–McCluskey tabular method, find the minimum sum of (7M)
products for
F(A,B,C,D,E) =∑m(1,5,6,7,9,13,14,15,17,18,19,21,22,23,25,29,30)

4. a) Design a excess-3 adder using 4-bit parallel binary adder and logic gates. (7M)
b) Construct a 4x16 decoder using logic gates and explain its operation with the (7M)
help of truth table.

5. a) Design a BCD to Excess-3 code converter using a PROM (7M)

b) Give the comparison between PROM,PLA and PAL (7M)

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Code No: R1621042 R16 SET - 2

6. a) Design a SR flip flop using NAND gates. Explain the operation of the SR flip (7M)
flop with the help of characteristic table and characteristic equation.
b) Explain the operation of 4-bit ring counter with circuit diagram and timing (7M)
diagrams.

7. a) Write the differences between Mealy and Moore type machines (7M)
b) Convert the following Moore machine into a corresponding Mealy Machine (7M)
PS NS Z
X=0 X=1
A D B 1
B A E 0
C A E 1
D C A 0
E F D 0
F F D 1

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Code No: R1621042 R16 SET - 3

II B. Tech I Semester Regular/Supplementary Examinations, October/November - 2018

SWITCHING THEORY AND LOGIC DESIGN
(Com to ECE, EIE and ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Convert the following numbers with the given radix to decimal. (2M)
i. 52 ii. 2
b) Reduce the following Boolean expression using Boolean theorems. (2M)
ab+b+c+....
c) Define priority encoder? (2M)
d) Realize the two input X-NOR gate using minimum number of NOR gates. (3M)
e) Draw the state diagram for S-R & T Flip-Flop . (3M)
f) What is the principal advantage of a PLD? (2M)
PART -B
2. a) Determine the canonical product-of-sums representation of the following (7M)
functions
i) f(A,B,C) =C (̅+B)(A+)

ii) f(A,B,C) =A( ̅  + ̅C)
b) Perform the subtraction using 1’s complement and 2’s complement methods. (7M)
(i)11010 – 10111 (ii)11000 – 1010 (iii)1110 - 110000

3. a) Reduce using mapping the following expression and implement the real (7M)
minimal expression using logic gates.
f(A,B,C,D)= ∑m (0,2, 4, 6,7,9, 11, 14)
b) Using the Quine–McCluskey tabular method, find the minimum sum of (7M)
products for
F(A,B,C,D) =∑m(1,5,6,12,13,14)+∑d(2,4)

4. a) Design a BCD adder using 4-bit parallel binary adder and logic gates. (7M)
b) Realize the function f(A,B,C,D) = ∑ (1,3,4,6,7,8,10,13,15) using (7M)
i) 16:1 MUX ii) 8:1 MUX

5. a) Implement the following Boolean functions using PLA. (7M)

A(x,y,z)= ∑m(0,1,2,4,6)
B(x,y,z)= ∑m(0,2,6,7)
C(x,y,z)=∑m(3,6)
b) Design a Excess-3 to BCD code converter using a PROM (7M)

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Code No: R1621042 R16 SET - 3

6. a) Design a SR flip flop using AND gates and NOR gates. Explain the operation (7M)
of the SR flip flop with the help of characteristic table and characteristic
equation
b) Explain the operation of 4-stage twisted ring counter with circuit diagram and (7M)
timing diagram.

7. a) Draw the diagram of Mealy type FSM for serial adder (7M)
b) Convert the following Mealy machine into a corresponding Moore Machine (7M)
PS NS,Z
X=0 X=1
A C,0 B,0
B A,1 D,0
C B,1 A,1
D D,1 C,0

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Code No: R1621042 R16 SET - 4

II B. Tech I Semester Regular/Supplementary Examinations, October/November - 2018

SWITCHING THEORY AND LOGIC DESIGN
(Com to ECE, EIE and ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Convert the following numbers with the given radix to decimal. (2M)
i. 73 ii. 4
b) Reduce the following Boolean expression using Boolean theorems. (3M)
xy+ ̅+wx̅
c) Realize Full subtractour using Half subtractors and logic gate (3M)
d) Realize the two input X-OR gate using minimum number of NAND gates. (2M)
e) Write the characteristic equations for S-R Flip-flop & T Flip-Flop. (2M)
f) What is meant by self correcting counters?. (2M)
PART -B
2. a) How are negative numbers represented? Represent signed numbers from +7 to (7M)
-8 using different ways of representation.
b) What is a Gray code? Obtain a 4-bit and 3-bit gray code from a 2-bit gray code (7M)
by reflection. Explain its application in data converters.

3. a) Design a combinational circuit that converts four bit gray number into binary (7M)
code
b) Simplify the following using tabulation method (7M)
F(A,B,C,D,E) = ∑m(0,4,12,16,19,24,27,28,29,31).

4. a) Construct the 4 bit parallel adder with look ahead carry generation. (7M)
b) Draw the logic diagram of a 3 to 8 line decoder with enable input and explain (7M)
its operation with the help of truth table.

5. a) Design a BCD to Excess-3 code converter using a PROM (7M)

b) What is a PLD? Compare the three combinational PLDs? (7M)

6. a) Design a JK flip flop using AND gates and NOR gates. Explain the operation (7M)
of the JK flip flop with the help of characteristic table and characteristic
equation
b) What are the different types of registers? Explain the Parallel Input Serial (7M)
Output shift register

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Code No: R1621042 R16 SET - 4

7. a) What are the Moore and Mealy machines? Compare them. (7M)
b) Reduce the number of states in the following state table and tabulate the (7M)
reduced state table.
PS NS,Z
X=0 X=1
A A,0 E,1
B E,1 A,0
C F,1 B,0
D B,0 F,1
E C,1 C,0
F G,0 C,1
G H,0 D,1
H D,1 H,0

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Code No: R1621042 R16 SET - 1

II B. Tech I Semester Regular Examinations, October/November - 2017

SWITCHING THEORY AND LOGIC DESIGN
(Com to ECE, EIE and ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Convert the binary number 11011101 to gray code. (2M)
b) Find the dual of the function: A'B(C+D)+B'C'D+AB'C. (2M)
c) What is a de-multiplexer? Write its applications. (3M)
d) Write the merits and demerits of PROM. (2M)
e) What are the differences between Johnson and ripple counter. (2M)
f) What is a state diagram? Describe with an example. (3M)
PART –B
2. a) Express the following numbers in decimal: (7M)
(i) (26.24)8
(ii) (16.5)16
b) Generate the Hamming code word for the message 1110010111. (7M)

3. a) Implement the following Boolean function with only two input NOR gates: (7M)
F=(AB'+CD')E+BC(A+B)
b) Simplify the following Boolean function with the don’t conditions d using K- (7M)
map method:
F(A, B, C, D)=Σ(4, 5, 7, 12, 13, 14); d(A, B, C, D)=Σ(1, 9, 11, 15)

4. a) Design a 4-bit binary comparator with basic gates. (7M)

b) Implement the following Boolean functions with a decoder. (7M)
(i) F1=Σ(3, 6, 7, 10, 13, 15)
(ii) F2=Σ(1, 9, 12, 15)
(iii) F3=Σ(2, 6, 8, 10, 14, 15)

5. a) Implement the following Boolean functions using PLA. (7M)

(i) F1= Σ(0, 1, 2, 4)
(ii) F2= Σ(0, 5, 6, 7)
b) Design a full adder circuit with a PAL. (7M)

6. a) Draw the circuit of a JK master slave flip-flop with active high clear and active (7M)
low preset and explain its operation.
b) Design a Mod-10 counter using RS flip-flops (7M)
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Code No: R1621042 R16 SET - 1

7. a) What are the capabilities and limitations of finite state machines? Explain. (7M)
b) Reduce the number of states in the following state table and tabulate the (7M)
reduced state table.

NS, O/P
PS
X=0 X=1
a f, 0 b, 0
b d, 0 c, 0
c f, 0 e, 0
d g, 1 a, 0
e d, 0 c, 0
f f, 1 b, 1
g g, 0 h, 1
h g, 1 a, 0

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Code No: R1621042 R16 SET - 2

II B. Tech I Semester Regular Examinations, October/November - 2017

SWITCHING THEORY AND LOGIC DESIGN
(Com to ECE, EIE and ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) Find the 10’s complement of 2476. (2M)
b) Define the essential prime implicants in a K-map method. (3M)
c) What is a multiplexer? Write its applications. (2M)
d) Compare PROM, PLA and PAL. (3M)
e) Write the differences between the synchronous and asynchronous sequential (2M)
circuits.
f) Write the features of Moore machine. (2M)
PART –B
2. a) Convert the following number to Hexadecimal: (7M)
(i) (735.5)8
(ii) (1011011)2
b) Perform the following subtraction in binary using 1's and 2's complement (7M)
method: (677)10 – (899)10

3. a) Find the complement and dual of the given function: (7M)

xy+x(wz+wz‫)׳‬
b) Simplify the following Boolean function using tabular method: (7M)
F(A, B, C, D)=Σ(2, 4, 6, 10, 12); d(A, B, C, D)=Σ(0, 8, 9, 13)

4. a) Realize 4:16 decoder using 2:4 decoders. (7M)

b) Implement the following Boolean function with 4X1 multiplexer and external (7M)
gates. Connect inputs B and C to the selection lines.
F(A, B, C, D)=Σ(1, 2, 4, 7, 8, 9, 10, 11, 13, 15)

5. a) Draw the internal structure of 8X1 PROM and explain its operation. (7M)
b) Give the realization of the following Boolean functions using PLA with 5 (7M)
inputs, 4 outputs and 8 and gates.
F1= Σ(0, 1, 2, 3, 11, 11, 13, 14, 15, 16, 17, 18, 19, 27, 28, 29, 30, 31)
F2= Σ (4, 5, 6, 7, 8, 9, 10, 11, 20, 21, 22, 23, 30)

6. a) Convert the JK flip into T flip-flop. (5M)

b) Design a Mod-12 counter using D flip-flops. (9M)
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Code No: R1621042 R16 SET - 2

7. a) Design a synchronous sequential circuit which goes through the following (7M)
states: 1, 3, 5, 3, 6, 1, 3, 5.
b) Convert the following Mealy machine into a corresponding Moore machine. (7M)

NS, Z
PS
X=0 X=1
A C, 0 B, 0
B A, 1 D, 0
C B, 1 A, 1
D D, 1 C, 0

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Code No: R1621042 R16 SET - 3

II B. Tech I Semester Regular Examinations, October/November - 2017

SWITCHING THEORY AND LOGIC DESIGN
(Com to ECE, EIE and ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) What are the universal gates? Why they are called as universal gates? (3M)
b) Find the complement of the function: A'B(C+D)+B'C'D+AB'C. (3M)
c) Write the truth table of a full subtractor. (2M)
d) Write the merits and demerits of PLA. (2M)
e) Write the differences between the Combinational and sequential circuits. (2M)
f) What is a state table? Describe with an example. (2M)
PART –B
2. a) Convert the following numbers to Binary: (7M)
(i) (27.315)10
(ii) (68BE)16
b) Reduce the following Boolean function to four literals and draw the logic (7M)
diagram: (A'+C)(A'+C')(A+B+C'D)

3. a) Implement the following Boolean function with only two input NAND gates: (7M)
F=(AB'+D')E+C(A'+B')
b) Simplify the following Boolean function with the don’t conditions d using K- (7M)
map method:
F(A, B, C, D)=Σ(1,3,8,10,15); d(A, B, C, D)=Σ(0, 2, 9)

4. a) Design an excess-3 adder circuit and explain its operation. (7M)

b) Implement the following Boolean function with 8X1 multiplexer and external (7M)
gates:
F(A, B, C, D)=Σ(1, 3, 4, 11, 12, 13, 14, 15)

5. a) Design a 3-bit binary to Excess-3 code converter using a PROM. (7M)

b) Implement the following Boolean functions using PLA. (7M)
(i)F1= Σ(0, 1, 2, 4)
(ii)F2= Σ(0, 5, 6, 7)

6. a) What is the drawback of JK flip-flop? How is it eliminated in Master Slave (7M)

flip-flop? Explain.
b) Design a decade counter using T flip-flops. (7M)

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7. a) Obtain the state table and state diagram for a sequence detector to recognize (7M)
the occurrence of sequence bits 110 & 001.
b) Find the equivalence partition and reduced table for the given state machine. (7M)

NS, O/P
PS
X= 0 X=1
A B, 0 E, 0
B E, 0 D, 0
C D, 1 A, 0
D B, 1 E, 0
E C, 0 D, 0

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Code No: R1621042 R16 SET - 4
II B. Tech I Semester Regular Examinations, October/November - 2017
SWITCHING THEORY AND LOGIC DESIGN
(Com to ECE, EIE and ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) Find the 2’c complement of the decimal number 97. (2M)
b) What are the prime implicants in a K-map method? (2M)
c) What is a decoder? Write its applications. (2M)
d) Write the merits and demerits of PAL. (2M)
e) What are registers? Write their applications. (3M)
f) Write the features of Mealy machine. (3M)
PART –B
2. a) Convert the following numbers to Octal: (7M)
(i) (1010.1010)2
(ii) (FAFA)16
b) Reduce the following Boolean function to three literals and draw the logic (7M)
diagram: (x'y'+z)'+z+xy+wz

3. a) Find the dual and complement of the following function: (7M)

A'BD'+B'(C'+D')+A'C'
b) Simplify the following Boolean function using tabular method: (7M)
F(A, B, C, D)=Σ(0, 6, 8, 13, 14); d(A, B, C, D)=Σ(2, 4,10)

4. a) Design a BCD adder circuit and explain its operation. (7M)

b) Implement the following Boolean function with 4X1 multiplexer and external (7M)
gates:
F(A, B, C, D)=Σ(1, 3, 4, 11, 12, 13, 14, 15)

5. a) Realize the following Boolean functions using a PROM (7M)

(i) F1= Σ(0, 4, 7)
(ii) F2= Σ(1, 3, 6)
(iii) F3= Σ(1, 3, 4, 6)
b) Design a BCD to Excess-3 code converter using a PAL. (7M)

6. a) Convert JK flip-flop into D flip-flop. (7M)

b) Design a modulo-10 ripple counter using RS flip-flops. (7M)

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7. a) Design a sequence detector that detects the overlapping sequence of 011010 (5M)
using T flip-flops.
b) Draw the diagram of Mealy type state machine for serial adder and explain its (9M)
operation.

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Code No: R1621042 R16 SET - 1

II B. Tech I Semester Model Question Paper Oct/Nov - 2017

SWITCHING THEORY AND LOGIC DESIGN
(Com. to ECE, ECC, EIE.)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A [7 x 2 =14]
1. a) Write the differences between combinational and sequential circuits.
b) State De Morgans’s theorems
c) List the applications of Multiplexers.
d) Write the demerits of PROM
e) Write the differences between combinational and sequential circuits.
f) Sketch Mealy circuit and explain.
g) What is race around condition? How can minimized in J-K flip-flop
PART –B

2. a) Given the 8bit data word 01011011, generate the 12 bit composite word for (10M)
the hamming code that corrects and detects single errors
b) Perform the following addition using excess-3 code i)386+756 ii)1010 + 444 (4M)

3. Simplify the following using tabulation method (14M)

y(w,x,y,z)=∑m(1,2,3,5,9,12,14,15)+d(4,8,11)

4. a) Design a excess-3 adder using 4-bit parallel binary adder and logic gates. (10M)
b) What are the applications of full adders?
(4M)

5. a) Design and implement Full adder with PLA (7M)

b) Write the comparisons between PAL, PLA (7M)

6. a) Construct a JK flip flop using a D flip flop, a 2x1 multiplexer and an inverter. (7M)
b) Draw the schematic circuit of RS master slave flip flop. Give its truth table and (7M)
justify the entries in the truth table.

7. a) Draw the diagram of Mealy type FSM for serial adder. (7M)
b) Draw the circuit for Moore type FSM. (7M)
*****

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Code No: R1621042 R16 SET - 2

II B. Tech I Semester Model Question Paper Oct/Nov - 2017

SWITCHING THEORY AND LOGIC DESIGN
(Com. to ECE, ECC, EIE.)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A [7 x 2 =14]
1. a) Perform (24)10 – (56)10 in BCD using 9’s complement
b) State De Morgans’s theorems.
c) Design 2x4 decoder using NAND gates.
d) Give the comparison between PROM, PLA and PAL.
e) What are applications of Flip-Flop?
f) Write capabilities and limitations of Finite- State machine.
g) Implement two input EX-OR gate from 2 to 1 multiplexer
PART –B
2. a) Convert the given expression in standard SOP form (7M)
f(A,B,C)=AC+BA+BC
b) Convert the given expression in standard POS form y=A.(A+B+C)
(7M)

3. a) Reduce the following function using k-map technique (7M)

F(A,B,C,D)=π(0,2,3,8,9,12,13,15)
b) Minimize the expression using k-map y=(A+B+C’ ) (A+ B+ C) (A’ + B’ + C’ )
(A’ + B +C) (A+B+C) (7M)

4. a) Design BCD to gray code converter and realize using logic gates. (7M)

b) Design a 1:8 demultiplexer using two 1:4 demultiplexer.

(7M)

5. a) Implement the following Boolean functions using PLA. A(x,y,z)=∑(1,2,4,6) (7M)

B(x,y,z)= ∑(0,1,6,7) C(x,y,z)= ∑(2,6)
b) Design a combinational circuit using PROM that accepts 3-bit binary number and (7M)
generates its equivalent excess-3 code.

6. a) Draw the logic diagram of a SR latch using NOR gates. Explain its Operation using (7M)
excitation table.
b) Convert D flip-flop into T and JK flip-flops. (7M)

7. a) The output Z of a fundamental mode, two input sequential circuit is to change from 0 to 1 only
when x2 changes from 0 to 1 while x1=1. The output changes from 1 to 0 only when x1 changes
from 1 to 0 while x2=1. Find a minimum row reduced flow table (7M)
b) Draw a state diagrams of a sequence detector which can detect 101 (7M)

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Code No: R1621042 R16 SET - 3

II B. Tech I Semester Model Question Paper Oct/Nov - 2017

SWITCHING THEORY AND LOGIC DESIGN
(Com. to ECE, ECC, EIE.)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A [7 x 2 =14]
1. a) Convert (97.75)10 to base 2.
b) Prove that OR-AND network is equivalent to NOR-NOR network.
c) Realize full adder using two half adders and logic gates.
d) Design a 4x2 PROM with AND-OR gates.
e) Distinguish between Moore and Mealy Machines.
f) Write and prove de-Morgan laws
g) Draw the diagram of subtractor using truth tables.
PART -B
2. Find the complement of the following Boolean functions and reduce them to minimum (7M)
number of literals.
a) (b c’ +a’ d) (ab’ +cd’ ) (7M)
b) (b’ d+ a’ b c’ +a c d+ a’ b c) (8M+8M)
3. Simplify the following Boolean expressions using K-map and implement it by using (7M)
NOR gates. a) F(A,B,C,D)=AB’C’ +AC+A’CD’
b)F(W,X,Y,Z)=w’ x’y’z’ + wxy’z’ + w’x’yz + wxyz

4. a) Design and implement a two bit comparator using logic gates. (7M)

b) Implement full adder using decoder and OR gates. (7M)

5. a) Design a BCD to excess-3 code converter and implement using suitable PLA. (7M)

b) Implement the following functions using a PROM i) F(w,x,y,z)=∑(1,9,12,15) (7M)

ii) G(w,x,y,z)= ∑(0,1,2,3,4,5,7,8,10,11,12,13,14,15)

6. a) Draw the logic diagram of a JK flip- flop and using excitation table explain its operation. (7M)
b) What do you mean by triggering? Explain the various triggering modes with examples. (7M)

7. a) Explain about sequential circuits, state table and state diagram. (7M)

b) Explain the procedure of Meelay to Moore conversion. (7M)

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Code No: R1621042 R16 SET - 4

II B. Tech I Semester Model Question Paper Oct/Nov - 2017

SWITCHING THEORY AND LOGIC DESIGN
(Com. to ECE, ECC, EIE.)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A [7 x 2 =14]
1. a) Convert(2468)10 to ( )16
b) What are the advantages of tabulation method over K-map?
c) Why a multiplexer is called a data selector? Draw the 2x1 MUX.
d) Write a brief note on PLDs
e) Give the comparison between synchronous sequential and asynchronous sequential circuits
f) Draw and explain Moore circuit.
g) Draw the basic architecture of a PAL?
PART -B
2. a) What is the difference between canonical form and standard form? Explain (7M)

b) How are negative numbers represented? Represent signed numbers from +7 to -8 (7M)
using different ways of representation.

3. a) Simplify the following using K- map and implement the same using NAND gates. (7M)
Y (A, B, C) =∑(0,2,4,5,6,7)
b) R Represent and draw the following Boolean function using minimum number of (7M)
basic gates. i) (AB + AB’) (AB)’ ii) [(ABD(C + D + E)) + (A +DBC)’] (ABC +
(CAD)’)

4. a) Define decoder. Construct 3x8 decoder using logic gates and truth table. (7M)
b) Define an encoder. Design octal to binary encoder.
(7M)

5. a) Design and implement Full adder with PLA (7M)

b) Design a combinational circuit using PROM. The circuit accepts a 3 bit number and
generates an O/p binary number equal to square of input number.
(7M)

6. a) Convert JK flip-flop to T flip-flop (7M)

b) Convert RS flip-flop to D flip-flop
(7M)

7. A clocked sequential circuit is provided with a single input x and single output z, (7M)
whenever the input produces a string pulsed 111 or 000 and at the end of the sequence
it produces an output z=1 and overlapping is also allowed. (7M)
a) Obtain state diagram and state table.
b) Find equivalence classes using partition method and design the circuit using D flip-
flop.

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Code No: R1621042 R16 SET - 1

II B. Tech I Semester Supplementary Examinations, May - 2018

SWITCHING THEORY AND LOGIC DESIGN
(Com to ECE, EIE and ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) Subtract 27810 from 49510 using the excess-3 subtractor. (3M)

b) Obtain complement and dual for the given expression (AB+BC+AC) (EF) (3M)

c) Design full adder using two half adders (2M)

d) Explain basic structure of PLA (2M)
e) Convert JK Flip Flop to T Flip Flop (2M)
f) Brief about Finite State Machine (2M)
PART -B
2. a) The message below has been coded in the 7 bit Hamming code and transmitted (7M)
through noisy channel. Decode the message assuming that at most a single
error has occurred in each code word 1001001, 0111001, 1110110, and
0011011.
b) Generate Hamming code for a 4-bit Excess-3 message to detect and correct (7M)
single bit errors.

3. a) Implement the following function using only NOR gates F=a. (b+ c.d) + (b. c). (7M)
b) Implement the following function using only NAND gates G=(a + b).(c. d + e ) (7M)

4. a) Design a full-adder with two half-adders and basic gates. (7M)

b) Convert Excess-3 code to BCD using Full adder circuits. (7M)

5. a) Implement f (A,B,C,D) = ∑(0,1,3,5,6,8,9,11,12,13) using PAL and explain its (7M)

procedure .
b) Write the merits and demerits of PROM. (7M)

6. a) Draw the circuit diagram of J-K flip flop with NAND gates with positive edge (7M)
triggering and explain its operation with the help of truth table. How race
around condition is eliminated.
b) Realize D-latch using R-S latch. How it is different from D-flip flop. Draw the (7M)
circuit using NAND gates and explain.
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Code No: R1621042 R16 SET - 1

7. a) Convert the following Mealy machine into a corresponding Moore machine: (7M)

b) Design the circuit for the above table using RS flipflops. (7M)

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Code No: R1621042 R16 SET - 1

II B. Tech I Semester Supplementary Examinations, May - 2019

SWITCHING THEORY AND LOGIC DESIGN
(Com to ECE, EIE and ECC)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. AnswerALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) Convert the given gray code number to binary: 1001001011. (2M)
b) Prove that Y=AB + BC + AC is a self-dual function. (3M)
c) Draw four bit adder circuit using full adders (3M)
d) Explain difference in the basic structure of PLA, PAL and PROM (2M)
e) Convert D Flip Flop to T Flip Flop (2M)
f) Explain about Mealy state machine (2M)
PART -B
2. a) Realize a 2 input EX-OR gate using minimum number of 2 input NAND gates. (7M)
b) Encode the decimal numbers using 6, 3, 1,-1 weighted code. Is it a self- (7M)
complementing code?

3. a) Simplify the Boolean function F using the don’t care conditions d, in (i) sum of (7M)
products and (ii) product of sums.
F= A’B’D’ + A’CD+A’BC
d=A’BC’D+ACD+AB’D’
b) F (A, B, C, D) = π max [5, 8, 14] + dπ [7, 11, 12, 13, 15]. Obtain minimal sop (7M)
function.

4. a) Define Multiplexer and explain the procedure to implement 32X1 MUX by (7M)
Using 4X1 Multiplexers.
b) Design 4-bit digital comparator and explain with neat sketch. (7M)

5. a) Write a brief note on Architecture of PLDs (7M)

b) Write a brief note on Capabilities and the limitations of threshold gates. (7M)

6. a) Draw the circuit diagram of MOD-10 Counter and explain the operation of it. (7M)
b) What is race around condition and how to avoid it along with circuit diagram. (7M)

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Code No: R1621042 R16 SET - 1

7. a) Distinguish between Mealy and Moore machines (7M)

b) Convert the following Mealy machine into a corresponding Moore machine: (7M)

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