3090 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO.
11, NOVEMBER 2013
4-Phase Interleaved Boost Converter With IC
Controller for Distributed Photovoltaic Systems
Francesco Pulvirenti, Amedeo La Scala, Domenico Ragonese, Keith D’Souza, Giuseppe M. Tina, Member, IEEE,
and Salvatore Pennisi, Senior Member, IEEE
Abstract—We present a DC-DC converter for photovoltaic (PV)
applications that is suitable for distributed power conversion ob-
tained by transferring part of the electronics from the inverter
to the module. The proposed circuit implements a high-efficiency
four-phase interleaved boost converter employing relatively low-
valued inductive and capacitive components. Its compact realiza-
tion is made possible thanks to the innovative design of a dedicated
integrated circuit (IC) embedding the power MOS switches and
performing the converter control section as well as the Maximum
Power Point Tracking (MPPT) algorithm. The solution is designed
for a maximum delivered power of 300 W and to work with an
MPPT voltage between 9 V and 36 V, with maximum allowed panel
current of 9 A. The area of the complete printed-circuit board is
4 cm 7 cm. Experimental measurements show that the average
power conversion efficiency is between 93% and 99% and that the
MPPT efficiency is always greater than 99.7%.
Index Terms—Boost converter, interleaved converter, MPPT,
photovoltaic, power conversion efficiency, switching DC-DC
converter.
I. INTRODUCTION
T HE use of active electronics inside the PV modules (also
referred to as PV panels) has been initially excluded
to avoid expected reduction of reliability and cost increase.
Discrete diodes utilized as blocking and bypass elements have
hence been the only passive electronic devices exploited [1].
Historically, the use of active electronics in PV systems has
been limited exclusively to the inverter section, a DC-AC con-
verter that transfers the energy extracted from the PV modules
to the grid at a given amplitude and frequency. A good review
of inverter topologies is found in [2]. The inverter performs also
the maximum power point tracking (MPPT), which is an algo-
rithm that adjusts the output impedance of the PV system to
match that of the load thus achieving maximum power transfer
[3]–[7]. However, MPPT techniques treat the entire array as a
single entity (field MPPT), averaging all of the PV modules to-
gether, with an inclination towards the weakest link. Indeed,
since PV modules in a series string must all conduct the same
Manuscript received February 28, 2012; revised January 14, 2013; accepted
March 02, 2013. Date of publication August 23, 2013; date of current version
October 24, 2013. This work is supported in part by the UE (ENIAC Joint Un-
dertaking) in the “END” project (ENIAC—120214). This paper was recom-
mended by Associate Editor J. Kim.
F. Pulvirenti, A. La Scala, D. Ragonese, and K. D’Souza are with ST-
Microelectronics, Catania 95125, Italy (e-mail: francesco.pulvirenti@st.com;
amedeo.la-scala@st.com; domenico.ragonese@st.com; keith.dsouza@st.com).
G. M. Tina and S. Pennisi are with the Dipartimento di Ingegneria Elettrica
Elettronica e Informatica (DIEEI), University of Catania, Catania 95125 Italy
(e-mail: giuseppe.tina@dieei.unict.it; salvatore.pennisi@dieei.unict.it).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2013.2256235
1549-8328 © 2013 IEEE
current, the least efficient module sets this string current. This
means that even though some panels are capable of supply 100%
power, the system will only harvest a fraction of that power due
to the averaging effect of the algorithm. Unfortunately, MPP
currents associated to a module may be permanently unbalanced
for different reasons, such as partial shadowing, dust collection,
manufacturer mismatches and ageing [8]. Among these, partial
shadowing is a particularly serious concern, especially when PV
strings/modules/cells are connected in series.
To reduce the effects of these problems, distributed MPPT
techniques have been recently studied [9]–[12]. In these ap-
proaches a DC-DC converter performs independently the MPPT
for each string and even for each PV module. To further extend
this trend, a part of the electronics has been moved from the
inverter to the module. With the generic name of power opti-
mizers we refer to one or several miniaturized DC-DC power
converters that can be integrated within a module [13]. Since
MPPT is calculated locally for each string of cells within the
module, the resulting efficiency of the distributed architecture
results to be higher than for the conventional topology where
the MPPT is calculated in the centralised inverter, provided that
the conversion efficiency of each power optimizer is enough.
In this paper, we propose a DC-DC boost converter that
differs from the previous implementations mainly for the fact
that the control unit is fully integrated as a monolithic circuit,
thereby minimizing area occupation and costs. Improved relia-
bility and reduced failure rate are also expected.
As we will see, the realization of a fully integrated control
section is not a trivial task, as many issues have to be solved.
However an IC solution is essential to implement a high-ef-
ficiency four-stage interleaved boost converter with matched
stage behaviors, low-value passive components (inductors and
capacitors) and reduced parasitic effects. Based on this con-
verter, an experimental printed circuit board (PCB) occupying
an area of 4 cm 7 cm has been realized and successfully
validated.
The outline of the paper is the following. After a brief in-
troduction on distributed PV systems in Section II, the pro-
posed solution and its implementation details are described in
Sections III and IV, respectively. Experimental results are pre-
sented in Section V. Finally, authors conclusions and future de-
velopments are summarized in Section VI.
II. DISTRIBUTED POWER CONVERSION
A. Background
Minimizing the number of modules required to produce the
target power is the most direct way to reduce the cost of a PV
system and to reduce in turn the cost of the energy harvested.
PULVIRENTI et al.: 4-PHASE INTERLEAVED BOOST CONVERTER
Fig. 1. PV field with multi-string inverter.
This can be achieved only by increasing the efficiency of each
module, i.e., maximizing the power extracted under a given ir-
radiation condition. To increase the efficiency of the entire field
in the case of more strings in parallel, multi-string inverters can
be used which allow to compensate for the strings non-unifor-
mity. A concise analysis of the development and trends of the
worldwide PV systems market by forecasting also the use of
multi-string inverters with optimized efficiency and cost-effec-
tive solutions was described in [14]. A PV system with a multi-
string inverter is shown in Fig. 1. In this architecture each string
is connected to a dedicated DC-DC converter which forms the
first stage of the multi-string inverter. The DC-DC converters
drive then in parallel a common DC-AC converter (second stage
of the multi-string inverter). The input voltage of each DC/DC
converter is therefore the voltage across each string and is reg-
ulated to work at the maximum power transfer point for each
string. Multistring inverters are now available commercially and
are becoming increasingly popular [15], [16], but it should be
noted that the power conversion process is still centralized.
The above approach was further expanded in [4], [10], [12],
where the idea of one DC-DC converter for each module was
proposed and experimentally demonstrated. Related stability
issues were also addressed in [9], where the acronym DMPT
(Distributed Maximum Power Point Tracking) was finally
introduced.
B. MPPT DC-DC Converters Integrated in the PV Module
To implement this approach a compact converter with MPPT
capability and that can be integrated in the module or housed
in the junction box is required. The design of this converter
is challenging since it must occupy a small area and must ex-
hibit both high power efficiency and reduced costs, but the ex-
pected advantages, besides the conversion efficiency increase,
are several:
1) The design of the inverter is heavily simplified, as the first
DC-DC stage with voltage boost capability is no longer
required. Ultimately, the centralised part of the power
3091
Fig. 2. Possible configurations of modules (or substrings inside the module)
using dedicated power converters: (a) series connection, (b) parallel connection,
and (c) series/parallel connection.
converter can be limited to a simplified DC-AC converter
(second stage of a traditional inverter).
2) The problem of multiple maxima in the PV characteristic
is eliminated, thus considerably simplifying the required
MPPT control technique and avoiding in turn the use of
DSP units or microcontrollers and other auxiliary circuitry
(signal interface I/O, programming interface, etc.) [17],
[18].
3) The circuit may include/replace the bypass diode, that is
no longer required.
4) The availability of such a component opens new scenarios
in the module arrangement (and even cell strings consti-
tuting the module, provided that the area of the circuit is
small). Indeed, it has been limited so far to the series con-
nection only. This unique connection type, however, is not
efficient in cases of different cell orientation and, in brief,
in severe mismatching conditions.
Fig. 2 shows the three possible alternative configurations that
can be realized with the aid of dedicated DC-DC converters,
assuming that the terminals of each sub-string inside the module
are available:
a) series connection: provides a higher output voltage than
that achievable with a conventional module (power losses
due to temperature mismatches are minimized);
b) parallel connection: maximizes the current capability of
the module (power losses due to irradiance mismatches
and rapidly fluctuating shadow conditions are minimized)
[19];
c) series/parallel connection: allows a trade-off between the
two previous cases to be achieved.
Currently, five different module-integrated DC/DC con-
verters have been commercialized (vBOOST from sIQ Energy,
3092 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 11, NOVEMBER 2013

Fig. 3. Simplified diagram of the implemented boost converter and control logic blocks. Thge blocks inside the dashed box are implemented in a single chip.
The actual converter is a four-stage 90 -interleaved version of the single-stage one illustrated here.

SMI from National Semiconductors, MM-ES/P from Tigo, SE
PowerBox from Solar Edge and SunMizer from Xandex). An
excellent comparison of the advantages and trade-offs of each
converter is found in [13]. All these solutions use buck, boost
or even buck-boost and flyback DC-DC converters with an
MPPT realized from discrete electronic components.
As already stated, we propose in this paper the design of a
DC-DC boost converter that differs from the previous imple-
mentations mainly for the fact that the control unit is fully inte-
grated as a monolithic circuit, thereby minimizing area occupa-
tion and costs, and due to the IC matching properties, enabling
a 4-phase interleaved solution to be implemented
C. Microinverters
To conclude this review we describe also the architecture
based on microinverters [20]–[25]. As said, in the conventional
string or central inverter approach a single high-power inverter
is connected to multiple series-connected PV modules from one
side and to the grid on the other side. This architecture suffers
from the same problems described in the previous sections for
the centralized architectures.
A microinverter converts the DC current from a single PV
module to an AC current suitable to feed the grid. Again, the
main advantages of microinverters are related to the reduction
of the module mismatches, as each micro-inverter extracts max-
imum power by performing MPPT for its connected panel. Be-
sides, microinverters power is typically rated around 200 W.
Many inverter design issues are thus solved, as there is no need
for a large transformer or large electrolytic capacitors. Cooling
problems are also reduced so that no fans are needed. System
modularity and flexibility is finally enhanced and plug-and-play
operation enabled. After a period of latency mainly due to cost
issues, researchers and the market recently demonstrated new
interest in microinverters [23]. However, issues still remain in
terms of cost, reliability and stability for the grid connection
[25].
III. THE PROPOSED SOLUTION
Fig. 3 shows the simplified block diagram of the proposed
module-integrated DC-DC converter for distributed power
conversion.
PULVIRENTI et al.: 4-PHASE INTERLEAVED BOOST CONVERTER
Fig. 4. The zero-crossing block prevents reverse current flow through
The blocks inside the dashed box are all integrated in the
same IC. Elements outside the box are discrete components.
The IC embeds a DC-DC switching converter including power
MOS transistors and gate drivers (inductors and capacitors are
external) and two digital control sections implementing the
MPPT algorithm and performing Fault Diagnosis. Auxiliary
blocks include an oscillator, three analog-to-digital converters
(ADCs), a differential amplifier, comparators and voltage
references. These main blocks are described in the following.
A. DC-DC Converter
Switching DC-DC converters are commonly used in PV
applications because they allow easy modification of the
impedance seen from the source, by changing the duty cycle
of the PWM signal which drives the active switch [26]. Com-
pared to the other alternatives, the boost topology has been
here selected because of its design simplicity, high conversion
efficiency, reduced voltage stress on devices and high yield
[27]. Besides, a boost converter allows the connection of the
outputs of several converters in parallel without phase margin
degradation [8].
The schematic in Fig. 3 shows a single-phase boost converter
made up of inductor , which stores and releases energy, and
the input and output capacitors, and , used for filtering
purposes. Synchronous rectification (through the power switch
, and the rectifying switch, ) is exploited in order
to be compatible with integration and to reduce voltage (and
power) losses. and are controlled by the digital sec-
tion (MPPT) through two gate drivers. is an external
bootstrapping capacitor whose function is to supply the gate
driver of . Diode D charges to (obtained from
the PV input voltage through pre-regulation). As a result, the
whole system is powered by the PV sources and no additional
supply is required.
Not shown in Fig. 3 an additional zero crossing block that
turns off transistor to prevent reverse current flow from the
output. Its simplified diagram is depicted in Fig. 4.
The step-up conversion makes the boost converter suitable
for a wide range of input voltage values, indeed the output to
input voltage ratio is in the Continuous Inductor Mode (i.e., the
current into the inductor never becomes zero) [28], [29]
3093
where is the period of the PWM signal driving
the switch and the ratio is the duty cycle.
Observe at this regard that the proposed converter operates at
a fixed frequency internally generated by block OSC in Fig. 3,
and set by default equal to 100 kHz. The frequency is exter-
nally adjustable from 50 kHz to 200 kHz through resistor ,
while the duty cycle can range from 5% to 90% with a step of
0.2%.
The boost converter ensures limited discontinuities of current
at the input when operating in continuous mode. Indeed, the
ripple of the input current is
. (2)
This is a very important feature for PV cells which must have
a DC component as stable as possible to maximize efficiency.
One way to minimise the input current variation is to increase
the value of the energy storage inductor (and capacitors
and to filter out input-output voltage variations). Unfor-
tunately, a single phase converter would require a significant in-
crease in the dimensions of the PCB, thereby prohibiting its inte-
gration into a junction box. For this reason, an interleaved boost
converter formed by four identical parallel branches, shifted in
phase by 90 degrees each other, was implemented (not shown
in Fig. 3 for simplicity) [30].
For a four-phase interleaved boost converter, considering the
four intervals in which the converter behavior can be divided
with respect to the duty cycle value, that is ,
with , the input current ripple is
(3)
The above equation shows that can be ideally set to
zero by choosing , 1/2, and 3/4 (0 and 4/4 are useless
choices).
Of course, we cannot use a fixed value of to nullify the
ripple, since we need a variable input-output voltage ratio, but in
any case the ripple reduction is at least a factor of 4 with respect
to a single-phase converter. Indeed, the maximum ripple value
is found by taking the derivative of with respect to and
equating it to zero. Hence, we find and con-
sidering the single-phase and four-phase converter, respectively
(this last value is computed in the first interval ).
As a result, the maximum ripple value is and
for the single-phase and four-phase converter,
respectively.
In the above discussion we assumed that the total inductance
in the four-phase converter is whereas is the value adopted
in the single-phase converter. Although this solution seems to
increase the converter cost and size in practice, as we will see,
the interleaved technique is an economical method to reduce re-
active component values, input and output current variation and
hence associated electromagnetic emissions (EMI) [31]–[38].
In fact, the ripple reduction allows the use of lower input and
output filtering capacitors. This is a very important feature that
avoids the use of electrolytic capacitors whose lifetime is lim-
(1) ited by the number of the voltage/current cycles.
3094 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 11, NOVEMBER 2013
Fig. 5. Schematic diagrams of the blocks implementing the current balancing technique. (a) V-I conversion, sensing, amplification and averaging of the four
currents in MSW1–MSW4. (b) Decision section for voltage . It is made up of 4 comparators and 4 offset voltages. Other three similar sections are required for
to .
Besides, each inductor of the four-phase converter carries
a maximum current that is four times lower than that of the
single-stage counterpart. This means that the physical section
of the inductor coil can be significantly reduced. At the end the
volume occupation of four inductors is comparable to that of
a single inductor carrying the same total current, but the cost
is usually less. In addition, a physically smaller inductor has
lower parasitic resistance and capacitance. This allows the use
of a higher switching frequency (that in a four-phase converter
is four times greater than in the single-stage counterpart with
the same clock period).
It should be also noted that power losses are reduced by 75%
compared to a single-phase converter. Indeed, assuming the
same parasitic resistance in the four phases, resistive
power losses are and /4, in single phase
and 4-phase converters, respectively.
As a drawback, it is recognized that current sharing among
the converter stages is very sensitive to duty cycle mismatches
[39], [40]. Therefore, attention has to be paid to synchronize
the working phases of the interleaved sections. This is a fea-
sible task if the control section is realized as single IC in which
devices mismatch and paths delay are well controlled through
careful design and layout techniques.
B. Current Balancing
Even using all the possible precautions, unavoidable mis-
matches in the four paths of the interleaved converter cannot
be eliminated. This is the main problem for the implementation
of interleaved techniques [41].
Therefore, a balancing technique for the currents in the coils
has been implemented (Current Balance block in Fig. 3). With
the adopted approach, we detect when the difference between
the current in each single phase and the average value (cal-
culated among the four phases) equals a certain threshold and
then the duty cycle of the detected unbalanced phase is changed
accordingly. The schematic diagram of the subsection imple-
menting this balancing technique is illustrated in Fig. 5. Tran-
sistors – are the power switches used in the four
interleaved boost converters (one of which has been depicted in
Fig. 3).
, connected in series to the source terminal, converts
the MOS drain current into a voltage, in order to facilitate the
subsequent processing. Observe that when is ON, its
drain current and the current in the -th inductor are the same.
The value of was set to 40 m as a trade-off between
a superior limit given by the maximum tolerated power dissi-
pation and an inferior limit given by resistor mismatches and
offsets of the following elaboration blocks.
Referring to Fig. 5(a), during the ON state of ( to
4), the voltage across the associated resistor is ampli-
fied by the -th switched-capacitor offset-compensated ampli-
fier [42], [43]. Two non overlapping clocks are used for each
amplifier, and , where the second additional sub cap-
tion indicates which of the four interleaved phases is active.
The operational amplifier is implemented as a simple two-stage
Miller OTA [43]–[45]. An accurate voltage gain of 10 is thus
achieved by setting . The amplified output voltages
to are hence available at the end of phase to
and are then averaged through capacitors , providing voltage
at the end of phase . Voltage
is held on capacitor that filters out unwanted high fre-
quency components. The last elaboration step is accomplished
by a decision section made up of 4 comparators. In each com-
parator a suitable offset voltage is added or subtracted at the non-
inverting input in order to introduce a threshold. The principle
is illustrated in Fig. 5(b), where only the comparator section re-
lated to voltage (in Fig. 5(a) is shown. The same structure
has been replicated also for and .
PULVIRENTI et al.: 4-PHASE INTERLEAVED BOOST CONVERTER 3095

Observe that ADC-3 is not directly fed by the output voltage,

but by its scaled version through voltage divider - . The
function of blocks ADIFF and COMP are for frequency sta-
bility and protection, respectively and will be described in the
following two subsections.

D. Digital Control Section and Fault Control

The main control section (MPPT CTRL in Fig. 3) has
the function of monitoring in real time the voltage and the
current generated by the PV module connected at the input
of the converter and implement the MPPT algorithm. Their
Fig. 6. Simplified schematic of one comparator used in Fig. 5(b). It is im- digitally-converted values are multiplied to obtain the instan-
plemented thorugh a source coupled pair – with one degeneration re-
sistance and active load (M3–M4). The tail current is derived from the taneous power which is utilized by the MPPT algorithm to
bandgap voltage . generate a pulsewidth modulated (PWM) control signal that
is applied to the gate of the switch . Of course, a boost
converter has the capability to increase its output voltage
We set that the maximum difference between the current without any limit. For this reason, a further feedback loop
in each single phase and the average value equals mA has been added through comparator COMP that senses the
(i.e., a difference of 15% when the average current in each output voltage and the duty cycle is limited in a safe way such
phase is 2 A). With the data already given, the offset voltage is that the output voltage does not exceed a given threshold (set
defined as mA mV. Hence, through ). Such a voltage threshold can be selected as a
voltages , and function of the characteristics of a single cell or a group of cells
are compared to . Therefore, connected in series at the input of the DC-DC converter, but in
becomes “1” for . any case it must not exceed the maximum voltage allowed by
Similarly, becomes “1” for the technology used to implement the converter. This further
. and adjustment is particularly advantageous at the system level
and ) are finally used by thanks to the fact that the voltage of the panel integrating the
the digital section that generates the gate signal of to converter is fixed at a value which does not depend on the
respectively decrease or increase the duty cycle, coded into a irradiation and the temperature. Therefore, the inverter is fed
10-bit word, by 2 bits (1 bit). with a more controlled voltage compared to that which would
In conclusion, 4 levels of duty cycle states are present within be derived from a conventional panel, thus working in a much
the offset band (2 120 mV). The same discussion holds for the narrower range around the nominal input value and thereby
other 3 arrays of comparators. resulting in a benefit to the conversion efficiency.
Fig. 6 illustrates the adopted strategy to implement the com- Many control algorithms have been developed to implement
parators and the offset voltage. The comparator is a simple dif- the MPPT for PV fields, including the Hill Climbing, Incre-
ferential pair with active load. Offset is introduced through the mental Conductance and fuzzy approaches [46]–[48]. An opti-
degeneration resistor . More specifically, if the tail current mized algorithm for Distributed MPPT has also been presented
is , where is the bandgap voltage (approxi- [49]. We selected the Perturb and Observe algorithm for its sim-
mately 1.25 V), then the voltage drop onto (i.e., the offset plicity. In this approach, the power , generated by the cell
voltage) is approximately equal to . To ob- string and sampled at time , is compared to the value acquired
tain about 120 mV we have to set . at the previous sampling period, . The direction of ad-
The solution is straightforward and inaccuracies in the abso- justment of the duty cycle, either incrementing or decrementing,
lute value of the offset voltage are not a concern since they are remains unchanged as long as the condition
tracked in all the comparators due to the IC matching proper- occurs, i.e., as long as it registers an increase of the instanta-
ties. A lower offset band could be feasible, but is more prone to neous power extracted from the cell string. In contrast, the di-
relative mismatches. rection of the adjustment of the duty cycle is changed when
is detected.
The safety of the application is guaranteed by the Fault Con-
C. ADCS
trol block which disables the gate drivers in the case of output
Three ADCs are required to monitor in real time the current over-voltage or over-temperature (this case is sensed by the tem-
generated by the cell string (ADC-1 in Fig. 3) and the voltage at perature sensor block TEMP SENS in Fig. 3).
the input (ADC-2) and the output (ADC-3) of the converter. The
ADCs are all based on a resistive-string 10-bit Successive Ap- E. Other Blocks and Issues
proximation DAC. Voltages and are derived through The converter has a under voltage lockout system (UVLO)
two resistor dividers realized outside the IC ( - and - with hysteresis of 500 mV. The two thresholds are 6.5 V for
in Fig. 3). The degeneration resistors in series to the power turning on and 6.0 V for turning off. At power up, until the
switches ( in Figs. 3 and 5) are used to convert the in- supply source provides a voltage lower than 6.5 V, the circuit
ductor currents into a voltage. stays in the OFF state and the whole current generated by the
3096 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 11, NOVEMBER 2013
PV panel is directly transferred to the output node through the
intrinsic diode of the synchronous rectifiers ( in Fig. 3, the
diode anode is the source-body and the cathode is the drain).
When the applied voltage reaches 6.5 V, the converter oper-
ates in the burst mode [50] as described below, and sequentially
activates each of the four phases. Initially, only phase 1 is en-
abled, charging the inductor only for one cycle out of 15 cycles.
Then the duty cycle is progressively increased until phase 1 is
active at every cycle and at the default switching frequency of
100 kHz. After phase 1 has reached its steady-state condition,
all the other phases are progressively switched on in the fol-
lowing sequence: phase 3, phase 2 and, lastly, phase 4. All the
sequences are running when the power generated by the PV cells
is increasing. Otherwise the sequence may go back and then for-
ward again.
Regarding the frequency stability, it is known that digital fre-
quency compensation techniques can achieve better noise im-
munity compared to analog ones. However their main draw-
back is due to the inherent delay from analog-to-digital conver-
sion, computation and PWM update [51], [52]. As a result, the
simplest analog approach was chosen, by considering the linear
converter model and adopting voltage control.
The auxiliary differential amplifier (ADIFF in Fig. 3), which
compares a scaled version of with the bandgap voltage
, is embedded in a high-gain negative feedback loop. There-
fore, the loop ensures that approaches . Denoting
the differential amplifier output resistance as , then
provides frequency compensation generating the dominant pole
). Resistor is used to introduce a (negative)
zero in the loop gain. Its expression is ). The zero can
be externally trimmed through the resistor in order to cancel
out the output pole (due to and the load). The suggested
components values are nF and k which
guarantee stability in most applications.
As far as the cost is concerned, it is useful to note that the
function of the bypass diode included in conventional modules
is eventually realized either by the parasitic diode of the inte-
grated switch, , or by that of the rectifying transistor
of the DC-DC converter. Therefore, the bypass diodes are no
longer required.
IV. IMPLEMENTATION
As discussed in the previous section and referring again to
Fig. 3, we realized in a single monolithic IC the digital control
sections, ADCs, auxiliary amplifiers, regulators and the four in-
stances of the power and rectifying switches ( and ).
Besides, we included the gate drivers, and some service blocks
such as pre-regulators, oscillator, under-voltage lock-out, tem-
perature sensor, comparators, differential amplifiers, etc.
The design strategy and component selection was aimed both
to minimize area and maximize the power conversion efficiency
by carefully minimizing undue power losses. The principal ob-
stacle was due to the fact that the DC-DC converter has to be
used in a broad range of PV modules types, within a power range
up to 300 W. This requires a more complicated design procedure
compared to a converter that has to be embedded into a specific
PV module [49].
Fig. 7. Micrograph of the designed IC device implementing the controller for
the interleaved DC-DC converter. It includes four power and four rectifying
switches (power section) plus associated gate drivers, the MPPT logic and ser-
vice blocks, and three ADCs. The area is about 15 mm .
The IC was designed and fabricated in the BCD8 technology
of STMicroelectronics [53]. This process allowed the realiza-
tion of complex monolithic solutions in the field of intelligent
power applications, as it enables the integration on the same sil-
icon substrate of high voltage power transistors together with
high density CMOS logic of 1.8 V and 3.3 V in 0.18- m lithog-
raphy. The maximum operating voltage supported by this tech-
nology is 40 V.
The micrograph of the designed device is shown in Fig. 7.
One can distinguish the different sections: Power (comprising
four active switches and four synchronous rectifiers; the aspect
ratio of each power MOS transistor is 200 m/0.8 m), Logic,
and ADC. The IC does not require specific cooling techniques.
Also standard packages can be used. Of course, if the DC-DC
boost converter is installed inside the junction box or just on
the back side of the PV module, it will work under increased
ambient temperature. In particular, depending on the type of in-
stallation, weather conditions and PV cells technology, the PV
module can reach up to 80 C. In this situation the issues con-
nected with thermal behavior of the booster converter have to be
analyzed [54]. But as we will show in the next subsection the IC
works correctly up to 110 C and under full loads the maximum
PCB temperature is about 75 C.
The main parameters of one of the MOS transistors are sum-
marized below. Open channel resistance, m ;
Input capacitance, pF; Output capacitance,
pF; Maximum drain-source voltage, V;
Maximum drain current, A; Breakdown Voltage,
V; and Maximum operating junction temperature,
C.
Inductors and capacitors (and the two auxiliary resistor-string
voltage dividers) in Fig. 3 are left as discrete components.
Specifically, the inductors were set equal to 47 H and the
capacitors to 2.2 F. The adoption of relatively low-valued
capacitors avoided the use of electrolytic capacitors, which
have a significantly shorter average lifetime compared to other
electronic components. The device is turned on if the voltage
at the output of the PV module is higher than 6.5 V. Since the
maximum output voltage is limited to 40 V, then from (1) the
duty cycle ranges from about 0.1 ( V) to about 0.9.
Fig. 8 shows the simplified scheme of the designed PCB with
the proposed IC and the passive components. and
to belong the basic interleaved boost converter, –
are the auxiliary bootstrapping capacitors used to drive the gate
PULVIRENTI et al.: 4-PHASE INTERLEAVED BOOST CONVERTER 3097

Fig. 8. Schematic of the proposed circuit with the designed IC and passive
components.

Fig. 10. Current waveforms: (a) currents in the four branches of the inter-
leaved boost converter. Upper traces are obtained under normal balanced condi-
tions. Lower traces are obtained by forcing a mismatch in one of the inductors.
(b) input and output currents. The implemented current balancing systems sta-
bilizes the maximum current difference (300 mA) with respect to the average
value. V, and V are the other operating conditions.

respectively set in the vertical and horizontal axis of Fig. 10(a);

whereas 1 A/div and 10 ms/div are set in Fig. 10(b).
Fig. 9. Printed circuit board of the four-stage interleaved DC-DC converter. Let us first consider the upper group of traces in both figures,
Dimensions are 4 7 cm .
labeled as balanced. These traces are obtained with practical
matching conditions of passive components. It is seen that de-
spite these unavoidable mismatches, the four currents are quite
of the rectifying switches ( in Fig. 3). and are
balanced and their mean values are 1.51 A, 1.53 A, 1.47 A,
filtering capacitors used to reduce the voltage ripple across the
and 1.46 A. This shows indirectly that the careful design and
voltage dividers of and , respectively. Three Schottky
layout strategies provide accurate symmetry in the four phase
diodes, – , and an additional capacitor are also utilized.
paths of the interleaved converter. As a result, the input and
is a decoupling diode between the input and the IC posi-
output currents are nearly constant with their average values
tive power supply, . In parallel to the capacitor
being A and A and with small rip-
is adopted to reduce unwanted supply variations. is a by-
ples well below 5%, effectively containing the electromagnetic
pass diode between the input and the output, acting when the
emissions.
output is accidentally shorted to ground. is a bypass diode
In order to test the efficacy of the implemented current bal-
between the output and ground, acting when the PV module is
ancing system, we intentionally created a strong mismatch in
completely shaded.
one of the four phase paths by changing the value of one of the
Fig. 9 shows the photograph of the application board which
inductors. The effect is illustrated in the same Fig. 10(a) with
measures 4 cm 7 cm.
the lower group of traces labeled as unbalanced (the curves are
offset to be displayed into the same picture with the previous
V. MEASUREMENTS ones). Even under this extreme working setting, the mean values
In this section we shall summarize the main results of sev- of the input currents resulted to be 1.45 A, 1.42 A, 1.45 A, 1.67
eral measurements performed either indoor, under controlled A. It is also confirmed that the currents differ at maximum by
settings and by powering the system with a solar array simu- 300 mA (the value expected) with respect to the average value
lator, or outdoor, under the direct sunlight and hence with vari- of the four phases. Of course, in this case the ripple of the input
able ambient conditions. and output current is increased, as shown in Fig. 10(b) lower
As a preliminary step, we validated the effectiveness of the traces.
designed interleaved DC-DC boost converter. We set at the As a second step, the power conversion efficiency of the cir-
input V and A( W) and at the cuit was evaluated. At this purpose, the output of the converter
output V. Figs. 10 show the measured currents at was connected to an electronic load (Chroma 6314A) in the
each of the four phases (Fig. 10(a) and the total input and output constant voltage mode. A Solar Array Simulator, SAS, (Agi-
converter currents (Fig. 10(b). 500 mA/div and 2 s/div are lent Technologies E4360A) was used as power supply.
3098 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 11, NOVEMBER 2013

Fig. 11. Measurement system for indoor testing. The device under test (DUT)
is the printed circuit board with the proposed converter.

Fig. 13. Power conversion efficiency versus for equal to 30 V.

The MPP current is a parameter that is varied from 2 A to 8 A (2 A steps) causing
to vary accordingly.

Fig. 12. Start-up behaviour of the input/output voltages/currents of the DC-DC

converter. We set V, A, V and
A. At the output the constant voltage was set to 36 V.
Fig. 14. MPPT conversion efficiency versus for equal to 15 V.
The MPP current is a parameter that is varied from 2 A to 8 A (2 A steps) causing
to vary accordingly.
Two voltmeters (Agilent 34401A digital multimeter) and two
ammeters (Agilent U1242 digital multimeter) were then used to
measure the input/output voltages and currents. The measure- the magnetic core losses closely related to the specific be-
ment system is illustrated in Fig. 11. Input power and output havior of the magnetic material. As a result, efficiency can
power were then computed as and be improved by selecting inductors with lower losses.
and the efficiency as percentage . As a third step we measured the MPPT accuracy defined as
Several measurements were performed under different con- average . The power values are calculated
ditions, in the following we will show some results. as follows and .
First we verified the correct start-up behavior of the system. To calculate , the SAS has been connected directly
We set V, A, V and to the electronic load. Fig. 14 shows the MPPT efficiency, when
A. At the output the constant voltage was set to 36 V. is 15 V and ranges from 2 A to 8 A (with 2 A steps).
Fig. 12 shows the transient behavior of the input/output volt- Then, we measured the performance of two converters con-
ages and currents after system turning on. The steady state op- nected in series, as shown in Fig. 2(a). Each device is supplied
eration is reached in around 130 ms. by a SAS whose initial set up is V, V
Fig. 13 shows the power conversion efficiency versus (open circuit output voltage), A, A (short
after setting the MPP voltage equal to 30 V and varying circuit output current). Their outputs are connected in series to
from 2 A to 8 A (with 2 A steps). Of course, changing the cur- an electronic load (constant voltage kept to 60 V). We simulated
rent level means in turn different delivered power. Efficiency is two main operating cases: 1) Two fully operating panels; 2) One
almost constant between 98% and 99%, slightly decreases for fully operating panel, one panel with some shaded cells (whose
increasing . The figure shows also that with a fixed output bypass diode is on). It implies that the generated currents are the
voltage (but power changes) the efficiency is quite constant. same, whereas the voltages are different.
By further analyzing these results we understood that the The applied voltages for the two cases described above are:
power conversion efficiency is limited by two main power 1) V; 2) V,
losses: V. The output current is 4 A in both cases. Therefore, the input
1) the power consumption of the IC boost converter. It was power is 192 W in the first case and 168 W in the second one.
found to be less than 0.5% of the output power. Fig. 15 compares the input and output power of the series con-
2) the power dissipated in the inductors, which can in turn be nection versus time. A change between the first and the second
split into two main contributions: a DC contribution (lower considered case is performed at minutes. Power con-
than 0.2%), due to series resistance losses of the winding version efficiency is always greater than 96.5%. This last test
wire; and an AC contribution (lower than 0.6%), due to highlights the importance of the use of PV module converters.
PULVIRENTI et al.: 4-PHASE INTERLEAVED BOOST CONVERTER
Fig. 15. Input and output power for a series connection of two designed boards
supplied by a SAS. At 50 minutes the initial matched condition (
V) changes into the unbalanced one ( V,
V). Power conversion efficiency greater than 96.5% is guaranteed in both
cases.
Fig. 16. Infra-red camera photograph of the DC-DC converter under full load.
Fig. 17. Quiescent current versus temperature for a fixed output power of
112 W and for different output voltages.
In fact, it is worth noting that, as the PV modules have different
voltages, the output voltage of the converters in series is con-
stant. In a real PV system, made of many strings in parallel, if
the string voltages are different some block diodes are turned on
and hence the array power is drastically reduced.
The photograph in Fig. 16 is taken with an infra-red camera
and shows the thermal behavior of the DC-DC converter under
full load. The red zones have the highest temperature that is
below 75 C.
Fig. 17 shows also the total IC quiescent current versus tem-
perature. A fixed power of 112 W was considered and three dif-
ferent output voltages (18 V, 28 V and 40 V) were set.
3099
Fig. 18. Trend of the output voltage of the converters (A and B) during the two
measurement sessions (1 and 2).
In the last test the converter is operated under real outdoor
conditions, i.e., considering the impact of some phenomena
such as: spreading of the electrical characteristic of the PV
module, impact of different irradiance and temperature of
the PV module, impact of the temporal variation of the main
ambient variables (irradiance, temperature and wind speed).
The outdoor measurements were performed, particularly, to
evaluate the converter behavior in a series connection. Two
converters were connected respectively to two PV modules
(Sharp NU180E, with main nominal parameters W,
A, V, A,
V). Some preliminary tests were performed to establish the
real rating of each module, i.e., rated tolerance %). The first
module, named “module A”, connected to the converter A, had
a power, reported at standard test conditions (STC) equal to
180 W, whereas the second, named “module B”, connected to
the converter B, had a power of 172 W.
Subsequently, during the measurement sessions, named sess.
1 and 2, the two modules have different tilt angles, respec-
tively 0 for module A and 30 for module B, in such a way
they are stroke by different irradiance. The two sessions last
30 minutes and the measurements are recorded every 20 sec-
onds. During these time periods the environmental conditions
remained pretty constant (clear sky day), the average value of
the irradiance, , during each session and for each module were
measured in the plane of the module, by means of a thermopile
pyranometer. The ambient temperature ranged between 28 C
and 29 C and the photovoltaic operating temperatures (mea-
sured on the rear face of the modules) ranged between 33 C and
34 C. The main results are reported in Figs. 18 to 20. Specif-
ically, Fig. 18 shows that the fixed output voltage of 35 V is
correctly shared between the two converters without any oscil-
lation and stability problem. Figs. 19 and 20 show the output
power and the power conversion efficiency, respectively. We
see from Fig. 20 that the average total efficiency during the
session 1 % is lower than the one
during session 2 % , this difference
3100 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 11, NOVEMBER 2013

The architecture of the converter, the layout of the integrated

circuit, the application board, the waveforms and the experi-
mental results have been reported to verify the potential of this
solution. Power conversion efficiency was found better than
93% in the worst case and about 98% for average cases. More-
over, it was validated the suitability of this solution to improve
the power efficiency of series-connected PV sources.
The converter with additional features not mentioned in this
paper (like for instance the introduction of a serial-parallel com-
munication port) has been commercialized very recently under
the name of SPV1020 by STMicroelectronics [55]. Presently,
a PV field equipped with the SPV1020 and, for comparison,
with other commercial power optimizers has been realized and
is being monitored. Preliminary data show that our solution pro-
vides the same power improvement of the counterparts. How-
ever, further improvement is to be expected when a dedicated
DC/AC converter (without the boost and the MPPT sections)
will be employed. The design and exploitation of a simplified
Fig. 19. Trend of the output power of the two converters (A and B) in series,
during the two measurement sessions (1 and 2).
inverter to be used with the proposed solution will be the next
step of this research. Besides, the use of a dedicated converter
for each of the three substrings constituting a PV module will
be investigated. Considering parallel output connection as in
Fig. 2(b) and under partial static shadowing of one cell, prelimi-
nary measurements show that an average power increase of 20%
was found compared to a traditional PV module series string
connection.

Fig. 20. Trend of the power conversion efficiency of two converters in series,
during the two measurement sessions (1 and 2).
appears wider than the laboratory tests, but the effect of the
output voltage variation on one hand and the uncertainties in the
outdoor measurements on the other hand partially justify these
results, which in any case give a total efficiency better than 93%.
VI. CONCLUSIONS AND FUTURE WORK
In this paper we presented an interleaved DC-DC converter
capable of improving the efficiency of a photovoltaic system
adopting the distributed conversion approach. Thanks to the
adopted BCD8 technology from STMicroelectronics, the power
and control sections have been integrated for the first time into
a monolithic form, therefore minimizing the number of external
components and the overall application cost which compares
favourably with that of the conventional centralised architec-
ture in today commercial systems.
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3102 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 11, NOVEMBER 2013
Francesco Pulvirenti was born in Catania, Italy, in
1964, and graduated in electronic engineering at the
University of Pisa, Pisa, Italy.
He joined STMicroelectronics in 1991 where he is
currently working as Design Director of Integrated
Circuits for Photovoltaic and Industrial applications.
He started as design engineer spending around ten
years developing smart power ics, linear regulators,
switch mode power supply and power management
respectively for industrial, mobile phone, battery
charger and computer applications. In 2001 he
moved to Display segment to manage the design of new drivers dedicated to
liquid crystal display applications for portable equipments becoming in 2004
Design Director of the Display Division. In 2007 he was appointed Director
of the Photovoltaic Business Unit with the mission to define and develop new
application specific devices for Photovoltaic market. He holds more than 50
international patents on Analog and Smart Power ICs, he is also coauthor of
13 papers published in international conferences/journals and coauthor of the
book Liquid Crystal Display Drivers (Springer, 2009).
Amedeo La Scala received the laurea degree in
electronic engineering in 1996 from the Univer-
sity of Palermo, Palermo, Italy.
In 1997, he joined STMicroelectronics, Catania,
Italy, as a digital designer for set top box. In
2004 he joined the Liquid Crystal Display Divi-
sion to develop display drivers for portable de-
vices. Since 2008 he is working on a new chal-
lenging activity for photovoltaic applications. In
this context he has contributed to the develop-
ment of new products for efficient power extrac-
tion like the SPV1001 and SPV1020.
Domenico Ragonese was born in Catania, Italy in
1973, and graduated in electronic engineering at the
University of Catania, Italy.
He joined STMicroelectronics, Catania, Italy, in
2001 where he is currently working as Application
Manager of Integrated Circuits of Industrial (IPS,
I/O Link families) and Photovoltaic applications. He
started as application engineer spending around 6
years designing SW and HW application environ-
ments for display drivers in consumer market. In
2007, he was appointed as Senior Application Engi-
neer for the Photovoltaic Business Unit with the mission to define and develop
new application specific devices for Photovoltaic Market. From 2009 to 2012
he continued to work in the same organization but as an Application Manager.
He holds 1 international patent on Photovoltaic Application Architectures.
Keith D’Souza received the B.Sc. (hons) degree
from Imperial College, London, U.K., in electrical
and electronic engineering.
He has worked for ST Microelectronics in France,
Italy and U.K. He is now working in the area of Power
Electronics for Photovoltaic, Industrial and Telecom
applications. He is member of the Institution of En-
gineering & Technology (IET).
Giuseppe M. Tina received the M.Sc. degree in 1988
and the Ph.D. degree in 1992 both in electrical en-
gineering from the University of Catania, Catania,
Italy.
He joined Agip Refineries and ST Micro-
electronics, Italy, where he worked as Electrical
Engineer. He is now Associate Professor at the
Dipartimento di Ingegneria Elettrica Elettronica
e Informatica at the University of Catania. His
research interests include renewable generation
systems, especially wind and photovoltaic systems,
Dispersed Generation Systems, ancillary services market and storage systems.
He is in charge of power system research group and laboratory at University
of Catania.
Salvatore Pennisi received the laurea degree in elec-
tronic engineering in 1992 and the Ph.D. degree in
electrical engineering in 1997, both from the Univer-
sity of Catania, Italy.
In 1996, he become a Researcher (Assistant Pro-
fessor) and in 2002 he was appointed an Associate
Professor at the DIEEI, University of Catania. His
main research interests include circuit theory and
analog design with emphasis on low-voltage and
current-mode techniques, multi-stage amplifiers with
related frequency compensation, data converters and
the analysis of high-frequency distortion in analog circuits. More recently, his
research activities have involved driving circuits and techniques for liquid
crystal displays and circuits for efficient energy harvesting. He published
over 70 international journal papers, 120 conference proceedings, and is the
coauthor of the books CMOS Current Amplifiers (Kluwer, 1999), Feedback
Amplifiers: Theory and Design (Kluwer, 2001) and Liquid Crystal Display
Drivers-Techniques and Circuits (Springer, 2009).
Dr. Pennisi has served as an Associate Editor of the IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS and is member of the IEEE
CASS Analog Signal Processing Technical Committee.