Circuits, Systems, and Signal Processing

https://doi.org/10.1007/s00034-019-01179-x

High Performance Four‑Quadrant Analog Multiplier Using

DXCCII

Jagadish Rajpoot1 · Sudhanshu Maheshwari1

Received: 28 February 2019 / Revised: 21 June 2019 / Accepted: 22 June 2019

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Abstract
This paper presents a four-quadrant analog multiplier using a single dual-X second-
generation current conveyor (DXCCII). The proposed analog multiplier employs
two NMOS transistors operating in triode region, besides a single DXCCII. The per-
formances of the proposed analog multiplier are verified through PSPICE simula-
tion using 0.18 μm TSMC CMOS process parameters. Simulation results reveal that
the circuit has a − 3 dB bandwidth of 19.30 GHz and 0.79% total harmonic distor-
tion for the input voltage of 250 mV. The application of proposed analog multiplier
as a squarer, for amplitude modulation and as frequency doubler are also included.
The detailed comparisons with existing literature justify the novelty of the proposed
circuit.

Keywords  Four-quadrant analog multiplier · Dual-X second-generation current

conveyors (DXCCIIs) · Amplitude modulator (AM) · Squarer circuit · Frequency
doubler

1 Introduction

Nowadays, analog circuits are designed using only active devices. The advantages
of using only active devices are beneficial for integrated circuit fabrication for sav-
ing chip area and power consumption. Therefore, several basic circuits have been
presented such as filter [18], full wave rectifier [8] and multiplier/divider [1, 5, 6,
9, 11, 12, 17]. These circuits are designed by using second-generation current con-
veyor (CCII), second-generation dual-X current conveyor (DXCCII), current dif-
ferencing buffered amplifiers (CDBA) and second-generation current controlled

* Sudhanshu Maheshwari
maheshwarispm@rediffmail.com
Jagadish Rajpoot
jacky91jagadish@gmail.com
1
Department of Electronics Engineering, Z.H. College of Engineering and Technology, Aligarh
Muslim University, Aligarh, India

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 Circuits, Systems, and Signal Processing

conveyor (CCCII) as active elements without any passive elements. Current mode
circuits have found wide acceptance over their voltage mode counterparts for a vari-
ety of analog signal processing applications. This is mainly due to their superior
bandwidth and slew rate performances over voltage mode circuits. Moreover, many
simple summing/differencing operations require reduced circuit complexities than
needed for voltage mode operations. Current mode circuits are also suitable for inte-
gration in CMOS technology and thus finding favor of analog circuit designers.
For instance, second-generation current conveyors (CCIIs) are used in many lin-
ear and nonlinear applications as active building blocks. This is due to their high sig-
nal bandwidths, high slew rate, greater linearity, and larger dynamic range as com-
pared to operational amplifiers (op-amps)-based ones [5]. Therefore, a large number
of CCII-based circuits for various functions were proposed in technical literature [6,
9, 15]. An active circuit element of current interest, called dual-X second-generation
current conveyor (DXCCII), was proposed quite long back [18]. It combines the fea-
tures of the CCII and inverting CCII (ICCII). Literature survey shows that DXC-
CII has found many applications in analog signal processing [5, 8, 17, 18]. Some
important analog signal processing functions require nonlinear building blocks like
multipliers, dividers and square rooting. These blocks find numerous applications in
communication and instrumentation system. Several analog multiplier circuits based
on various active building blocks are available in the literature, namely dual-X cur-
rent conveyor (DXCCII) [5, 17], CCIIs [6, 9, 13], second-generation current con-
trolled conveyor (CCCII) [1, 12], current-differencing buffered amplifiers (CDBAs)
[4, 11], operational amplifiers (Op-amp) [14], differential difference current convey-
ors (DVCC) [3], current differencing transconductance amplifiers (CDTAs) [16],
operational trans resistance amplifier (OTRA) [10]. However, most of these analog
multipliers suffer from large number of active elements [1, 5, 6, 9, 11, 12, 17] and
additional active or passive elements in form of resistors [14].
In this paper, a new four-quadrant analog multiplier using a single dual-X sec-
ond-generation current conveyor (DXCCII) and two NMOS transistors is proposed.
The analog multiplier is based on the operation of two NMOS transistors in linear
region. CMOS DXCCII can be used to realize the four-quadrant analog multiplica-
tion using the proposed structure. The proposed analog multiplier provides simple
configuration, low cost, suitable for integrated circuit (IC) implementation and good
performance. It can be used effectively within range of input voltages ± 250 mV, and
it can multiply over a range of ± 250 mV. The performance of the analog multiplier
is verified by PSPICE simulator using 0.18 μm TSMC CMOS process parameters.
It is found that the simulated results are in close agreement with the mathematically
predicted results. The performances of the analog multiplier as amplitude modula-
tor, squarer and frequency doubler are also verified.
The following sections include DXCCII description in Sect. 2, the proposed mul-
tiplier in Sect. 3, followed by the simulation results and comparative study in Sect. 4.
Application examples are presented in Sect. 5, and the conclusion is given in Sect. 6.

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Circuits, Systems, and Signal Processing

2 DXCCII Description

DXCCII is a five-terminal device with terminals namely Y, XP, XN, ZP, ZN. The two
X terminals are namely XP (non-inverting X terminal) and XN (inverting X terminal).
The XP and XN terminal currents are conveyed to the respective Z terminals, namely
ZP and ZN. The voltage at the XP follows that of Y terminal, whereas the voltage
of XN follows the inverted version of voltage at Y terminal. DXCCII combines the
properties of second-generation current conveyers (CCII) and inverting second-gen-
eration current conveyers (ICCII). The input impedances for the ideal DXCCII are,
respectively, infinite at port Y and zero at Port X. The port Z, i.e., equivalent to cur-
rent output, shows infinite output impedance [18]. Several realizations of DXCCII
were proposed. This includes CMOS and AD844 realization. The CMOS realization
requires twenty MOSEFT transistors [18], whereas the AD844 realization, which
is commercially available IC, require four IC and two or three resistances [7]. As a
general observation, DXCCII and its variants have found recent literature space [2].
Figure 1 shows the symbol of DXCCII and its CMOS circuitry [18], whose rela-
tions are given below with the various port Y, XP, XN, ZP, ZN as indicated. The arrow
shows the direction of current in the symbol below:
The DXCCII can be characterized by the following matrix:

Fig. 1  a DXCCII symbol; b CMOS implementation

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 Circuits, Systems, and Signal Processing

⎡ IY ⎤ ⎡ 0 0 0⎤
⎢ VXP ⎥ ⎢ 1 0 0 ⎥ ⎡ VY ⎤
⎢ VXN ⎥ = ⎢ −1 0 0 ⎥ ⎢ IXP ⎥ (1)
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ IZP ⎥ ⎢ 0 1 0 ⎥ ⎣ IXN ⎦
⎣ IXN ⎦ ⎣ 0 0 1⎦

By solving the matrix, following relations are obtained. These can be referred to
as the defining equation of DXCCII.
IY = 0, VXP = VY , VXN = −VY , IZN = IXN , IZP = IXP (2)
From above equations, it is clear that DXCCII is a combination of CCII and
ICCII.

3 Proposed Circuit

The proposed four-quadrant analog multiplier circuit employing a single DXCCII is

shown in Fig. 2. The MOSFETs M1 and M2 are assumed to be matched and biased
to operate in triode region. Voltage VG is applied at gate terminal to bias MOSFET
in triode region. Thus, the expression for drain current for the MOSFETs is given as
below.
[ ]
W ( ) 2
Vds
ID = Kn VGS − Vth Vds − (3)
L 2

Here, Kn is transconductance; W and L are the channel width and channel length
of the MOSFET, respectively. The other terms are of their usual meaning.
Since the source terminals of the MOSFETs M1 and M2 are virtually grounded,
due to voltage following properties of DXCCII ( VY = 0 ), and thus, using Eq. (3), the
current IXP and Id can be expressed as:

Fig. 2  Proposed four-quadrant analog multiplier circuit

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Circuits, Systems, and Signal Processing

[ ]
W ( ) V12
IXP = Kn V2 + VG − Vth V1 − (4)
L 2

[ ]
W ( ) V12
Id = Kn VG − Vth V1 − (5)
L 2

Current at port XN of DXCCII

IXN = Id − IZP (6)
According to current conveying property of DXCCII, output current of proposed
analog multiplier is as:
W
Iout = Kn VV (7)
L 1 2
From Eq. (7), it can be seen that the circuit operates as an analog multiplier with
multiplication constant equal to Kn WL  . If the analog multiplier is loaded with a resis-
tor RL, then output voltage of analog multiplier can be expressed as
W ( )
VOut = Iout ∗ RL = Kn V V ∗ RL = K V1 ∗ V2 (8)
L 1 2
where K = Kn WL ∗ RL is the multiplication constant.
As it can be seen from (7) and (8), the proposed multiplier can operate in
transconductance mode as well as in voltage mode.
The DXCCII introduces non-ideality due to deviation of voltage (current) transfer
gain and also due to development of parasitic components.
The matrix equation defining a non-ideal DXCCII due to voltage (current) trans-
fer may be given as

⎡ IY ⎤ ⎡ 0 0 0 ⎤
⎢ VXP ⎥ ⎢ 𝛽P 0 0 ⎥⎡ VY ⎤
⎢ VXN ⎥ = ⎢ −𝛽n 0 0 ⎥⎢ IXP ⎥ (9)
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ IZP ⎥ ⎢ 0 𝛼P 0 ⎥⎣ IXN ⎦
⎣ IXN ⎦ ⎣ 0 0 𝛼n ⎦

I = 0, VXP = 𝛽P VY , VXN = −𝛽n VY , IZN = 𝛼n IXN , IZP = 𝛼P IXP (10)

(Y )
Here
( ) p n𝛽 𝛽 are the voltage transfer gains from the
( ) Y port to Xp(Xn)
( ) ports, and
𝛼p 𝛼n are the current transfer gains from the XP Xn port to the ZP Zn ports. (Ide-
ally, there voltage and current transfer gains are unity in magnitude.) The non-ideal
performance of the proposed analog multiplier can be found by assuming VX = 𝛽VY
where β is a voltage transfer ratio; 𝛽 = 1 − 𝜀v and ||𝜀v || ≪ 1 ; IZ = 𝛼IX where α is a
current transfer ratio;𝛼 = 1 − 𝜀i and ||𝜀i || ≪ 1 , 𝜀v and 𝜀i are voltage and current track-
ing errors, respectively. In this case, the output voltage of multiplier in (7) can be
rewritten as

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 Circuits, Systems, and Signal Processing

[ ]
( ) W( ) W ( ) V2
Vout = 𝛼n ∗ RL 1 − 𝛼P Kn VG − Vth − 𝛼p Kn V1 ∗ V2 + 𝛼P − 1 1
L L 2
(11)
It is evident from (11) that the multiplier is affected by non-ideality of DXCCII;
however, its adversity depends on the deviation of current transfer ratio 𝛼p and 𝛼n
from the ideal value.

4 Simulation Results

To validate the proposed analog multiplier of Fig.  2, it is simulated by PSPICE

simulator using 0.18  μm TSMC CMOS model parameters. The CMOS realiza-
tion of DXCCII shown in Fig. 1 with the NMOS and PMOS transistor aspect ratios
W/L = 0.9μ/0.18μ and W/L = 1.8μ/0.18μ, respectively, is used. The power supply
voltages are taken as VDD = −VSS = 0.9 V, and biasing voltage VB = − 0.38 V. MOS-
FETs M1 and M2 are used with aspect ratios W/L = 1.35μ/0.18μ. The bias voltage
VG = 0.6 V for operation of MOSFETs M1 and M2 in triode regions. The summary
of measured parameters for DXCCII is given in Table  1. The multiplier circuit is
loaded with RL = 1  kΩ. Figure  3a, b shows the DC transfer characteristics of the
proposed multiplier. Here, in Fig. 3a, the input voltage V1 is swept from − 0.25 V
to + 0.25 V while V2 is varied from − 0.25 to + 0.25 V in steps of 125 mV, and for
Fig.  3b, the input voltage V2 is swept from − 0.25 to +0.25  V, while V1 is varied
from − 0.25 to + 0.25  V in steps of 125  mV. It confirms that the proposed circuit
acts as a four-quadrant multiplier, with good linearity.
Figure  4 shows the frequency response of the proposed analog multiplier. In
this case, voltage V2 is kept constant at 200 mV, while V1 is taken as an AC source
having amplitude 150 mV. The − 3 dB bandwidth is found to be about 19.30 GHz,
which suggests excellent high frequency performance.

Table 1  Summary of measured Parameters Value

DXCCII parameters
Technology 0.18 μm
Supply voltage (V) ± 0.9
Voltage transfer range (mV) ± 200
Voltage transfer bandwidth (Vxp/Vy) GHz 40.20
Voltage transfer bandwidth (Vxn/Vy) GHz 39.60
Current transfer frequency (Izp/Ixp) GHz 39.47
Current transfer frequency (Izn/Ixn) GHz 40.60
Voltage transfer gain (Vxp/Vy) 1
Voltage transfer gain (Vxn/Vy) 0.9
Current transfer gain (Izp/Ixp) 1
Current transfer gain (Izn/Ixn) 1
Power dissipation (mW) 7.3

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Circuits, Systems, and Signal Processing

(a) (b)
Fig. 3  DC Transfer characteristic a V1 is swept, V2 changed in steps, b V2 is swept, V1 changed in steps

Figure  5 shows the variation of total harmonic distortion (THD) with the
amplitude variation of the input signal for frequency of signal as 2 GHz. For this
evaluation, a sinusoidal signal of varying amplitude with frequency 2  GHz is
taken as V2 where a constant 150 mV DC voltage is applied to V1. It shows that
the maximum THD does not exceed 0.79% for the entire input range, which sug-
gests excellent performance. The performance comparisons of the proposed mul-
tiplier with previously published exemplary works shown in Table 2 also suggest
superior performance.

Fig. 4  AC characteristic of the proposed multiplier

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 Circuits, Systems, and Signal Processing

Fig. 5  Variation of THD (%) with the amplitude of the input signal

Table 2  Comparison of performance of available works with proposed multiplier

Performance param- Technology (μm) Supply Linear Bandwidth Active No of extra
eters voltage input range element MOS used
(V) (V) count

DXCCII [17] 0.35 ± 2.5 ± 0.5 100 MHz 1 2

DXCCII [17] 0.35 ± 2.5 ± 1.0 100 MHz 2 3
DXCCII [5] 0.35 ± 1.6 ± 0.1 450 MHz 2 6
CCII [6] Bipolar – ± 0.5 – 2 2
CDBA [11] 0.35 ± 5.0 ± 0.25 82 MHz 1 6
CCII [9] 0.25 ± 1.5 ± 0.45 95 MHz 2 2
CDBA [4] 1.20 ± 5.0 ± 0.6 10 MHz 1 2
BiCMOS CCII [13] 0.80 ± 2.5 – 10 MHz 2 4
DDCC [3] Bipolar ± 7.5 ± 0.5 – 2 4
CDTA [16] Bipolar ± 3.0 – 30 MHz 2 0
OTRA [10] 0.5 ± 1.5 ± 0.3 8 MHz 1 9
This work 0.18 ± 0.9 ± 0.25 19.3 GHz 1 2

5 Application Examples

5.1 Amplitude Modulator

The proposed four-quadrant analog multiplier can be used as an amplitude mod-

ulator (AM). To verify the operation of the proposed analog multiplier as an
amplitude modulator, a sinusoidal signal of 10  MHz with 100  mV amplitude is
multiplied by 100  mV, 500  MHz sinusoidal carrier signal. Figure  6 shows self-
explanatory modulation function performed. Figure  6 shows the time domain
response of the amplitude modulator and the frequency spectrum.

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Circuits, Systems, and Signal Processing

(a) (b)
Fig. 6  Simulation result of the proposed circuit as amplitude modulator a time domain response, b fre-
quency spectrum

5.2 Squarer

The proposed circuit can be used as an analog squarer circuit by assuming input
signal V1 = V2 = Vin. The input and output signals of the squarer are shown in
Fig.  7a, and the spectrum of the squared output is shown in Fig.  7b, when the
input signal is taken as a 100 mV, 500 MHz sinusoid.

5.3 Frequency Doubler

The proposed four-quadrant multiplier circuit is next used as frequency doubler.

Figure 8 shows that when a 200 mV, 500 MHz sinusoidal signal is used as input
signal, we get a 75  mV, 1  GHz signal at the output. Thus, it is to be concluded
that the proposed circuit can also be used as a frequency doubler.

(a) (b)
Fig. 7  Simulation results of the proposed circuit as a squarer a time response, b frequency spectrum

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 Circuits, Systems, and Signal Processing

(a)

(b)

Fig. 8  Simulation result of the circuit as frequency doubler a input, b output

6 Conclusion

In this work, a single DXCCII-based four-quadrant analog multiplier circuit has

been proposed. CMOS DXCCII is used to realize the new proposed four-quadrant
analog multiplier circuit. The proposed analog multiplier employs only single
DXCCII and two MOS transistors. It provides simpler, hence low-cost solution to
the four-quadrant analog multiplier problem, and shows good performance. It has
been shown through SPICE simulations that the proposed circuit can operate in
range of ± 250 mV and can multiply over the input signal range of ± 250 mV. The
other performance features show the − 3 dB bandwidth of 19.30 GHz and THD
of less than 0.79%. A detailed comparison of the proposed circuit with known
solutions is carried out, which suggest useful knowledge contribution to the sub-
ject. The proposed multiplier is quite suitable for high-speed application such as
variable gain amplifier, adaptive filter, phase locked loops, amplitude modulator,
squarer and frequency doubler. The integration of the proposed circuit is a natural
future problem open for further study.

Acknowledgements  The authors thank anonymous reviewers and the EIC, Prof. MNS Swamy, for rec-
ommending this paper.

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