Experiment 4 22/08/2019

Aim: Design and simulate using WINSPICE a resistive loaded inverter with
RL=1kohm, such that VOL=0.6V. The enhancement type NMOS driver transistor has
following parameters: Vdd=5V, VT0=1V, unCox=22uA/V2. Also observe the effect
of variation of RL on VTC plot and noise margin parameter. Use 1um technology.
Comment about the robustness with respect to VOL parameter of the designed
resistively NMOS inverter design.
Theory:

Circuit diagram:

Codes:
Inverter:

*cmos

.model mynmos NMOS vt=1

vdd s1 0 5

R1 s1 d 1k

M1 d s 0 0 mynmos w=90.1u l=1u

vin s 0 5

.dc vin 0 5 0.01

.control

run

plot v(d) v(s)

.endc

.end
Vary RL:

*cmos

.model mynmos NMOS vt=1

vdd s1 0 5

R1 s1 d1 1k

R2 s1 d2 10k

R3 s1 d3 20k

M1 d1 s 0 0 mynmos w=90.1u l=1u

M2 d2 s 0 0 mynmos w=90.1u l=1u

M3 d3 s 0 0 mynmos w=90.1u l=1u

vin s 0 5

.dc vin 0 5 0.01

.control

run

plot v(d1) v(d2) v(d3) v(s)

.endc

.end
Observations:
Result:
Parameters V(th.) V(prac.)
VIL
VIH
VOL
VOH
Conclusion: