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Stand-Alone CAN Controller With SPI™ Interface: Features Description
Stand-Alone CAN Controller With SPI™ Interface: Features Description
MCP2515
TX0RTS 4 15 SO
• Clock out pin with programmable prescaler:
TX1RTS 5 14 SI
- Can be used as a clock source for other
device(s) TX2RTS 6 13 SCK
• Start-of-Frame (SOF) signal is available for OSC2 7 12 INT
monitoring the SOF signal: 11
OSC1 8 RX0BF
- Can be used for time-slot-based protocols
Vss 9 10 RX1BF
and/or bus diagnostics to detect early bus
degredation
• Interrupt output pin with selectable enables
• Buffer Full output pins configurable as:
- Interrupt output for each receive buffer 20-LEAD TSSOP
- General purpose output
TXCAN 1 20 VDD
• Request-to-Send (RTS) input pins individually RXCAN 2 19 RESET
configurable as: CLKOUT/SOF 3 18 CS
- Control pins to request transmission for each TX0RTS 4 17 SO
MCP2515
RXCAN
CAN TX and RX Buffers SPI™ CS
Protocol Interface SCK SPI
Engine Masks and Filters Logic Bus
SI
TXCAN SO
Control Logic
OSC1
Timing
OSC2
Generation INT
CLKOUT
RX0BF
RX1BF
TX0RTS
Control TX1RTS
and
Interrupt TX2RTS
Registers RESET
TX RX TX RX TX RX
CANH
CANL
MESSAGE
MESSAGE
c Acceptance Filter Acceptance Filter e
TXREQ
TXREQ
TXREQ
TXERR
TXERR
TXERR
e RXF0 RXF4 p
MLOA
MLOA
MLOA
ABTF
ABTF
ABTF
p t
Acceptance Filter Acceptance Filter
t
RXF1 RXF5
R R
M
X Identifier Identifier X
Message A
B B
Queue B
0 1
Control
Transmit Byte Sequencer Data Field Data Field
Transmit ErrPas
Error BusOff
Counter
Transmit<7:0> Receive<7:0>
Shift<14:0>
{Transmit<5:0>, Receive<8:0>}
Comparator
Protocol
Finite SOF
State
CRC<14:0> Machine
Bit
Transmit
Timing Clock
Logic Logic Generator
TX RX
Configuration
Registers
SAM
REC
Sample<2:0> Receive
Error Counter
TEC
StuffReg<5:0>
Transmit
ErrPas
Majority Error Counter
Decision BusOff
BusMon
Comparator
CRC<14:0>
Protocol
FSM SOF
Comparator
Shift<14:0>
(Transmit<5:0>, Receive<7:0>)
Receive<7:0> Transmit<7:0>
RecData<7:0> TrmData<7:0>
Interface to Standard Buffer Rec/Trm Addr.
12 6 8N (0≤N≤8) 16 7
Arbitration Field Control Data Field CRC Field
Field End-of-
4 Frame
STANDARD DATA FRAME
11 8 8 15
CRC
Start-of-Frame
IFS
ACK Del
Ack Slot Bit
CRC Del
DLC3
ID 10
ID3
ID0
DLC0
IDE
RB0
RTR
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Preliminary
Identifier Data
Length
Message Code
Filtering
Reserved Bit
Stored in Transmit/Receive Buffers
Stored in Buffers
Bit-stuffing
DS21801D-page 9
MCP2515
FIGURE 2-2:
DS21801D-page 10
MCP2515
IFS
ACK Del
Ack Slot Bit
ID10
ID3
SRR
IDE
EID17
EID0
RTR
RB1
RB0
DLC3
DLC0
ID0
CRC Del
Start-Of-Frame
0 11 000 1 11111111111
Identifier Data
Extended Identifier
Length
Preliminary
Message Code
Filtering
Reserved bits
Stored in Buffers Stored in Transmit/Receive Buffers
Bit-stuffing
ID10
ID3
SRR
IDE
EID17
EID0
RTR
RB1
RB0
DLC3
DLC0
CRC Del
ID0
Start-Of-Frame
0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Identifier Data
Extended Identifier
Preliminary
Length
Message Code
Filtering Reserved bits
No data field
DS21801D-page 11
MCP2515
FIGURE 2-4:
DS21801D-page 12
MCP2515
12 6 8N (0≤N≤8)
Arbitration Field Control Data Field
Field
4
11 8 8
Start-Of-Frame
DLC3
ID 10
ID3
ID0
DLC0
IDE
RB0
RTR
ACTIVE ERROR FRAME
0 0 0 0
Identifier Data
Length
Message Code
Filtering
Preliminary
Reserved Bit
Error Frame
Bit-stuffing 8
6 £6
Data Frame or
Error Echo Error Inter-Frame Space or
Remote Frame
Flag Error Delimiter Overload Frame
Flag
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
12 6 16 7
Arbitration Field Control CRC Field
Field End-of-
OVERLOAD FRAME
4 Frame
11 15
CRC
Start-Of-Frame
ACK Del
Ack Slot Bit
CRC Del
DLC3
ID 10
ID0
IDE
DLC0
RB0
RTR
0 1 0 0 1 1 1 1 1 1 1 1 1
Overload Frame
Preliminary
End-of-Frame or Inter-Frame Space or
Error Delimiter or 6 8 Error Frame
Overload Delimiter
Overload Overload
Flag Delimiter
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
DS21801D-page 13
MCP2515
MCP2515
NOTES:
Start
The message transmission
sequence begins when the
device determines that the
TXBnCTRL.TXREQ for any of
the transmit registers has been
Are any set.
No TXBnCTRL.TXREQ
bits = 1
?
Yes
Is is
CAN bus available No TXBnCTRL.TXREQ=0 No
to start transmission? or CANCTRL.ABAT=1
?
Yes Yes
Transmit Message
Message
Was No Message error
Error
Message Transmitted or
Successfully? Lost arbitration
? Set
TxBnCTRL.TXERR
Yes Lost
Clear TxBnCTRL.TXREQ Arbitration
Yes
CANINTE.MEERE?
Yes
Generate Set
CANINTE.TXnIE=1? TxBNCTRL.MLOA
Interrupt
No
Generate
Interrupt
No
Set Set
CANTINF.TXnIF CANTINF.MERRF
The CANINTE.TXnIE bit
determines if an interrupt
should be generated when
a message is successfully
transmitted.
GOTO START
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Sample
Point
RXCAN
SOF
Glitch-Filtering
EXPECTED START-OF-FRAME BIT
Expected Sample
Point BUS IDLE
RXCAN
SOF
R R
Identifier M Identifier
X X
A
B B
B
0 1
Start
Detect
No
Start of
Message?
Yes
Valid
Generate No
Error Message
Frame Received?
Yes
Meets Meets
Yes No Yes
a filter criteria a filter criteria
for RXB0? for RXB1?
No
Go to Start
Determines if the receive
register is empty and able
to accept a new message
Is No Is Yes
CANINTF.RX0IF = 0? RXB0CTRL.BUKT = 1?
Yes No
No Is
Move message into RXB0 Generate Overflow Error: Generate Overflow Error: CANINTF.RX1IF = 0?
Set EFLG.RX0OVR Set EFLG.RX1OVR
No No
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Extended Frame
* The two MSb (EID17 and EID16) mask and filter bits are not used.
RXFn0 RXMn0
RXMn1 RxRqst
RXFn1
RXFnn RXMnn
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
SYNCHRONIZATION SEGMENT
The Synchronization Segment (SyncSeg) is the first
segment in the NBT and is used to synchronize the
nodes on the bus. Bit edges are expected to occur
within the SyncSeg. This segment is fixed at 1 TQ.
Sample
Point
Nominal Bit Time (NBT), tbit
tOSC
TBRPCLK
TQ
(tTQ)
Input Signal (e = 0)
PhaseSeg2 (PS2)
SyncSeg PropSeg PhaseSeg1 (PS1)
SJW (PS2)
SJW (PS1)
Sample
Point
Input Signal
(e > 0)
PhaseSeg2 (PS2)
SyncSeg PropSeg PhaseSeg1 (PS1)
SJW (PS2)
SJW (PS1)
Sample
Point
Nominal Bit Time (NBT)
PhaseSeg2 (PS2)
SyncSeg PropSeg PhaseSeg1 (PS1)
SJW (PS2)
SJW (PS1)
Sample
Point
5.5.3 CNF3
The PHSEG2<2:0> bits set the length (in TQ’s) of PS2,
if the CNF2.BTLMODE bit is set to a ‘1’. If the
BTLMODE bit is set to a ‘0’, the PHSEG2<2:0> bits
have no effect.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
RESET
Error-Passive
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
TABLE 7-1: ICOD<2:0> DECODE Note: The MCP2515 wakes up into Listen-only
mode.
ICOD<2:0> Boolean Expression
7.6 Error Interrupt
000 ERR•WAK•TX0•TX1•TX2•RX0•RX1
When the error interrupt is enabled
001 ERR
(CANINTE.ERRIE = 1), an interrupt is generated on
010 ERR•WAK the INT pin if an overflow condition occurs or if the error
state of the transmitter or receiver has changed. The
011 ERR•WAK•TX0 Error Flag (EFLG) register will indicate one of the
100 ERR•WAK•TX0•TX1 following conditions.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
OSC1
C1 To internal logic
XTAL SLEEP
RF(2)
RS(1)
C2 OSC2
Note 1: A series resistor (RS) may be required for AT strip cut crystals.
2: The feedback resistor (RF ), is typically in the range of 2 to 10 MΩ.
Clock from
OSC1
external system
(1)
Open OSC2
Note 1: A resistor to ground may be used to reduce system noise. This may increase system current.
2: Duty cycle restrictions must be observed (see Table 12-2).
OSC1
0.1 mF
XTAL
TABLE 8-1: CAPACITOR SELECTION FOR TABLE 8-2: CAPACITOR SELECTION FOR
CERAMIC RESONATORS CRYSTAL OSCILLATOR
Typical Capacitor Values Used: Typical Capacitor
Osc Crystal Values Tested:
Mode Freq. OSC1 OSC2 Type(1)(4) Freq.(2)
C1 C2
HS 8.0 MHz 27 pF 27 pF
16.0 MHz 22 pF 22 pF HS 4 MHz 27 pF 27 pF
Capacitor values are for design guidance only: 8 MHz 22 pF 22 pF
These capacitors were tested with the resonators 20 MHz 15 pF 15 pF
listed below for basic start-up and operation. These Capacitor values are for design guidance only:
values are not optimized. These capacitors were tested with the crystals listed
Different capacitor values may be required to below for basic start-up and operation. These values
produce acceptable oscillator operation. The user are not optimized.
should test the performance of the oscillator over the Different capacitor values may be required to produce
expected VDD and temperature range for the acceptable oscillator operation. The user should test
application. the performance of the oscillator over the expected
See the notes following Table 8-2 for additional infor- VDD and temperature range for the application.
mation. See the notes following this Table for additional
Resonators Used: information.
4.0 MHz Crystals Used(3):
8.0 MHz 4.0 MHz
16.0 MHz 8.0 MHz
20.0 MHz
VDD VDD
D(1) R
R1(2)
RESET
Note 1: The diode D helps discharge the capacitor quickly when VDD powers down.
2: R1 = 1 kΩ to 10 kΩ will limit any current flowing into RESET from external
capacitor C, in the event of RESET pin breakdown due to Electrostatic
Discharge (ESD) or Electrical Overstress (EOS).
10.2 Sleep Mode Listen-only mode provides a means for the MCP2515
to receive all messages (including messages with
The MCP2515 has an internal Sleep mode that is used errors) by configuring the RXBnCTRL.RXM<1:0> bits.
to minimize the current consumption of the device. The This mode can be used for bus monitor applications or
SPI interface remains active for reading even when the for detecting the baud rate in ‘hot plugging’ situations.
MCP2515 is in Sleep mode, allowing access to all For auto-baud detection, it is necessary that there are
registers. at least two other nodes that are communicating with
To enter Sleep mode, the mode request bits are set in each other. The baud rate can be detected empirically
the CANCTRL register (REQOP<2:0>). The by testing different values until valid messages are
CANSTAT.OPMODE bits indicate operation mode. received.
These bits should be read after sending the sleep Listen-only mode is a silent mode, meaning no
command to the MCP2515. The MCP2515 is active messages will be transmitted while in this mode
and has not yet entered Sleep mode until these bits (including error flags or acknowledge signals). The
indicate that Sleep mode has been entered. filters and masks can be used to allow only particular
When in internal Sleep mode, the wake-up interrupt is messages to be loaded into the receive registers, or the
still active (if enabled). This is done so that the MCU masks can be set to all zeros to allow a message with
can also be placed into a Sleep mode and use the any identifier to pass. The error counters are reset and
MCP2515 to wake it up upon detecting activity on the deactivated in this state. The Listen-only mode is
bus. activated by setting the mode request bits in the
CANCTRL register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Mask byte 0 0 1 1 0 1 0 1
12.10 Bit Modify Instruction
The Bit Modify instruction provides a means for setting
or clearing individual bits in specific status and control Data byte X X 1 0 X 0 X 1
registers. This command is not available for all
registers. See Section 11.0 “Register Map” to
Previous
determine which registers allow the use of this
Register 0 1 0 1 0 0 0 1
command. Contents
Note: Executing the Bit Modify command on
Resulting
registers that are not bit-modifiable will Register 0 1 1 0 0 0 0 1
force the mask to FFh. This will allow byte- Contents
writes to the registers, not bit modify.
Read Status 1010 0000 Quick polling command that reads several status bits for transmit
and receive functions.
RX Status 1011 0000 Quick polling command that indicates filter match and message
type (standard, extended and/or remote) of received message.
Bit Modify 0000 0101 Allows the user to set or clear individual bits in a particular
register. Note: Not all registers can be bit-modified with this
command. Executing this command on registers that are not bit-
modifiable will force the mask to FFh. See the register map in
Section 11.0 “Register Map” for a list of the registers that apply.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI 0 0 0 0 0 0 1 1 A7 6 5 4 3 2 1 A0 don’t care
data out
high-impedance
SO 7 6 5 4 3 2 1 0
CS
n m Address Points to Address
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI 0 0 0 0 0 0 1 0 A7 6 5 4 3 2 1 A0 7 6 5 4 3 2 1 0
high-impedance
SO
CS
0 1 2 3 4 5 6 7
SCK
instruction
SI 1 0 0 0 0 T2 T1 T0
high-impedance
SO
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI 0 0 0 0 0 1 0 1 A7 6 5 4 3 2 1 A0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
high-impedance
SO
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
instruction
SI 1 0 1 0 0 0 0 0 don’t care
repeat
data out data out
high-impedance
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
CANINTF.RX0IF
CANINTFL.RX1IF
TXB0CNTRL.TXREQ
CANINTF.TX0IF
TXB1CNTRL.TXREQ
CANINTF.TX1IF
TXB2CNTRL.TXREQ
CANINTF.TX2IF
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
instruction
SI 1 0 1 1 0 0 0 0 don’t care
repeat
data out data out
high-impedance
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
3
CS
11
1 6 10
Mode 1,1 7 2
SCK Mode 0,0
4 5
SI
MSB in LSB in
SO high-impedance
CS
2
8 9
SCK Mode 1,1
Mode 0,0
12
14
13
SO MSB out LSB out
don’t care
SI
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Param.
No. Sym Characteristic Min Max Units Conditions
VOH TXCAN, RXnBF Pins VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V
OSC1 Pin -5 +5 µA
IDDS Standby Current (Sleep mode) — 5 µA CS, TXnRTS = VDD, Inputs tied to
VDD or VSS, -40°C TO +85°C
16
RXCAN sample point
15
Param.
Sym Characteristic Min Max Units Conditions
No.
XXXXXXXXXXXXXXXXX e3
MCP2515-I/P^^
XXXXXXXXXXXXXXXXX
YYWWNNN 0434256
XXXXXXXXXXXX MCP2515
XXXXXXXXXXXX e3
E/SO^^
XXXXXXXXXXXX
YYWWNNN 0434256
XXXXXXXX MCP2515
XXXXXNNN IST e^3 256
YYWW 0434
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
E1
n 1 α
E A2
c L
A1
B1
β
B p
eB
E
p
E1
2
B n 1
h
α
45°
c
A A2
φ
β L A1
p E1
D
B
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n 1
α
A
φ
A2
β
L A1
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
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• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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03/01/05