SOLAR TRACKING SYSTEM

1.1 INTRODUCTION

Renewable energy is rapidly gaining importance as an energy resource as fossil fuel

prices fluctuate. One of the most popular renewable energy sources is solar energy. Solar
tracking enables more energy to be generated because the solar panel is able to maintain
a perpendicular profile to the sun’s rays.
There are three ways to increase the efficiency of a photovoltaic (PV) system.
1) The first is to increase the efficiency of the solar cell.
2) The second is to maximize the energy conversion from the solar panel.
A solar panel under an open circuit is able to supply a maximum voltage with no
current, while under a short circuit is able to supply a maximum current with no voltage.
In either case, the amount of power supplied by the solar panel is zero. The key is to
develop a method whereby maximum power can be obtained from the voltage and
current multiplied together.

1.2 PROBLEM DEFINITION

In years to come the need for energy will increase manifold while the reserve of
conventional energy will deplete in rapid pace. To meet the growing demand of energy
harnessing of non-conventional / renewable energy is the necessity. Among all the
available non-conventional sources, solar energy is the most abandunt and uniformly
distributed. Though the technology of trapping the solar energy is in existence the
process can be in proved to increase efficiency and make it cost-effective.

1.3 MOTIVATION

Renewable energy is rapidly gaining importance as an energy resource as fossil fuel

prices fluctuate. One of the most popular renewable energy sources is solar energy.
Many researches were conducted to develop some methods to increase the efficiency of
Photo Voltaic systems (solar panels). One such method is to employ a solar panel
tracking system .This project deals with a microcontroller based solar panel tracking
system. Solar tracking enables more energy to be generated because the solar panel is
always able to maintain a perpendicular profile to the sun’s rays.
Development of solar panel tracking systems has been ongoing for several years now.
As the sun moves across the sky during the day, it is advantageous to have the solar
panels track the location of the sun, such that the panels are always perpendicular to the
solar energy radiated by the sun. This will tend to maximize the amount of power
absorbed by PV systems. It has been estimated that the use of a tracking system, over a
fixed system, can increase the power output by 30% - 60%. The increase is significant
enough to make tracking a viable preposition despite of the enhancement in system cost.
It is possible to align the tracking heliostat normal to sun using electronic control by a
micro controller.

1.4 System Design

Design requirements:
1) Must track the sun during daylight hours
 During the time that the sun is up, the system must follow the sun’s position in
the sky.
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  This must be done with an active control.
 A base must be designed to allow installation without fasteners onto a flat section
of roof
2) Weather resistant
 This system will be designed to be fully functional outdoors and resist any wind
and weather complications.
3) Remote instrumentation to monitor status
 A method will be implemented to allow the system to be monitored remotely.
The major components of this system are as follows. Each component required
the student to make decisions that would ultimately affect the final design, based
on both technical as well as financial constraints.
4) The solar panel that will convert the radiation of the sun into electricity
 The solar panel in direct sunlight is capable of sourcing 23V under open circuit
conditions, and approximately 0.75A under short circuit conditions. The solar
panel used in this project was already available and therefore did not cost any
money towards the project.
5) A base to support the solar panel
 The base must be able to mount with no fasteners on a flat roof. It must also be
large enough and heavy enough to provide a solid mounting point that will
prevent the system from being damaged by strong winds.
6) A weather-resistant housing to protect the electronics
 The final control box had two parts (bottom and top). The interface between the
two included a gasketed design for water-resistance.
7) A motor to move the solar panel as the sun traverses through the sky
 The intent of the project was to automatically rotate the solar panel to orient the
panel perpendicular to the sun’s rays.
8) Electronics to sense the sun’s position, and determine whether the solar panel needs
to move
 The approach employed to orient the panel with the sun was to find the point that
maximized the amount of power being converted by the panel. Current was
measured through a fixed resistance to determine the power consumed.
 An 8051 microcontroller would be the brains of the operation, sensing which
position of the panel yielded maximum power, and sending signals to the
antenna motor to move the solar panel accordingly.

1.5 METHEDOLOGY
This project is designed with solar panels, LDR, ADC, Microcontroller, Stepper
Motor and its driving circuit.
In this project three LDRs are fixed on the solar panel at three distinct points. LDR
(Light Dependant Resistor) varies the resistance depending upon the light fall. The
varied resistance is converted into an analog voltage signal.
The analog voltage signal is then fed to an ADC. ADC is nothing but analog to digital
converter which receives the two LDR voltage signals and converts them to
corresponding digital signal. Then the converted digital signal is given as the input of the
microcontroller. Microcontroller receives the two digital signals from the ADC and
compares them. The LDR signals are not equal except for normal incidence of sunlight.
When there is a difference between LDR voltage levels the microcontroller programme
drives the stepper motor towards normal incidence of sunlight.

1.6 BLOCK DIAGRAM:

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 Fig 2.1 : General Block diagram of the Tracking system.

Fig 2.1 shows the general block diagram of the tracking system.

In this system the sun's light is tracked in order to generate power very
effectively. For that purpose 3 LDR’s are used for sensing the light from the sun. Here 3
LDR’s are used so that the sun's path can be divided into 3 columns of 180° (East-West).
The LDR outputs have been compared and the sun’s angle is traced. Hence the solar
panel is moved towards the sun’s angle with the help of microcontroller by using stepper
motor. In this operation the signal from the light sensor is given to the signal conversion
circuit and then it is filtered before passing into the microcontroller.

INTRODUCTION TO MICROCONTROLLER ARCHITECTURE

2.1 INTRODUCTION
A microcontroller (or MCU) is a computer-on-a-chip used to control electronic
devices. It is a type of microprocessor emphasizing self-sufficiency and cost-
effectiveness, in contrast to a general-purpose microprocessor (the kind used in a PC). A
typical microcontroller contains all the memory and interfaces needed for a simple
application, whereas a general purpose microprocessor requires additional chips to
provide these functions. A highly integrated chip that contains all the components
comprising a controller . Typically this includes a CPU, RAM, some form of ROM, I/O
ports, and timers. Unlike a general-purpose computer, which also includes all of these
components, a microcontroller is designed for a very specific task – to control a
particular system. As a result, the parts can be simplified and reduced, which cuts down
on production costs.

2.2 Microcontroller Applications

The microcontroller applications are mainly categorized into the following types:
 Audio
 Automotive
 Communication/wired
 Computers and peripherals
 Consumer
 Industrial
 Imaging and video
 Medical
 Military/aerospace
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 Mobile/wireless
 Motor control
 Security
 General Purpose
 Miscellaneous
Automobile industry is the main driving force in propelling the growth of
microcontrollers. The 8- and 16-bit microcontrollers are used for low-end applications
and lower-cost vehicles while the 32-bit microcontrollers are used for high-end
application and high-end vehicles.
2.3 AT89S8252 CONTROLLER
2.3.1 Features
o 8K Bytes of In-System Reprogrammable Downloadable Flash Memory
 SPI Serial Interface for Program Downloading
 Endurance: 1,000 Write/Erase Cycles
o 2K Bytes EEPROM – Endurance: 100,000 Write/Erase Cycles
o 4V to 6V Operating Range
o Fully Static Operation: 0 Hz to 24 MHz
o Three-level Program Memory Lock
o 256 x 8-bit Internal RAM
o 32 Programmable I/O Lines
o Three 16-bit Timer/Counters
o Nine Interrupt Sources
o Programmable UART Serial Channel
o SPI Serial Interface
o Low-power Idle and Power-down Modes
o Interrupt Recovery from Power-down
o Programmable Watchdog Timer
o Dual Data Pointer
o Power-off Flag
2.3.2 Description
The AT89S8252 is a low-power, high-performance CMOS 8-bit microcontroller with
8K bytes of downloadable Flash programmable and erasable read-only memory and 2K
bytes of EEPROM. The device is manufactured using Atmel’s high-density non-
volatile memory technology and is compatible with the industry-standard 80C51
instruction set and pinot. The on-chip downloadable Flash allows the program memory
to be reprogrammed In-System through an SPI serial interface or by a conventional
non-volatile memory programmer. By combining a versatile 8-bit CPU with
downloadable Flash on a monolithic chip, the Atmel AT89S8252 is a powerful
microcontroller, which provides a highly-flexible and cost-effective solution to many
embedded control applications.
The AT89S8252 provides the following standard features:
 8K bytes of downloadable Flash,
 2K bytes of EEPROM,
 256 bytes of RAM,
 32 I/O lines,
 programmable watchdog timer,
 two data pointers,
 three 16-bit timer/counters,
 six-vector two-level interrupt architecture,
 a full duplex serial port,
 On-chip oscillator and clock circuitry.
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 In addition, the AT89S8252 is designed with static logic for operation down to zero
frequency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt
system to continue functioning. The Power-down mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions until the next external interrupt
or hardware reset. The downloadable Flash can be changed a single byte at a time and
is accessible through the SPI serial interface. Holding RESET active forces the SPI bus
into a serial programming interface and allows the program memory to be written to or
read from unless lock bits have been activated.
2.3.4 BLOCK DIAGRAM

2.3.5 Pin Configurations

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 Fig 2.1: Pin out of AT89S8252
2.3.6 Pin Description

Port 0
Port 0 is an 8-bit open drain bi-bidirectional I/O port. As an output port, each pin can
sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high
impedance inputs. Port 0 can also be configured to be the multiplexed low-order
address/data bus during accesses to external program and data memory. In this mode,
P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming
and outputs the code bytes during program verification. External pull-ups are required
during program verification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output
buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are
pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins
that are externally being pulled low will source current (IIL) because of the internal
pull-ups.
Some Port 1 pins provide additional functions. P1.0 and P1.1 can be configured to be
the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input
(P1.1/T2EX), respectively. Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured
as the SPI slave port select, data input/output and shift clock input/output pins as shown
in the following table. Port 1 also receives the low-order address bytes during Flash
programming and verification.

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Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output
buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are
pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins
that are externally being pulled low will source current (IIL) because of the internal
pull-ups.
Port 2 emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that uses 16-bit addresses
(MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when
emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX
@ RI), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during
Flash programming and verification.

Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output
buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are
pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins
that are externally being pulled low will source current (IIL) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification. Port 3
also serves the functions of various special features of the AT89S8252, as shown in the
following table.

RST
Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device.
ALE/PROG
Address Latch Enable is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during
Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency
and may be used for external timing or clocking purposes. Note, however, that one
ALE pulse is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With
the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the
pin is weakly pulled high. Setting the ALE-disable bit has no effect if the
microcontroller is in external execution mode.
PSEN
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 Program Store Enable is the read strobe to external program memory. When the
AT89S8252 is executing code from external program memory, PSEN is acti-vated
twice each machine cycle, except that two PSEN activations are skipped during each
access to external data memory.

EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions. This pin also receives
the 12-volt programming enable voltage (VPP) during Flash programming when 12-
volt pro-gramming is selected.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.
XTAL2
Output from the inverting oscillator amplifier .

2.3.7 SPECIAL FUNCTION REGISTERS

A map of the on-chip memory area called the Special Function Register (SFR) space is
shown in Table 2.

Table 2: AT89S8252 SFR Map and Reset Values

Timer 2 Registers Control and status bits are contained in registers T2CON (shown in
Table 3) and T2MOD (shown in Table 9) for Timer 2. The register pair (RCAP2H,

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RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit
auto-reload mode.

Table 3: TCON – Timer/Counter 2 Control Register

Watchdog and Memory Control Register

The WMCON register contains control bits for the Watchdog Timer (shown in Table
4). The EEMEN and EEMWE bits are used to select the 2K bytes on-chip EEPROM,
and to enable byte-write. The DPS bit selects one of two DPTR registers available.

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 Table 4: WMCON—Watchdog and Memory Control Register
SPI Registers Control and status bits for the Serial Peripheral Interface are contained in
registers SPCR and SPSR . The SPI data bits are contained in the SPDR register.
Writing the SPI data register during serial data transfer sets the Write Collision bit,
WCOL, in the SPSR register. The SPDR is double buffered for writing and the values
in SPDR are not changed by Reset.
Interrupt Registers The global interrupt enable bit and the individual interrupt enable
bits are in the IE register. In addition, the individual interrupt enable bit for the SPI is in
the SPCR register. Two priorities can be set for each of the six interrupt sources in the
IP register.
Dual Data Pointer Registers To facilitate accessing both internal EEPROM and exter-
nal data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR
address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR WMCON selects
DP0 and DPS = 1 selects DP1. The user should ALWAYS initialize the DPS bit to the
appropriate value before accessing the respective Data Pointer Register.
Power Off Flag The Power Off Flag (POF) is located at bit_4 (PCON.4) in the PCON
SFR. POF is set to “1” during power up. It can be set and reset under software control
and is not affected by RESET.
Interrupts
The AT89S8252 has a total of six interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 2.2.

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 Table 5: Interrupt Enable (IE) Register
Each of these interrupt sources can be individually enabled or disabled by setting or
clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA,
which disables all interrupts at once.
Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89C51, bit
position IE.5 is also unimplemented. User software should not write 1s to these bit
positions, since they may be used in future AT89 products.

Fig 2.2: Interrupt Sources

2.4 THE 8051 INSTRUCTION SET
The 8051 instruction set is optimized for 8-bit control applications. It provides a
variety of fast addressing modes for accessing the internal RAM to facilitate byte
operations on small data structures. The instruction set provides extensive support
for one-bit variables as a separate data type, allowing direct bit manipulation in
control and logic systems that require Boolean processing.

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 Data’s are stored in source address and moved to destination addresses. The ways
by which data’s are represented are addressing modes.

There are four types of addressing modes used to access the data, namely
1. Immediate addressing mode
2. Direct addressing mode
3. Register addressing mode
4. Indirect addressing mode

The syntax used to access the data from source to destination is

“Opcode destination, source”
Where, opcode = any instruction such as mov, add, subb etc.
Destination = address to which data has to be copied.
Source = address from which data has been copied.

2.4.1 ADDRESSINS MODE:

1. Immediate addressing mode:
In this addressing mode source operand is constant. In immediate addressing
mode, when the instruction is assembled the operand comes immediately after the
opcode and data must be preceded by the pound (#) sign.

When 8051 executes the immediate data move, the program counter is
automatically incremented to point to the byte following the opcode byte in the
program memory. Whatever the data found there is copied to the destination.

Eg: MOV A, #n ; where n can take any hexadecimal values.

MOV A,#25H ; here n=25h
MOV R3, #62H ; this loads 62 to register R3.

This addressing mode can also be used to load the information to data pointer
register (DPTR).
Although DPTR is a 16bit register it can be accessed as a two 8 bit registers
namely DPL &DPH.

Eg: MOV DPTR, #1234H ; this copy the immediate data 1234h to DPTR.
MOV DPL, #34H ; this copy the immediate data 34h to the lower
byte .
MOV DPH, #45H ; this copy the immediate data 45h to the upper byte

2. Register addressing mode:

This mode involves the registers to hold data to be manipulated. The limitation of
this addressing mode is that the source and the destination register must match in
size.

Eg: MOV A, R4 ; this copies the content of R4 to A.

ADD A, R5 ; this adds the contents of A with contents of R5.

3. DIRECT and INDIRECT ADDRESSING MODES

These addressing modes are used for accessing memories. As we know that 8051
has 128 bytes of RAM with the memory ranging from 00 to 7Fh. The following is
the summary of the allocation of these 128 bytes.
1. RAM location 00 to 1Fh is assigned to register bank and stack.
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 2. RAM location 20 to 2Fh is set as bit addressable space to save single bit data.
3. RAM location 30 to 7F is available to save byte size data.

4. DIRECT ADDRESSING MODE

In this addressing mode the data is in a RAM memory location whose address is
known and this memory address is given as a part of the instruction to access the
data stored in that memory address.

Eg: MOV R0, 49H ; this saves the content of RAM location 40h in R0
MOV 23H, R4 ; saves the content of R4 in RAM location 23h.

5. INDIRECT ADDRESSING MODE

In this mode a register is used as a pointer to data rather than register. If the data
is inside the CPU, only register R0 and R1 are used for this purpose otherwise R2
to R7 are used. When R0 and R1 are used as pointers they are called data
pointers. That is when they hold the address of RAM location they must be
preceded by “@”sign.
Eg: MOV A, @R0 ; this moves the content of RAM location whose address is
held in R into A.
MOV @R1, B ; moves the content of B into RAM location whose
address is held by R1.
One advantage of register indirect addressing mode is that it makes accessing data
dynamically rather than static as in case of direct addressing mode. Also looping
can be possible in indirect addressing mode. Where as it is not possible in direct
addressing mode.
2.4.2 Arithmetic Instructions.
The menu of arithmetic instructions is listed in Table 2.1. The table indicates the
addressing modes that can be used with each instruction to access the <byte>
operand.
For example, the ADD A, <byte> instruction can be written as:
ADD A,7FH (direct addressing)
ADD A,@ R0(indirect addressing)
ADD A,R7 (register addressing)
ADD A,# 127(immediate constant)

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 Table 2.1: A list of the Atmel 8051 Arithmetic Instructions.

2.4.3 Logical Instructions

Table 2.2 shows the list of logical instructions. The instructions that perform
Boolean operations (AND, OR, Exclusive OR, NOT) on bytes perform the
operation on a bit-by bit basis. That is, if the Accumulator contains 00110101B
and <byte> contains 01010011B, then
ANL A,<byte> will leave the Accumulator holding 00010001B.
The addressing modes that can be used to access the <byte> operand are listed in
Table 2.2. Thus, the ANL A, <byte> instruction may take any of the following
forms.
ANL A, 7FH(direct addressing)
ANL A, @ R1(indirect addressing)
ANL A, R6(register addressing)
ANL A, # 53H(immediate constant)

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 Table 2.2: A list of the Atmel 8051 Logical Instructions
2.4.4 Data Transfers
Table 2.3 shows the menu of instructions that are available for moving data
around within the internal memory spaces, and the addressing modes that can be
used with each one. With a 12 MHz clock and X1 mode, all of these instructions
execute in either1 or 2 μs.
The MOV <dest>, <src> instruction allows data to be transferred between any
two internal RAM or SFR locations without going through the Accumulator.
Remember the Upper 128 bytes of data RAM can be accessed only by indirect, and
SFR space only by direct
addressing. Note that in all 8051 devices, the stack resides in on-chip RAM, and
grows upwards.
The PUSH instruction first increments the Stack Pointer (SP), then copies the
byte into the stack. PUSH and POP use only direct addressing to identify the byte
being saved or restored, but the stack itself is accessed by indirect addressing using
the SP register.

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 Table 2.3: Atmel 8051 Data Transfer Instructions that Access Internal Data
Memory Space.
STEPPER MOTOR

3.1 INTRODUCTION
A stepper motor is an electromechanical device which converts electrical pulses into
discrete mechanical movements. The shaft or spindle of a stepper motor rotates in
discrete step increments when electrical command pulses are applied to it in the proper
sequence. The motors rotation has several direct relationships to these applied input
pulses. The sequence of the applied pulses is directly related to the direction of motor
shafts rotation. The speed of the motor shafts rotation is directly related to the
frequency of the input pulses and the length of rotation is directly related to the number
of input pulses applied.

3.2 Advantages and Disadvantages

Advantages
1. The rotation angle of the motor is proportional to the input pulse.
2. The motor has full torque at standstill (if the windings are energized)
3. Precise positioning and repeatability of movement since good stepper motors have
accuracy of 3 – 5% of a step and this error is non cumulative from one step to the
next.
4. Excellent response to starting/ stopping/reversing.
5. Very reliable since there are no contact brushes in the motor. Therefore the life of the
motor is simply dependant on the life of the bearing.
6 .The motors response to digital input pulses provides open-loop control, making the
motor simpler and less costly to control.
7. It is possible to achieve very low speed synchronous rotation with a load that is
directly coupled to the shaft.
8. A wide range of rotational speeds can be realized as the speed is proportional to the
frequency of the input pulses.

Disadvantages
1. Resonances can occur if not properly controlled.
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 2. Not easy to operate at extremely high speeds.

Open Loop Operation

One of the most significant advantages of a stepper motor is its ability to be accurately
controlled in an open loop system. Open loop control means no feedback information
about position is needed. This type of control eliminates the need for expensive sensing
and feedback devices such as optical encoders. Your position is known simply by
keeping track of the input step pulses.

3.3 Stepper Motor Types

There are three basic stepper motor types. They are:
 Variable-reluctance
 Permanent-magnet
 Hybrid

1) Variable-reluctance (VR)
This type of stepper motor has been around for a long time. It is probably the easiest
to understand from a structural point of view. Figure 3.1 shows a cross section of a
typical V.R. stepper motor. This type of motor consists of a soft iron multi-toothed
rotor and a wound stator. When the stator windings are energized with DC current
the poles become magnetized. Rotation occurs when the rotor teeth are attracted to
the energized stator poles.

Fig3.1. Cross-section of a variable reluctance

(VR) motor

2) Permanent Magnet (PM)

Often referred to as a “tin can” or “can stock” motor the permanent magnet step
motor is a low cost and low resolution type motor with typical step angles of 7.5° to
15°. (48 – 2 steps/revolution) PM motors as the name implies have permanent
magnets added to the motor structure. The rotor no longer has teeth as with the VR
motor. Instead the rotor is magnetized with alternating north and south poles situated
in a straight line parallel to the rotor shaft. These magnetized rotor poles provide an
increased magnetic flux intensity and because of this the PM motor exhibits
improved torque characteristics when compared with the VR type.
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 Fig 3.2: Principle of a PM or tin-can
Stepper motor .
3) Hybrid (HB)
The hybrid stepper motor is more expensive than the PM stepper motor but provides
better performance with respect to step resolution, torque and speed. Typical step
angles for the HB stepper motor range from 3.6° to 0.9° (100 – 400 steps per
revolution). The hybrid stepper motor combines the best features of both the PM and
VR type stepper motors. The rotor is multi-toothed like the VR motor and contains a
axially magnetized concentric magnet around its shaft. The teeth on the rotor
provide an even better path which helps guide the magnetic flux to preferred
locations in the airgap. This further increases the detent, holding and dynamic torque
characteristics of the motor when compared with both the VR and PM types.

Fig 3.3: Cross-section of a hybrid stepper

motor.
The two most commonly used types of stepper motors are the permanent
magnet and the hybrid types. If a designer is not sure which type will best fit his
applications requirements he should first evaluate the PM type as it is normally
several times less expensive. If not then the hybrid motor may be the right choice.
There also excist some special stepper motor designs. One is the disc magnet
motor. Here the rotor is designed sa a disc with rare earth magnets, See fig. 3.4. This
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 motor type has some advantages such as very low inertia and a optimized magnetic
flow path with no coupling between the two stator windings. These qualities are
essential in some applications.

Fig 3.4: Magnetic flux path through a

Two-pole stepper motor with a lag between
the rotor and stator.
3.4 Size and Power
In addition to being classified by their step angle stepper motors are also
classified according to frame sizes which correspond to the diameter of the body of
the motor. For instance a size 11 stepper motor has a body diameter of approximately
1.1 inches. Likewise a size 23 stepper motor has a body diameter of 2.3 inches (58
mm), etc. The body length may however, vary from motor to motor within the same
frame size classification. As a general rule the available torque output from a motor of
a particular frame size will increase with increased body length.
3.5 When to Use a Stepper Motor
A stepper motor can be a good choice whenever controlled movement is required.
They can be used to advantage in applications where you need to control rotation
angle, speed, position and synchronism. Because of the inherent advantages listed
previously, stepper motors have found their place in many different applications.
Some of these include printers, plotters, high end office equipment, hard disk drives,
medical equipment, fax machines, automotive and many more.
3.6 The Rotating Magnetic Field
When a phase winding of a stepper motor is energized with current a magnetic
flux is developed in the stator. The direction of this flux is determined by the “Right
Hand Rule” which states: “If the coil is grasped in the right hand with the fingers
pointing in the direction of the current in the winding (the thumb is extended at a 90°
angle to the fingers), then the thumb will point in the direction of the magnetic field.”

3.7 Phases, Poles and Stepping Angles

Usually stepper motors have two phases, but three- and five-phase motors also exist.
A bipolar motor with two phases has one winding/phase and a unipolar motor has one
winding, with a center tap per phase. Sometimes the unipolar stepper motor is referred
to as a “fourphase motor”, even though it only has two phases.
In reality several more poles are added to both the rotor and stator structure in order to
increase the number of steps per revolution of the motor, or in other words to provide
a smaller basic (full step) stepping angle. The permanent magnet stepper motor
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 contains an equal number of rotor and stator pole pairs. Typically the PM motor has
12 pole pairs. The stator has 12 pole pairs per phase. The hybrid type stepper motor
has a rotor with teeth. The rotor is split into two parts, separated by a permanent
magnet—making half of the teeth south poles and half north poles. The number of
pole pairs is equal to the number of teeth on one of the rotor halves. The stator of a
hybrid motor also has teeth to build up a higher number of equivalent poles (smaller
pole pitch, number of equivalent poles = 360/teeth pitch) compared to the main poles,
on which the winding coils are wound. Usually 4 main poles are used for 3.6 hybrids
and 8 for 1.8- and 0.9-degree types. It is the relationship between the number of rotor
poles and the equivalent stator poles, and the number the number of phases tha
determines the full-step angle of a stepper motor.
Step angle=360 ¸ (NPh ´ Ph)=360/N
NPh = Number of equivalent poles per phase = number of rotor poles
Ph = Number of phases
N = Total number of poles for all phases together
If the rotor and stator tooth pitch is unequal, a more-complicated relationship exists.
3.8 Stepping Modes
The following are the most common drive modes.
• Wave Drive (1 phase on)
• Full Step Drive (2 phases on)
• Half Step Drive (1 & 2 phases on)
Micro stepping (Continuously varying motor currents) For the following
discussions please refer to the figure 3.5. In Wave Drive only one winding is
energized at any given time. The stator is energized according to the sequence A ® B
® A ® B and the
rotor steps from position 8 ® 2 ® 4 ® 6.

Half Step Drive combines both wave and full step (1&2 phases on) drive
modes. Every second step only one phase is energized and during the other steps one
phase on each stator. The stator is energized according to the sequence AB ® B ® AB
® A ® AB ® B ® AB ® A and the rotor steps from position 1 ® 2 ® 3 ® 4 ® 5 ® 6
® 7 8. This results in angular movements that are half of those in 1- or 2-phases-on
drive modes. Half stepping can reduce a phenomena referred to as resonance which
can be experienced in 1- or 2- phases-on drive modes.

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 Fig 3.5: Unipolar and bipolar wound
stepper motors.
The excitation sequences for the above drive modes are summarized in Table 3.1.In
Micro-stepping Drive the currents in the windings are continuously varying to be able
to break up one full step into many smaller discrete steps. More information on micro-
stepping can be found in the micro-stepping chapter.

Table 3.1: Excitation sequences for different drive modes

3.9 Step Angle Accuracy
One reason why the stepper motor has achieved such popularity as a positioning
device in its accuracy and repeatability . Typically stepper motors will have a step
angle accuracy of 3 – 5% of one step. This error is also noncumulative from step to
step. The accuracy of the stepper motor is mainly a function of the mechanical
precision of its parts and assembly.

Step Position Error

The maximum positive or negative position error caused when the motor has rotated
one step from the previous holding position.
Step position error = measured stepangle - theoretical angle
Positional Error
The motor is stepped N times from an initial position (N = 360°/step angle and the
angle from the initial position is measured at each step position. If the angle from the
initial position to the N-step position is QN and the error is DQN where:
DQN = DQN - (step angle) ´ N.
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 The positional error is the difference of the maximum and minimum but isusually
expressed with a ± sign. That is:
positional error = ±1⁄2(DQMax - DQMin)
Hysteresis Positional Error
The values obtained from the measurement of positional errors in both directions.

ANALOG TO DIGITAL CONVERTERS

Successive Approximation ADC (0809) & Programmable Timer test
interface
The timer is divided into two parts
a) One part allows a user to study the technique involved in interfacing a successive
approximation ADC like the industry standard ADC 0809 from national
semiconductors. This contains an eight channel multiplexer and can directly interface
up to eight analog inputs in the range 0 to 5V.
b) The second part provides the hardware to assist the user in studying the
characteristics of a programmable timer (8253) that is on the SDA 86 trainers.
Provision has been made to interface to only one of the three 16 bit timers available in
the 8253 as their operation is identical.

DESCRIPTION
The ADC interface consists of a NOR gate crystal oscillator, a CMOS clock divider which
feeds 768kHz as the input clock to the ADC regulator (723) to connect the +12V to +5V
required by the IC, a stable voltage reference (LM 336) and buffer (which provides the 5V
A multi-turn cermet adjustment of the reference voltage. The channel selects, ALE, start
conversion and out enable lines are interfaced through port lines (connect a flat cable from
the PPI-8255 connector on the trainer to the connector CI in the interface).
Port lines Description
PA0-PA7 Connected data lines D0-D7
PB0 Channel select line A
PB1 Channel select line B
PB2 Channel select line C
*PB5 Ale to latch address
*PB6 Start conversion
*PB7 Input enable
PC0 End of conversion signal

Note – Since PB5,PB6 & PB7 are inverted, the signal at the output of the port lines will be
the complement of the signals required by the IC.
2.2 A conversion can be done in the Polled mode or Interrupt mode
2.2.1 In the Polled mode
1) Program the 8255 to mode zero, control byte’99’.
2) Do a dummy read to clear the f/f output pin status.
3) Setup the address of the channel required to be converted (the 10 ways reliamate
provides a means of applying voltages to the IC).
CAUTION: Ensure that the interface is always provided with +5 volts & +12 volts i.e.,
the interface should not have its power removed while being connected to an active
signal.
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 4) Toggle the ALE at the port output from 1 to 0 and back to 1.
5) Toggle the STRT the port output from 1 to 0 and back to 1.
6) Monitor the f/f output at C1/5- port; line PCO- when it goes to zero conversion is
completed.
7) Read the converted value at port A- the process of reading clears the pending
status.

2.2.2 In the interrupt mode

1) 1 of reliamate (two-way) connector to an interrupt input line in the 85m or 86
trainer (e.g. Pin /34 of the 50 pins bus expansion connector in the 85m which to the
RST6.5 interrupt line).
2) Repeat steps 1 to 5 in section 2.2.1 above.
3) Wait for an interrupt.
4) Read port A in the interrupt routine.
2.2.3 Short J1 to J2 if the INTR interrupt is to be used.
2.2.4 A sample program showing conversion in the polled mode is enclosed.
2.3 The programmable timer test interface consists of an astable multivibrator (using NE
555) that can be used as clock input to the 8253, a key input that can be connected gate
input and two way reliamate that can extend the output of the 82532 for interrupt
purposes. The gate, clock and out lines are terminated parallely in a 6-way reliamate
connector for connection to external signals.
2.4 This interface connects to the SDA 85 M at connector P2 and to the SDA86 at
connector CN2. Take care to see that pin 1’s is properly aligned.
2.4.1 When using the 85M trainers make the following jumper connections in the interface
J12 to J13 ;
J14 to J15 ; OUT 2 is used
J18 to J19 ; GATE 2 is used
J21 to J22 ; CLK 2 is used
J5 to J6 ; if the stable output is used as clock input
J7 to J8 ; for high frequency
J7 to J10 ; for low frequency
J3 to J4 ; for gate input control
2.4.2 When using 86 Trainer make the following connections
J11 to J12 ; GND to the signal connector
J16 to J15 ; OUT 1 is used
J19 to J20 ; GATE 1 is used

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 J22 to J23 ; CLK 1 is used
J1 to J2 ; for interrupt function (OUT 1 is inverted and
; connected to C 2/9, an interrupt pin in
J5 to J6 ; for local astable clock and
J7 to J8 ; high or low frequency
J7 to J10 ;
2.4.3 A small program enclosed shows the interface is used with an 85 M trainer
A flat cable is used to connect the interface .The connectors C1 & C2 in the interface
should be respectively connected to the connectors P3 & P2 on the SDA 85M trainer.
In case of SDA 86 connectors C1 & C2 should be connected to the connectors CN3 &
CN2 respectively. The 8253 timer 2 is programmed to operate in the square-wave
mode. The output pin should show a low frequency compared to the astable output at
jumper J5, when monitored on an oscilloscope or a logic probe, only when the key is
depressed (i.e. The gate input to the 8253 is made high).

Installation Procedure for ADC & Timer Interface

SDA-85M to NFIC-07 Interface Connection Details
1. Connect P3to 85M to the connector C1 on the interface using a 26 core flat cable
CARE SHOULD BE TAKEN THAT, PIN1 OF P3 THE KIT COINCIDES WITH
PIN 1 OF THE CABLE [OBSERVE THE NOTCH ON THE CABLE
CONNECTOR].
2. Power connections
Connect 5V, +/- 12V to the interface
Color codes of power connector on the interface,
1. +5V ORANGE
2. GND BLACK
3. +12V RED
4. -12V GREEN
3. The features of the ADC are
1. ADC -809-28 PIN DIP
SUCCESSIVE APPROXIMATION ADC
INPUTS - 8 ANALOG INPUTS.
MAXIMUM VOLTAGE RANGE -0 TO 5V
CLOCK INPUT ADC – 768 kHz
RESOLUTION – 8-BITS
CONVERSION TIME – 100 MICRO SECONDS
POWER CONSUMPTION 15 Mw

IN0-IN7 ARE THE ANALOG INPUTS TO ADC.

THESE INPUTS ARE FED THROUGH THE 10- WAY RELIAMATE
CONNECTION ON THE BOARD.
PIN0 &10 ARE THE GROUND POINTS AND 2-9 ARE THE INPUT
CHANNELS.
FOR INTERRUPT MODE OF CONVERSION – SHORT J1 & J2.
FOR POLLED MODE CONVERSION – OPEN J1 & J2.
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 4. Enter the program as per the listing given in the appendix in the RAM region.
5. Now execute the program.
GO < STARTING ADDRESS> <EXEC>
The particular channel (i.e., channel 0 to 7) is selected from keypad of the kit.
The keys are from 0- 7. 0 key corresponds to channel 0, key 1 corresponds
channel 1, key 2 corresponds to channel 2, and so on.
Give analog input through any one of the channels.(Max 5V).
Now press the keys on the kit. The key corresponding to particular
channel,through which the input is feed remains constant. This value is displayed
in the data field of the display other channels are all floating i.e., if you press any
key value in the data field keeps on varying.
0V=00H
5V=FFH
All the converted values range between 0 to FF.

Timer interface:
1. Connect P2 on the 85M trainer kit (take care of pin 1 or the cable and the kit) to the
connector C2 on the Interface through a flat cable.
2. Enter the program as per the listing given in appendix
3. Now execute the program,
GO< STARTING ADDRESS> <EXEC>
Press the KEY on the interface, you will observe square wave on the CRO through the
points 1 &2 of the 6 way count provided on the interface.
To change the period of the waveform.
Key in the delay parameter in the address field display. The count should be above
20.( e.g. 30,40 etc)
After entering the delay, press the EXEC key on the kit & press the button on the
interface and observe changed waveform.
The waveform can be observed until the RESET key is pressed.

Figure: 8-Bit Successive Approximation ADC interface

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 CIRCUIT DIAGRAMS
BASIC MICROCONTROLLER CONNECTIONS:

Fig 4.1: Oscillator connection to AT89S8252

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