Professional Documents
Culture Documents
Soc Design Flow
Soc Design Flow
1
From Requirement to Deliverables
Hierarchy Hierarchy
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Refinemenet Validaton
Customer Product
Needs System Vaildation "Pattern" Deliver
System Function System Function
Architecture Architecture
Verification
Behavioral Behavioral
RTL Test
Patern
Logical Netlist Logical Device
Layout
Wafer
Abstract Mask Real
Fab
2
Five SoC Design Issues
• To manage the design complexity
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– Co-design
– IP modeling
– Timing closure
– Signal Integrity
– Interoperability
3
How to Conquer the Complexity
• Use a known real entity
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4
SoC Design Flow
Specification
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Hardware/Software Partition
N2C/VCC
Software
Front End
Design
Design
WinCE/VxWorks Driveway
Chip
5
Physical Design Flow
• In VDSM Specification
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Chip
6
Making Sense of Interconnect
• At 0.35u, timing convergence started to become a problem.
• At 0.25u, it started to significantly impact the work of the
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designer.
• At 0.18u, if not accounted for, it actually causes designs to fail.
Percentage of Delay
Gate
Wire
1.0u 0.5u 0.25u 0.18u
Silicon Technology
Source: Avant! Source: Synopsys
7
Interconnect Power Consumption in DSM
• DSM effects in energy dissipation:
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cross-coupling capacitances
Source: Y. Zorian, S. Dey, and M. Rodgers, “Test of Future System-on-Chips,” Proceeding of the 2000 International Conference on Computer-Aided Design, 392-398 8
Signal Integrity and Timing Closure
• Root causes of both Signal Integrity and Timing Closure
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9
Example - Crosstalk Delay
• Net-to-net coupling capacitance dominates as a
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10
New Physical Design Flow Needed
Specification
• Bring physical information into the
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System Level
logical design Design
Timing
Synthesis Simulaton
Back
LVS/DRC
Back End
Sign-off
Annotated
Package RC
Delay
Extraction
P&R Chip
11
HW/SW Cosimulation Through Emulation
• Emulation in “virtual silicon” 100M
CPS (Cycle/Second
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10M
ices
ls
– Complete functional simulation 1M Emulation
ode
erv
100K
IP M
nS
atio
10K
of the chip at close to real time
con
ific
1K
Sili
Acceleration
Ve r
100
Source: IKOS Systems Inc
– Run real software 10 Simulation
Error Memory
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MMI/GUI
Host Handling Allocation
Diagnostics
Application Message Task State
Manager controller Machine
Device Drivers
Hardware
13
Software Development
• Porting software to a new processor and RTOS
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Old New
14
Software Performance Estimation
• Have to take the following into account
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– Instruction set
– Bus loading
– Memory fetching
– Register allocation
• Example: Cadence VCC technology
– CPU characterized as Virtual Processor Model
– Using a Virtual Machine Instruction Set
– SW estimation using annotation into C-Code
– Good for early system scheduling, processor load estimation
• Two orders of magnitude faster than ISS
• Greater than 80% accuracy
15
Tester Partitioning
High bandwidth
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Source/ Source/
Logic Sink Logic
Sink Low bandwidth
Source: Y. Zorian, S. Dey, and M. Rodgers, “Test of Future System-on-Chips,” Proceeding of the 2000 International Conference on Computer-Aided Design, 392-398 16
Self-Testing of Embedded Processor Cores
• Logic BIST
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17
Platform-based Design
Block Authoring VC Chip Integration SW
Delivery Development
Executable Specification
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Functional
Design
Formal IP Handoff
Testbenches
Testbenches
Block
Integration
Design
Implementation Chip
Implementation
Supporting Manufacturing
Physical
Verification SW
Physical Distribution
Link
Verification
Technology
SW
Cell IP Portfolio Authoring Guide Integration Development RTOS/
IP Portfolio
Libraries Platform Links Applications
" Source: “Surviving the SOC Revolution - A Guide to Platform-Based Design” by Henry Chang et al, Kluwer Academic Publishers, 1999 18
Design Entry
Gate level
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Truth table
1K~10K
FSM
Waveform Manage Size and Run-Time
19
Hardware Platform-Based Design
It is a “meet-in-the-middle” approach.
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20
System-Level Design
• Goal
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21
Control Scheme Model
Interrupts
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Interrupt
Status Polling (timer)
Status
Command
Configuration
22
Some Helps in System-Level Design
• Cadence VCC (Virtual Component Codesign,
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23
Cadence’s VCC
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Development
Development
Hardware
Software
Algorithm Analysis Platform Configuration
SPW Fixed Point VCC Communication Synthesis
Algorithm Analysis Communication Integration
VCC Hardware VCC Software
SPW HDS Block Implementation
Assembly Assembly
HW/SW Verifier - Verification Cockpit - NC-SIM
RTL Block Verification and HW-SW-Co-Verification
Synthesis / Place & Route etc.
24
25
An Opportunity To Do It Right !
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26
SystemC Heritage
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27
SystemC Roadmap
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The Intent of Different Level of Model
• Design exploration at higher level
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28
SystemC
• SystemC is a modeling platform
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29
30
Level of abstraction in SystemC
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31
SystemC Design Flow
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32
Source: SystemC Users Forum, DAC, June 2000
Example
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Implementing Virtual Prototypes
• Functionality partition
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• Module specification
• Communication refinement
Func_A()
{
MC
IQ_IDCT()
...... MC
{
IQ(); Func_B() ......
......{ IQ(); FIFO
} ......
IDCT();
IDCT();
......
IQ-
......
} IDCT IQ-
}
IDCT
33
Functionality Partition
• Separating communication and computation
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34
Module Specification (1/2)
Process A
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entry()
{
......
Z = func_B(X,Y);
......
}
func_B(X,Y)
{
Z = X+Y;
retuen Z;
2 }
Process B Process C
X
entry() entry()
{ {
...... Y X.read();
X.write(); Y.read();
Y.write(); Z = X+Y;
Z.read(); Z Z.write();
...... }
}
3
35
Module Specification (2/2)
• Abstraction Levels
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36
Communication Refinement
Key
Guarantee consistency of communication during refinement
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37
Software Performance Estimation
• Have to take the following into account
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– Instruction set
– Bus loading
– Memory fetching
– Register allocation
• Example: Cadence VCC technology
– CPU characterized as Virtual Processor Model
– Using a Virtual Machine Instruction Set
– SW estimation using annotation into C-Code
– Good for early system scheduling, processor load estimation
• Two orders of magnitude faster than ISS
• Greater than 80% accuracy
38
Discussion: Commonality and Differentia
• Differentiae
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39
Summary
• Platform-based design
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40