Intel 8088 pro

essor
8088 pin onguration
The 8088 ma hine y le onsists of four lo k y les. The four lo k pulses within the ma hine
y le are normally alled T1, T2, T3 and T4. During T1 the 20 pins AD0 − AD7, A8 − A15 and
A16/S3 − A19/S6 a t as the address bus. after that, AD0 − AD7, a t as the 8-bit data bus and
A16/S3 − A19/S6 a t as four status pins.
Fun tionalities of some of the other pins:
• RD - memory read (if S2 is 1) or I/O read (if S2 is 0).

• READY - the pin through whi h the addressed memory or I/O devi e a knowledges that it is
able to omplete the data transfer.
• IN T R - interrupt request

• N M I - non-maskable interrupt request

• RESET - used for resetting the pro essor.

• CLK - lo k input whi h provides the basi timing for the pro essor. This should be an asym-
metri signal with 33
• M N/M X - indi ates what mode the pro essor is to operate in ( minimum mode or maximum
mode).
• S0, S1 and S2 - status pins. A tive only during T1, T2 and T4. Otherwise stay in 1 state.

8088 registers

8088 pin diagram

GND VCC
A14 A15
A13 A16/S3
A12 A17/S4
A11 A18/S5
A10 A19/S6
A9 SS0
A8 MN/MX
AD7 RD
AD6 8088 RQ/GT0
AD5 RQ/GT1
AD4 LOCK
AD3 S2
AD2 S1
AD1 S0
AD0 QS0
NMI QS1
INTR TEST
CLK READY
GND RESET

Memory segmentation
The 8088 mi ropro essor has a 20 bit address bus. Therefore one an onne t a maximum of 1
Megabytes of memory. However, the internal registers are all 16-bit. In parti ular, the instru tion
pointer IP is a 16-bit register. Therefore IP alone annot a ess more than 64 kilobytes of memory.
This problem has been solved by the use of segment registers. Whenever the 8088 needs to fet h
an address from the memory, it onstru ts a 20-bit address by ombining IP with the ode segment
register CS. As shown below, this ombining is done by shifting the ontents of the segment register
by 4 bits to the left and adding it to IP.

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 Following are the general rules for using segment
registers:

• IP is always added to CS

• SP is always added to SS

• BP is normally added to SS

• All other registers are normally added to DS.

IBM PC Ar hite ture

In the IBM PC, 8088 was onne ted to several support hips. These in lude 8284A lo k gener-
ator/driver, 8288A bus ontroller, and 8259A programmable interrupt ontroller and 8237A pro-
grammable DMA ontroller. Figure below shows the onne tions to these hips and the way address
and data pins are demultiplexed.
8288
bus controller
s0 clk
clock clk s0 s1 MEMR
generator ready s1 MEMW
reset s2 IOR
s2 DEN
IOW
DT/R
8088 INTA
ALE
processor
STB
AD0−AD7 address bus
A8−A19 74373
latch
DIR
G data bus
74245
buffer

IRQ0
IRQ1 interrupt
IRQ2 requests
8259
interrupt IRQ7
controller

The 8284A lo k generator produ es the lo k signal for the pro essor. The lo k signal is a square
wave whi h is high during one third of the y le and low during two thirds of the y le. An 8088
ma hine y le onsists of four lo k y les.
The 8288 bus ontroller generates following ontrol signals using the information from S0 - S2 lines.
IOR (I/O read): When this line is low, the pro essor is reading the ontents of the I/O port
address spe ied by the address bus.
IOW (I/O write): When this line is low, the pro essor is writing the ontents of the data bus to
the I/O port address spe ied by the address bus.
M EM R (memory read): When this line is low, the pro essor is reading from memory address
spe ied by the address bus.
M EM W (memory write): When this line is low, the pro essor is writing to the memory address
spe ied by the address bus.
IN T A (interrupt a knowledgment): This line is used by the pro essor to a knowledge an interrupt.

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Memory mapped and isolated I/O

Using the above signals, it

is possible to interfa e exter-
nal devi es as memory mapped
I/O devi es or as isolated I/O
devi es. If a devi e is made to
respond to I/O read and write
signals, it be omes an isolated
I/O devi e. In the 8088 pro-
essor, only address lines A0
- A15 are used for isolated
I/O. That means it is possible
to onne t devi es with 65536
dierent addresses. However,
in order to make address de-
oding logi simple, the IBM
PC ignores address lines from
A10 to A15. This restri ts the
number of possible I/O ports
to 1024.
If a devi e responds to memory read and write signals, it be omes a memory mapped I/O devi e.
In the PC, all 20 address lines are used for memory mapped I/O. Therefore, there are 1048576 dierent
memory addresses. It is possible to onne t I/O devi es to use one or more of these addresses. However,
devi es other than memory and graphi adapters are normally onne ted as isolated I/O devi es.
The isolated I/O map of a PC running Windows XP an be displayed by sele ting ontrol panel,
system, devi e manager, properties and input/output as shown above.

Read/Write y les

The gure below shows a timing diagram for

an 8088 memory read y le.CLK, S0, S1 and
S2 signals are produ ed by the 8088. The
others signals are those produ ed by the In-
tel 8288 bus ontroller used in the IBM PC.

Interrupt handling
When an external devi e needs to ommuni ate with the pro essor, it sends a signal through one of
the 8 interrupt inputs of the 8259. (Ideally, only one devi e should be atta hed to ea h of the 8 inputs
labeled IRQ0, IRQ1 . . . . Otherwise an interrupt oni t an o ur.)
Seeing the interrupt request from the external devi e, the 8259 sets the INTR line of the 8088
high. At the same time it pla es a number on the data bus identifying the input line through whi h
it re eived the request.
If the data byte put on the data bus by the interrupt ontroller is n, the pro essor assumes that
memory lo ations 0:n×4 and 0:n×4 +1 ontain the IP. The lo ations 0:n×4+2 and 0:n×4+3 are
assumed to ontain CS. This ombination of IP:CS determines the interrupt ve tor.
Assignment of hardware interrupts to various devi es an be viewed in PCs running Windows XP
by sele ting ontrol panel, system, devi e manager, properties and interrupt request as shown below.

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 For example, if IRQ5 line is a tivated by an external devi e, the 8559 sets the INTR high and
puts the number 0Dh (or 13 in de imal) on the data bus. Then the pro essor fet hes two bytes from
addresses 0:34 and 0:35 and loads them in IP. Two bytes from 0:36 and 0:37 are loaded in CS.
Interrupt Type Name Comments
0 divide by 0
1 single step
2 NMI
3 breakpoint
4 overow
5 print s reen
6 unused Software interrupts
7 unused Software interrupts are very similar to
8 IRQ0 - time of day hardware interrupts. One important dif-
9 IRQ1 - key board feren e is that they are generated by a
A IRQ2 software instru tion of the form INT n
B IRQ3 - COM2 8259A instead of a hardware signal. The num-
C IRQ4 - COM1 interrupt ber n whi h follows INT is used to deter-
D IRQ5 - unused lines mine the lo ation of the ve tor, exa tly
E IRQ6 - diskette the way it is done in hardware interrupts.
F IRQ7 - LPT1 The interupt assignment s heme in the
10 video I/O original IBM PC is shown in the table.
11 equipment Modern PCs have more hardware IRQ
12 memory lines and therefore this table is dierent
13 disk I/O for them.
14 serial I/O
15 assette BIOS
16 keyboard I/O entry
17 printer points
18 resident BASIC
19 bootstrap
1A time of day