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Ref 102
Ref 102
102
REF102
REF
102
10V Precision
Voltage Reference
FEATURES APPLICATIONS
● +10V ±0.0025V OUTPUT ● PRECISION-CALIBRATED VOLTAGE
● VERY LOW DRIFT: 2.5ppm/°C max STANDARD
● EXCELLENT STABILITY: ● D/A AND A/D CONVERTER REFERENCE
5ppm/1000hr typ ● PRECISION CURRENT REFERENCE
● EXCELLENT LINE REGULATION: ● ACCURATE COMPARATOR THRESHOLD
1ppm/V max REFERENCE
● EXCELLENT LOAD REGULATION: ● DIGITAL VOLTMETER
10ppm/mA max ● TEST EQUIPMENT
● LOW NOISE: 5µVPP typ, 0.1Hz to 10Hz ● PC-BASED INSTRUMENTATION
● WIDE SUPPLY RANGE: 11.4VDC to 36VDC
● LOW QUIESCENT CURRENT: 1.4mA max
● PACKAGE OPTIONS: PLASTIC DIP, SO-8
DESCRIPTION Trim
5
V+
2
The REF102 is a precision 10V voltage reference. The drift
is laser-trimmed to 2.5ppm/°C max C-grade over the indus-
trial temperature range. The REF102 achieves its precision R5 50kΩ
R2 R3
without a heater. This results in low power, fast warm-up,
excellent stability, and low noise. The output voltage is
14kΩ 8kΩ
extremely insensitive to both line and load variations and can
R1 22kΩ –
be externally adjusted with minimal effect on drift and 6
A1 VOUT
stability. Single-supply operation from 11.4V to 36V and
+
excellent overall specifications make the REF102 an ideal
choice for demanding instrumentation and system reference R6 7kΩ
R4
applications.
DZ1 4kΩ
8 4
Noise Common
Reduction
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000-2009, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
Input Voltage ...................................................................................... +40V
Operating Temperature DISCHARGE SENSITIVITY
P, U ................................................................................. –25°C to +85°C
Storage Temperature Range This integrated circuit can be damaged by ESD. Texas Instru-
P, U ............................................................................... –40°C to +125°C ments recommends that all integrated circuits be handled with
Short-Circuit Protection to Common or V+ .............................. Continuous appropriate precautions. Failure to observe proper handling
NOTE: (1) Stresses above these ratings may cause permanent damage. and installation procedures can cause damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION(1)
MAX INITIAL MAX DRIFT PACKAGE PACKAGE
PRODUCT ERROR (mV) (PPM/°C) PACKAGE-LEAD DESIGNATOR MARKING
REF102AU ±10 ±10 SO-8 D REF102AU
REF102AP ±10 ±10 DIP-8 P REF102AP
REF102BU ±5 ±5 SO-8 D REF102BU
REF102BP ±5 ±5 DIP-8 P REF102BP
REF102CU ±2.5 ±2.5 SO-8 D REF102CU
REF102CP ±2.5 ±2.5 DIP-8 P REF102CP
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com.
PIN CONFIGURATIONS
NC 1 8 Noise Reduction
V+ 2 7 NC
NC 3 6 VOUT
Com 4 5 Trim
NC = Not Connected
2
REF102
www.ti.com SBVS022B
ELECTRICAL CHARACTERISTICS
At TA = +25°C and VS = +15V power supply, unless otherwise noted.
REF102 3
SBVS022B www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +15V, unless otherwise noted.
VOUT VOUT
VIN VIN
120
+1.0
Power Supply Rejection (dB)
110
+0.5
100
0
90
−0.5
80
70 −1.0
60 −1.5
1 100 1k 10k –5 0 +5 +10
Frequency (Hz) Output Current (mA)
+300 1.4
0 1.2
–300 1.0
REF102C Immersed in +85°C Fluorinert Bath
TA =
+25°C TA = +85°C
–600 0.8
0 15 30 45 60 −75 −50 −25 0 +25 +50 +75 +100 +125
Time (s) Temperature (°C)
4
REF102
www.ti.com SBVS022B
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +15V, unless otherwise noted.
20Ω 2kΩ
6 Oscilloscope
4
Noise Voltage (µV)
– 8kΩ
2 100µF OPA227
0 DUT +
2µF
15.8kΩ
−2 Gain = 100V/V
f −3dB = 0.1Hz and 10Hz
−4
V1
zener. 2.75mV
VNOMINAL Worst-case
+10.0000 ∆VOUT for
REF102CU
DISCUSSION V2
OF PERFORMANCE +9.99725
REF102CU VLOWER BOUND
The REF102 is designed for applications requiring a preci-
sion voltage reference where both the initial value at room −25 0 +25 +50 +85
temperature and the drift over temperature are of importance Temperature (°C)
to the user. Two basic methods of specifying voltage refer-
ence drift versus temperature are in common usage in the
FIGURE 1. REF102CU Output Voltage Drift.
industry—the butterfly method and the box method. The
REF102 5
SBVS022B www.ti.com
INSTALLATION AND used. The circuit in Figure 3 has a minimum trim range of
±300mV. The circuit in Figure 4 has less range but provides
OPERATING INSTRUCTIONS higher resolution. The mismatch in TCR between RS and the
BASIC CIRCUIT CONNECTION internal resistors can introduce some slight drift. This effect
is minimized if RS is kept significantly larger than the 50kΩ
Figure 2 shows the proper connection of the REF102. To
internal resistor. A TCR of 100ppm/°C is normally sufficient.
achieve the specified performance, pay careful attention to
layout. A low resistance star configuration will reduce voltage
errors, noise pickup, and noise coupled from the power
supply. Commons should be connected as indicated, being
sure to minimize interconnection resistances. V+
+ 1µF
2 Tantalum
(1)
VOUT
6
2 (2)
REF102 +10V
VTRIM
20k Ω
V+ 6 5
Output
+ 1µF Voltage
Tantalum REF102 Adjust
RL 1 RL 2 RL 3
4
(1) (2)
FIGURE 3. REF102 Optional Output Voltage Adjust.
NOTES: (1) Lead resistances here of up to a few ohms have
negligible effect on performance. (2) A resistance of 0.1Ω in
series with these leads will cause a 1mV error when the load
current is at its maximum of 10mA. This results in a 0.01% V+
error of 10V.
+ 1µF
2 Tantalum
FIGURE 2. REF102 Installation. VOUT
6
6
REF102
www.ti.com SBVS022B
OPTIONAL NOISE REDUCTION APPLICATIONS INFORMATION
The high-frequency noise of the REF102 is dominated by the
High accuracy, extremely low drift, outstanding stability, and
zener diode noise. This noise can be greatly reduced by
low cost make the REF102 an ideal choice for all instrumen-
connecting a capacitor between the Noise Reduction pin and
tation and system reference applications. Figures 6 through
ground. The capacitor forms a low-pass filter with R6 (refer to
14 show a variety of useful application circuits.
the figure on page 1) and attenuates the high-frequency
noise generated by the zener. Figure 5 shows the effect of a
1µF noise reduction capacitor on the high-frequency noise of
the REF102. R6 is typically 7kΩ so the filter has a –3dB V+ (1.4V to 26V)
frequency of about 22Hz. The result is a reduction in noise 2
from about 800µVPP to under 200µVPP. If further noise
reduction is required, use the circuit in Figure 14.
6 (5V −IL)
REF102 1.4mA < < 5.4mA
RS
4
−10V Out
IL
RS
NO CN
−15V V+ (1.4V to 26V)
2
a) Resistor Biased –10V Reference
R1
REF102
2kΩ
6
10V
C1
CN = 1µF 1000pF
REF102 7
SBVS022B www.ti.com
V+ V+ V+
2
220Ω
–
OPA227 +10V 2N2905
6 IL 2 2
REF102 + R1 = VCC − 10V
IL (TYP)
6
6 +10V
REF102 +10V REF102 IL
4 IL
4 4
a) −20mA < IL < +20mA b) −5mA < IL < +100mA c) IL (MAX) = IL (TYP) +10mA
(OPA227 also improves transient immunity) IL (MIN) = IL (TYP) −5mA
FIGURE 7. +10V Reference With Output Current Boosted to: a) ±20mA, b) +100mA, and c) IL (TYP) +10mA, –5A.
+15V
28mA
2 357Ω
1/2W 28.5mA
6 +5V
350 Ω Strain
REF102 Gauge Bridge
5
–
4
8 V OUT
RG INA126
x100
2
– +
10
6
OPA227
+
3
−5V
357Ω
1/2W
–15V
V+ V+
2 2
6 6
+10V REF102
REF102 Out
2 5
−10V
25kΩ 25kΩ Out R
– I OUT
4
4 OPA277
6 +
25kΩ LOAD
3
Can be connected
25kΩ to ground or −VS .
1 10V
INA105 IOUT = , R ≥ 1kΩ
R
See SBVA007 for more details. See SBVA001 for more details and ISINK Circuit.
8
REF102
www.ti.com SBVS022B
31.4V to 56V
2
V+
2
+30V
6
REF102 6 +10V
REF102
INA105
2
4
2
5
4
+20V
6 –
REF102
6 +5V
3
+
4
2
1
+10V
6
REF102
V+
NOTES: (1) REF102s can be stacked to obtain voltages in multiples of 10V. 2
(2) The supply voltage should be between 10n + 1.4 and 10n + 26, where n is
the number of REF102s. (3) Output current of each REF102 must not exceed 2kΩ
its rated output current of +10, −5mA. This includes the current delivered to 6
the lower REF102. REF102 VOUT 1
(1)
R2
FIGURE 11. Stacked References.
2kΩ
4
C2
V+
V+ 2 1µF
2 –
2
2kΩ OPA227
6 3 +
+5V REF102 R1
6 VOUT 2
(2) 1k Ω
Out +10V
REF102
2 VREF
C1 1µF
INA105 4
5 4 –5V
Out V+
VREF = (V01 + V02 … VOUT N)
2
– N
6
2kΩ
+ 6 eN = 5µVPP (f = 0.1Hz to 1MHz)
REF102 VOUT N √N
(N)
See SBVA002 for more details.
1 3 4
FIGURE 12. ±5V Reference. FIGURE 14. Precision Voltage Reference with Extremely
Low Noise.
REF102 9
SBVS022B www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
10
REF102
www.ti.com SBVS022B
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
REF102AP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type REF102P
& no Sb/Br) A
REF102AU ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR REF
& no Sb/Br) 102U
A
REF102AU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR REF
& no Sb/Br) 102U
A
REF102AUG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR REF
& no Sb/Br) 102U
A
REF102BP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type REF102P
& no Sb/Br) B
REF102BU ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -25 to 85 REF
& no Sb/Br) 102U
B
REF102BUG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -25 to 85 REF
& no Sb/Br) 102U
B
REF102CP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -25 to 85 REF102P
& no Sb/Br) C
REF102CPG4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -25 to 85 REF102P
& no Sb/Br) C
REF102CU ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -25 to 85 REF
& no Sb/Br) 102U
C
REF102CU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -25 to 85 REF
& no Sb/Br) 102U
C
REF102CUG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -25 to 85 REF
& no Sb/Br) 102U
C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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