~. ~ ..

'

LAB EXERCISE 5.1

Set-Clear Flip-flops

~ lab ' exercise will foCus on the Set-Clear flip.;f1ops. You will
Objectives study several methods of implementing the s-c flip-flops.

Materials LD-2 Logic Designer

74LS02 Quad 2-Input NOR IC

74LSOO Quad 2-Input NAND IC

Jumper Wires

TILData Book

Procedure Until now we have concentrated on learning the basics of

flip-flop operation. To better understand . these ·. experiments
some nuances of flip-flops must be understood. Most of the flip- "­
flops discussed in the text were level or pulse triggered devices.
These devices use the standard flip-flop notations. As was noted
in the text active LO inputs to ' the flip-flops are,designated by a
bubble on the input pin. Another type of flip-flop which
operates similarly is the edge triggered flip-flop. These devices
will have the same basic truth table as the devices we have
studied; however, the output will change states only on the
positive (LO to HI) or negative (HI to LO) edge of the dock
pulses. Edge triggered . inputs are shown bya triangle on the
affected input as shown in .Figure .'>-15.
FIGURE 5-15. Schematic
Symbol for Edge Triggered
Flip-flop.

Circuits to accomplish the edge triggering functions are shown

in Figure .>-16.
90
 In FIGURE 5-16. Edge
Trigger Circuits.

Positive Edge Trigger (Lo to HI Transition)

Negative Edge Trigger {HI to LoTransition) ,

In.

Positive and Negative Edgeirigger

The operation of the circuits is possible beci'iIse of the

gate delay of the inverters. This gate ,delay results in a short
duration pulse correspondil\g ,t<;> , the edge of the clock pulse.
With these fundamentals you are ready to perform experiments
with flip-flops.

1. Wire the circuit shown in Figure 5-17 using the 74LS02

NOR gate.

FIGURE 5-17. Schematic

CLR
for NOR ·S-C· Flip-flop.
S2
D--~_---a

L2

1 L1
»--------0
S1 - - -.......-1'
.' Set

214 74LS02

2. Wire the power and ground pins to the 74LS02 if you

have not already done so. Place Sl and S2 to OFF.
91
 3. S1 is the Set input, . S2 the Clear input, L2 the Q output
and L1 the;O output:' Determine the truth table for this
circuit and record your ieSillfhete. '
. )" .

4. Wire the circuit for the NAND s-c flip-flop shown in

Figure 5-18. , .
FIGURE 5-18. Schematic
for NAND ·S-C· Flip-flop. S1
Set D-_---'O
L1

S2
Clear
214 74LSOO
5. Wire power and ground to the 74LSOO. Place S1 and 52 to
ON.

6. TU!,I' on power. D1 and L2 sho~d light.

7. Use 51, '52, L1 and U todeterinine the truth 'table for this
drcuit.ReC:ordyour
, , '
observationS here:

8. Remove power from this circuit and leave the circuit on

the circuit board for use in the next experiment.

Questions 1. Which states cause trouble for theNaR s-c flip-flop?

2. Which states cause trouble for the NAND s-c flip-flop?

92
3. What state should the inputs to a NOR g..c flip-flop be
. ?
ffi.

4. What state should the inputs to a NAND S:C flip-flop be

. ?
ffi.

, .

In this lab exercise you will study the "D" latch. You will LAB EXERCISE 5.2
implement two types of "D" latches, one with active HI input The "0" Latch
and the other with active LO input. ObJectiv~s

LD-2 Logic Designer Materials

74LSOO Quad NAND Ie

74LS04 Hex Inverters Ie

Jumper Wires

TIL Data Book

1. Wire the active HI "D" latch circuit shown in ,Figure 5-19 Procedure
using the 74LSOO and 74LS04 Ies. If you have retained the
circuit from laborat()ry 5-1, this will only requife rewiring
the two input lines to the S-C FF. /.~ P
S1
D
- .
1
r./3 _ _ . FIGURE 5-19. Schematic for
-0" Flip-flop.
10---1"'-- Q
L1

)
L2
1/6 74LS04 f 214 74LSOO

93
 2. Wire power and ground to all circuits.

3. Use Sl as the D input, U as the Q output, and L1 as the

complement output. Construct a truth table for this
circuit.

4. Now, turn off pdwer and swap the wires connected to

pins 1 and 5 of the 74LSOO. This will result in a low
active "0" latch.

5. Use ,51, 12 and L3 to determine the truth table for this.

circuit. ·'Reeaid yoUr observations here. . . .. ... . ..

6. Leave this circuit connected while you . answer the

following questions.

Questions 1. What do you notice about the circuit of Figure 5-19? How
could this CIrcuit be simplified?

2. How could the circuit of step 5 be constructed using only

one IC? Build a ~cuit'to test your solution.

94
 LAB EXERCISE 5.3
The Clocked Set·
Clear Flip-flops
In this lab exercise we will study th~ clOcked s-c .flip-flops and
clock signals. . ' . . . Objectives

L0-2 Logic Designer ' Materials

74L500IC

Jumper Wires

TTL Data Book

In order to perf()rm this experiment we will need to Procedure

understand something about clOCk signals. Oock signals are
periodically spaced binary pulses. These pulses are used for
circuit timing in sequential logic circuits. The duty cycle of a
clock signal is the pulse length divided by the period and is
expressed as a percentage by multiplying the quotient by 100.
Two clock outputs are available on the L0-2 at the left most two­
row:breadboard.

1. Connect the clock output to L7 on L0-2. Turn on power.

2: Set the clock frequency to 1 Hz.

3. Turn on power and observe L7. Record your observation.

H an oscilloscope is availabl~ observe the clock pulse and
sketch your observations.

95
 4. Turn-off power ~d wire the circuit shown in Figure 5-20.
FIGURE '5-'20. Sch$ry'latic
for Cloc~ed ·S-C· FIi,p-flQP·
,. ~:

S _____
10...
..- ­
S1 9 ~--......!..:r-~D-_ _ _ _ _ a
L1
Clock PB2 .n.
13
L2­a
a;.._----=:..
52
Aore
4/4 74L500

5. Use S1 as the Set input, S2 as the Oear or Reset input,

PB2 for the clock input, Ll as the Q output, and U as the
Q output to construct a truth table for this circuit. Record
your observations here.
.. .

6. Record your obserVations of ~e outputs if the dock input

is not actuated.'. . .

Questions 1. Does adding the clock circuitry cure the inherent flaws of
the s-c flip-flop circuit? Explain.

2. When do the input signals have an effect on the output

states?

------------------------------------------- .~
96
 LAB EXERCISE 5.4

The 'T' Flip-flops

In this lab exercise" we will study the implementation ' and

application of "T" flip-flops. Objective~

L0-2 Logic Designer Materials

74;LS74 Dual "D" Type Positive Edge Triggered Flip-flop

With Preset and dear

Jumper Wires

TIL Data Book

1. Use the 74LS74' IC to construct the Circuit shown in Figure Procedure

~21. 2J.
Sc-t FIGURE 5-21. Schematic
• for "r Flip-flop .
14
S 5
1. D Q I - - - - - L1

. . '. '
.. : .. ,. , .

7~LS74
. . ~ :.: .

112

Clear
51.
2. The feedback of the complement output to the D input
results in the toggle operation. Wire power and ground
to the IC

3. Turn on power and record the initial state of the latch.

4. Record your observation of L1, Q and L7, cloc.k, while

pressing PB2 several times.

5. Turn Off power. Remove the wire to PB2 and place it on

97
 ·. the clock signal. .Set d~Jrequency . to 1 Hz.

6. Tum On power and observe the clock and 'T' flip-flop

outputs ·on L7 and Llrespectively.., Record your
observation here.

7. Leave this circuit connected while answering the

following questions.

Questions 1. What effect does the 'T' flip·Jlop have on binary pulse
· ?
traIDS.

2. In Step 4 how many .t;imes do you have , to . push PB2

before the flip-flop output toggles through an entire cycle
(example: starts LO goes HI, then end LO)? .

. '--­

LAB EXERCISE 5.5

The Clocked "0"
Flip-flops

Objectives In this lab exercise you will study clocked "D" flip-flops.

Materials LD-2 logic Designer

74LS74 Dual"D" Type Positive Edge Triggered Flip-flop

With Preset and Clear

Jumper Wires

ITL Data BoOk

Procedure' 1. Wire the circuit shown in Figure 5-22 using the 74LS74.
98
 , ,- FIGURE 5-22.&q,~er;natic
. ~."'.
" '4 for' ClOCked "0· Flip~1iop. '
2 S 5
S 1 - - -..... 0 a~-- L1

PB2 .n. 3 112 74LS74

CK
1

2. Wire power to the ICand place S1 to off.

3. Use Sl as the 0 input, PB2 as the clock input and L1 as the

Q output and create a truth table for the clocked liD" flip­
flop. Record this truth table here.

4. Use PB2 to detennine on which edge of the clock pulse

the liD" latch changes state.

5. Remove power from the circuit and disassemble it.

1. From the results of step 4 describe the switching action of Questions

the 74LS74.

2. Is this an active HI or active LO circuit?

99
 LAB EXERCISE 5.6
The "J-K" Flip-flops In this lab exercise you will study the "J-K" flip-flop and its
Objectives applications.

Materials LD-2 Logic Designer

74l.S76 Dual J-K Flip-flop With Preset and Oear

74LS04QuadHex Inverters

Jumper Wires

TIL Data Book

Procedure 1. Wire the circuit shown in Figure 5-23 using ' the 74LS76
IC Leave room on the breadboard for the 74LS04 IC
FIGURE 5-23. •J-t<" Set ~.-
Flip-flop Schematic.
12
S 15
S1
4 J a L1

PB211 . 1

CK
16
S2 K
14
· R a L2
(3
1/2 74LS76

2. Wire power and ground to this circuit. Place Sl and 52 to

Off. Wire Set and Clear to +5 VDC

3. Tum on power. Observe the initial state of the latch.

4. Use 51, 52, PB2 with Ll and L2 to make a truth table for
the "J-K" flip-flop.

5. Place Sl and S2 to ' the high state. Turn off power. --,­
Connect the wire at PB2 to the elk signal of the LD-2 and
tpL7.
100
 6. .Turri
on ·· powJr.·· .
ObserVe the:.dock on L7and the FF
output on Ll. Describe your observations.

7. Turn off power. Wire the circuit shown in Figure 5-24.

FIGURE 5-24. Schematic
set for Step Seven.
.........2~ S.C-+S VDC
S
S1 1 .»_____- -__4.... J a 1S
L
1
PB2 1 C
~ ____________
16~K a 14 L2

R
1/6 74LS04 3
CLA 112 74LS76

'- B. Wire power and ground to these circuits. Use 51, L1 and
L7 to make a truth table for this circuit.

9. Leave· this circuit connected while answering the

following questions.

1. If bOth J and K inputs are held HI as in steps 5 and 6 what Questions

function is the J-K fliJrflop performing?

2. What latch function does the circuit of step eight

perform? .
,

101
 LAB EXERCISE 5.7
The One-shot In this laboratory you will learn about the monostable
Objectives multivibrator or one-shot.

Materials LD-2 logiC Designer .

74121 Monostable Multivibrator With Schmitt-Trigger

Inputs

Assorted Resistors

Assorted Capacitors

Jumper Wires

TIL Data Book

Procedure 1. Wire the circuit shown in Figure 5-25.

FIGURE 5-25. "One-shot"

Schematic.

11 RIC

· 'O.22Il F
PB2lr
a 6 L7
+5VDC
5
10 Ext

2. Wire power and ground to the circuit.

3. Tum on power. What do you notice about L7?

102
 4. Press PB2. What happened to L7.

5. Turn off power. Remove the }OO k o~_ resistor and put
a 47 k ohm resistor in its place.

6. Turn on power and press PB2. What did you observe?

Compare this pulse with the pulse obtained in Step 4.

7. Turn off power to this circuit.

1. Name one use ora One-shot IC Questions

2. Explain the name One-shot.

103