This document outlines chapters in an introduction to Verilog textbook. Chapter 1 introduces Verilog and the chip design flow. Chapter 2 covers Verilog data types including scalars, vectors, and arrays. Chapter 3 discusses Verilog building blocks such as modules, ports, always blocks, initial blocks and generate statements. Chapter 4 examines behavioral modeling with block statements, assignment types, control flow and functions. Chapter 5 concludes with gate and switch level modeling examples.
This document outlines chapters in an introduction to Verilog textbook. Chapter 1 introduces Verilog and the chip design flow. Chapter 2 covers Verilog data types including scalars, vectors, and arrays. Chapter 3 discusses Verilog building blocks such as modules, ports, always blocks, initial blocks and generate statements. Chapter 4 examines behavioral modeling with block statements, assignment types, control flow and functions. Chapter 5 concludes with gate and switch level modeling examples.
This document outlines chapters in an introduction to Verilog textbook. Chapter 1 introduces Verilog and the chip design flow. Chapter 2 covers Verilog data types including scalars, vectors, and arrays. Chapter 3 discusses Verilog building blocks such as modules, ports, always blocks, initial blocks and generate statements. Chapter 4 examines behavioral modeling with block statements, assignment types, control flow and functions. Chapter 5 concludes with gate and switch level modeling examples.