C. Byregowda Institute of Technology: HDL Lab Manual

C.
Byregowda Institute Of
Technology
Subject HDL
Code: 15ECL58
15EC
L37 LAB MANUAL
DEPT. OF ELECTRONICS & COMMUNICATION

ENGINEERING
2018
C. BYRE GOWDA INSTITUTE OF TECHNOLOGY KOLAR
Department of
Electronics & Communication Engineering
V Semester
HDL LAB MANUAL
(15ECL58)
Lab In charge’s : Mrs. SUJANI G

Mrs. LESHADEVI G
Mr. BHASKAR S.V
Scrutinized By : Mrs. SUJANI G
Approved By : Dr. SREERAMA REDDY G.M
Assisted by: Mr. Srikanth

C. BYRE GOWDA INSTITUTE OF TECHNOLOGY, KOLAR
Department of Electronics & Communication Engg
LINEAR IC’S AND COMMUNICATION LAB
Sub Code: 15ECL48
Contents
prog Page no
Name of the experiment
no.
01 Realize all the logic gates 1
02a Realize 2 to 4 Decoder, 3
02b Realize 8to 3 Encode 5
02c Realize 8to 1 Mux 7
02d Realize 1to 4 Dmux 9
02e Realize Binary to Gray 11
02f Realize bit Comparator 13

model 32 bit ALU
03 15
Full Adder using three modeling styles
04 SR flip-flops, J K flip-flops, D flip-flops, T flip-flops 17
05 4 bit binary, BCD counters, any sequence counter 20
06 Full Adder using three modeling styles 22
01 Stepper motor 29
02 DC Motor 31
03
DAC 34
04
Seven segment display 44
05
Elevator operation. 46
06.07
Extra program 49
5th SEM , (CBCS Scheme) HDL LAB [15ECL58]
Program1 Date:___/____/_______
All logic gates

Aim: Write a Verilog code to to realize all the logic Gates and Simulate.
Theory: A logic gate is an elementary building block of a digital circuit. It is an electronic device that makes logical
decisions based on the different combinations of digital signals present on its inputs A digital logic gate may have more
than one input but only has one digital output. At any given moment, every terminal is in one of the two binary conditions
low (0) or high (1), represented by different voltage levels. There are seven basic logic gates: AND, OR, XOR, NOT, NAND,
NOR, and XNOR.
 The AND gate is so named because, if 0 is called "false" and 1 is called "true," the gate acts in the same way as
the logical "and" operator.
 The OR gate gets its name from the fact that it behaves after the fashion of the logical inclusive "or."
 The XOR (exclusive-OR) gate acts in the same way as the logical "either/or."
 A logical inverter , sometimes called a NOT gate, has only one input. It reverses the logic state.
 The NAND gate operates as an AND gate followed by a NOT gate
 The NOR gate is a combination OR gate followed by an inverter.
 The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter.
Circuit Diagram and Truth table:
Block Diagram
Prepared By: BHASAKR S VBE, M.Tech, LMISTE Dept. Of ECE, CBIT Kolar
Truth table
a b c d e f g h i
0 0 0 0 1 1 1 0 1
0 1 0 1 1 1 0 1 0
1 0 0 1 0 1 0 1 0
1 1 1 1 0 0 0 0 1
BOOLEAN EXPRESSIONS:
C = AB , D = A+B
E = A', F = (AB)'
G = (A+B)' H = A B
I=A B
PROGRAM:
module basic_gates (a,b,c,d,e,f,g,h);
input a,b;
output c,d,e,f,g,h;
assign e= ~a;
assign c=a&b;
assign d=a|b;
assign f=~(a&b);
assign g=~(a|b);
assign h=a^b;
assign i=~ (a^b);
endmodule
SIMULATION OUTPUT:
RESULT: The logic gates designs have been realized and simulated using HDL codes.
APPLICATIONS :
 In practice, the gates are made from field-effect transistors (FETs), particularly MOSFETs (metal–oxide–
semiconductor field-effect transistors).
 Logic circuits include devices such as multiplexers, registers, arithmetic logic units (ALUs), and computer
memory, all the way up through complete microprocessors, which may contain more than 100 million
gates.
 Compound logic gates AND-OR-Invert (AOI) and OR-AND-Invert (OAI) are often employed in circuit design
because their construction using MOSFETs is simpler and more efficient than the sum of the individual
gates.Every digital product, like computers, mobile, calculators even digital watches, contain logic gates
Program2a Date:___/____/_______
2 to 4 decoder
Aim: Write a Verilog code to to realize 2 to 4 decoder and simulate.
Theory:
 A n-to-2n decoder takes an n-bit input and produces 2n outputs. The n inputs represent a binary
number that determines which of the 2n outputs is uniquely true.
 A 2-to-4 decoder operates according to the following truth table.
 The 2-bit input is called a & b, and the four outputs are y0-y3.
 If the input is the binary number i, then output Qi is uniquely true.
 For instance, if the input a & b = 10 (decimal 2), then output y2 is true, and y0, y1, y3 are all false
 This circuit decodes a binary number into a one-of-four code
Block Diagram: Circuit Diagram:
Truth Table: Boolean Expression:

E a b y3 y2 y1 y0 y3 = Eab
1 0 0 0 0 0 1 y2 = Eab'
y1 = Ea'b
1 0 1 0 0 1 0 y0 = Ea'b'
1 1 0 0 1 0 0
1 1 1 1 0 0 0
0 X X 0 0 0 0
Verilog Code Alternate Code

module dec2_4 (a,b,en,y0,y1,y2,y3) module decoder (s,r);
input a, b, en; input [1:0]s;
output y0,y1,y2,y3; output [3:0]r;
assign y0= (~a) & (~b) & en; reg [3:0]r;
assign y1= (~a) & b & en; always@ (s)
begin
assign y2= a & (~ b) & en; case (s)
assign y3= a & b & en; 2'b00: r=4'b0001;
end module 2'b01: r=4'b0010;
2'b10: r=4'b0100;
2'b11: r=4'b1000;
default: r="z";
endcase
end
endmodule
Wave form:
RESULT: The 2 to 4 decoder design have been realized and simulated using Verilog code.
APPLICATIONS:
Decoding is necessary in applications such as data multiplexing, 7 segment display and

memory address decoding, wireless control systems.
Program2b Date:___/____/_______
8 TO 3 ENCODER
Aim: Write a Verilog code to to realize 8 to 3 Encoder.
Theory:
 An encoder is a device, circuit, transducer, software program, algorithm or person that
converts information from one format or code to another, for the purposes of standardization,
speed, secrecy, security, or saving space by shrinking size.
 Encoders are combinational logic circuits and they are exactly opposite of decoders. They accept one
or more inputs and generate a multi bit output code.
 An encoder has M input and N output lines. Out of M input lines only one is activated at a time and
produces equivalent code on output N lines. If a device output code has fewer bits than the input
code has, the device is usually called an encoder.
 Octal-to-Binary take 8 inputs and provides 3 outputs. At any one time, only one input line has a value
of 1
Block Diagram: Circuit Diagram:
8 3
y Enc_wop a
WITHOUT PRIORITY
a0 = y1 + y3 + y5 + y7
a1 = y2 + y3 + y6 + y7
a2 = y4 + y5 + y6 + y7
WITH PRIORITY
a0 = y1 + y3 + y5 + y7
a1 = y2 + y3 + y6 + y7
a2 = y4 + y5 + y6 + y7
Verilog Code (WITHOUT PRIORITY) Verilog Code (WITH PRIORITY)

module enc_wop(a,y); module enc8_3(y, a);
input [7:0]y; input [7:0] y;
output [2:0]a; output [2:0] a;
reg [2:0]a; reg [2:0]a;
always@ (y) always @(y)
begin begin
case (y) case (y)
8'b 00000001: a=3'b000; 8'b0000000X: a=3'b000;
8'b 00000010: a=3'b001; 8'b0000001X: a=3'b001;
8'b 00000100: a=3'b010; 8'b000001XX: a=3'b010;
8'b 00001000: a=3'b011; 8'b00001XXX: a=3'b011;
8'b 00010000: a=3'b100; 8'b0001XXXX: a=3'b100;
8'b 00100000: a=3'b101; 8'b001XXXXX: a=3'b101;
8'b 01000000: a=3'b110; 8'b01XXXXXX: a=3'b110;
8'b 10000000: a=3'b111; default: a=3'b111;
default: a="zzz"; endcase
endcase end
end endmodule
endmodule
Wave form:
RESULT : The 8 to 3 encoder design have been realized and simulated using Verilog code..
APPLICATIONS:
Encoding is used in most wireless control systems to prevent interference. It is useful in web
processes, handling and inspection systems that use conveyors and simple speed or position
control in high vibration environments.
.
Program2c Date:___/____/_______
MULTIPLEXER (8 TO 1)
Aim: Write a Verilog code to to realize 8 to 1 Multiplexer and simulate.
Theory:
A multiplexer has many input lines and one output line. The signal from one input line will be directed
to the output line. The input line is chosen based on the signals which are carried to the multiplexer on another
set of input lines called control lines. Multiplexers are sometimes called selectors because they choose or select
one of their inputs.
The number of control lines needed depends on the number of input lines. A multiplexer with 2 control
lines can select from 4 input lines, a multiplexer with 3 control lines can select from 8 input lines. In general, a
multiplexer with n control lines can select from up to 2ninput lines.
Block Diagram: Circuit Diagram:(8to1 mux)

E S2(X) S1(Y) S0(Z) M M = I(0)X'Y'Z' + I(1)X'Y'Z + I(2)X'YZ' + I(3)X'YZ +
1 0 0 0 I(0) I(4)XY'Z' + I(5)XY'Z +
I(6)XYZ' + I(7)XYZ
1 0 0 1 I(1)
1 0 1 0 I(2)
1 0 1 1 I(3)
1 1 0 0 I(4)
1 1 0 1 I(5)
1 1 1 0 I(6)
1 1 1 1 I(7)
0 X X X 0

module mux8_1 module mux (I,s,y);
input [7:0] I; input [2:0]s;
output [2:0] S; input [7:0]I;
output Y; output y;
input E; reg y;
reg Y; always@(I,s)
always @(E,S,I,Y); begin
begin case (s)
if (en= =1) 3'b000: y=I[0];
begin 3'b001: y=I[1];
if (s==000) Y=I[0]; 3'b010: y=I[2];
else if (s==001) Y=I[1]; 3'b011: y=I[3];
else if (s==010) Y=I[2]; 3'b100: y=I[4];
else if (s==011) Y=I[3]; 3'b101: y=I[5];
else if (s==100) Y=I[4]; 3'b110: y=I[6];
else if (s==101) Y=I[5]; 3'b111: y=I[7];
else if (s==110) Y=I[6]; default: y="z";
else if (s==111) Y=I[7]; endcase
end end
else Y=0; endmodule
end
end
endmodule
Wave form:
RESULT: The 8 to 1 multiplexer design have been realized and simulated using Verilog code.
APPLICATIONS:
Multiplexers are used in building digital semiconductors such as central processing units (CPUs) and
graphics controllers. They are also used in communications. cross bar switch, cellphone systems,
instrumentation, and any other function where only one transmission channel (e.g a radio transmitter) is
available. They mostly find in numerous and varied applications in digital systems of all types such as data
selection, data routing, operation sequencing, parallel -to-serial conversion, waveform generation and logic-
function generation
Program2d Date:___/____/_______
DE-MULTIPLEXER (1 TO 4)
Aim: Write a Verilog code to to realize 1 to 4 De-Multiplexer.
Theory:
The de-multiplexer takes one single input data line and then switches it to any one of the number of
individual output lines one at a time. The de-multiplexer converts a serial data signal at the input to a parallel
data at its output lines. The function of the 1 : 4 De-multiplexer is to switch one common data input line to any
one of the 4 output data lines.

X = ES1’S0’Y0 + ES1’S0Y1 + ES1S0’Y2 +
X E S1 S0 Y3 Y2 Y1 Y0 ES1S0Y3
1 0 0 0 0 0 0 1
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 1 0 0 0
0 1 X X 0 0 0 0
Verilog Code
module demux (s2,s1,I,E,y0,y1,y2,y3)
input s2,s1,I,E;
output y0,y1,y2,y3;
assign y0=(~s2)&(~s1)& I& E;
assign y1=(~s2)& s1& I& E;
assign y2=s2&(~s1)& I & E;
assign y3=s2& s1 & I & E;
endmodule
Wave form:
RESULT: The 1 to 4 De-multiplexer design have been realized and simulated using Verilog code.
APPLICATIONS:
De-multiplexers are used in Clock de-multiplexer, Security monitoring system, Synchronous data
transmission system
Program2e Date:___/____/_______
BINARY TO GRAY CODE CONVERTER

Aim: Write a Verilog code to to realize 4 bit Binary to Grey converter.
Theory:
The Gray code , by Frank Gray, is a binary numeral system where two successive values differ in only
one bit. The gray code is sometimes referred to as reflected binary, because the first eight values compare with
those of the last 8 values, but in reverse order. It is a non-weighted code; therefore, it is not a suitable for
arithmetic operations. It is a cyclic code because successive code words in this code differ in one bit position
only i.e. it is a unit distance code.

B3 B2 B1 B0 G3 G2 G1 G0 G3= B3
0 0 0 0 0 0 0 0 G2= B3’ B2 + B3 B2’= B3 XOR B2
0 0 0 1 0 0 0 1 G1= B1’ B2 + B1 B2’= B1 XOR B2
0 0 1 0 0 0 1 1 G0= B1’ B0 + B1 B0’= B1 XOR B0
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

module bin_gray(b,g);
input [3:0]b;
output [3:0]g;
reg [3:0]g;
always@ ( b)
begin
g[3]=b[3];
g[2]=b[2]^b[3];
g[1]=b[1]^b[2];
g[0]=b[0]^b[1];
end
endmodule
Wave form:
RESULT: The 4 bit binary to gray converter design have been realized and simulated using Verilog
code.
APPLICATIONS:
Gray codes are widely used to facilitate error correction in digital communications such as digital
terrestrial television and some cable TV systems.
Program2f Date:___/____/_______
BIT COMPARATOR
Aim: Write a Verilog code to to realize 2bit comparator.
Theory:
A digital comparator is a hardware electronic device that compares two numbers in binary form and
generates a one or a zero at its output depending on whether they are the same or not. A 2 bit comparator
compares two 2-bit binary, BCD, or other monotonic codes and presents the three possible magnitude results
at the outputs i.e., a>b, a<b, a=b.

Module comp(a,b,y1,y2,y3); module compare_2_bit (y1, y2, y3, a1, a0, b0, b1);
input [1:0] a,b; input a1, a0, b1, b0;
output y1,y2,y3; output z, x, y;
reg y1,y2,y3; assign y3= (~a1)&b1|(~a1)&(~a0)&b0|(~a0)&b1&b0;
assign y1= a1&(~b1)|a0&(~b1)&(~b0)|a1&a0&(~b0);
assign y2=
always @(a , b) (~a1)&(~a0)&(~b1)&(~b0)|(~a1)&a0&(~b1)&b0|a1&a0&b1&b0|a1
begin &(~a0)&b1&(~b0);
y1=0; y2=0; y3=0; endmodule
if(a==b)
y2=1’b1;
else if (a>b)
y1=1’b1;
else
y3=1’b1;
end
endmodule
Wave form:
RESULT: The 2 bit comparator design have been realized and simulated using Verilog code.
APPLICATIONS:
In mass production, where components are to be checked at a very fast rate. In selective assembly of
parts, where parts are graded in three or more groups depending upon their tolerance.
Program3 Date:___/____/_______
ALU
Aim: Write Verilog code describe the functions of a Arithmetic Logical Unit .
Theory:
The Arithmetic Logic Unit is the section of the CPU that actually performs add, subtract, multiply,
divide, and, or, floating point and other operations. The range of integer values that can be stored in 32 bits
is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GiB of
byte-addressable memory.
RESULT: 32 bit ALU operations have been realized and simulated using Verilog code.
APPLICATIONS:
Arithmetic Logic Unit is used extensively for Signal Processing and Control. It can be used in many
applications involving arithmetic operations. Many DSP and control applications require a small subset of
arithmetic operations that must be computed efficiently.
Program4 Date:___/____/_______
Flip Flop
Aim: Write Verilog code describe the functions of a flip flop .
Theory:
Block Diagram: (S,R Flip flop) Block Diagram: (J,K Flip flop)
Truth Table: Truth Table:

module sr_ff(sr ,clk ,reset,q ,qb ); module jk_ff( jk, clk, reset ,q ,qb );
input [1:0] sr; input [1:0] jk;
input clk, reset ; input clk, reset ;
output q,qb; output q,qb;
reg q,qb; reg q,qb;
always @ (posedge clk or posedge always @ ( posedge clk or posedge
reset) reset)
if (reset) if (reset)
begin begin
q = 1'b0; q = 1'b0;
qb = ~q; qb = ~q;
end end
else else
begin begin
case (sr) case (jk)
2'd0 : q = q; 2'd0 : q = q;
2'd1 : q = 1'b0; 2'd1 : q = 1'b0;
2'd2 : q = 1'b1; 2'd2 : q = 1'b1;
2'd3 : q = 1'bX; 2'd3 : q = ~q;
endcase endcase
qb = ~q; qb = ~q;
end end
endmodule endmodule
Wave form: SR Flip Flop
Wave form:j k Flip Flop
Block Diagram: (D Flip flop) Block Diagram: (T Flip flop)
Truth Table: Truth Table:
Verilog Code Verilog Code

module d_ff( d , clk , reset , q ,qb module t_ff( t, clk, reset, q, qb
); );
input d, clk, reset ; input t, clk, reset ;
output q,qb; output q,qb;
reg q,qb; reg q,qb;
always @ ( posedge clk or posedge
reset)
always @ ( posedge clk or posedge
if (reset) reset)
begin if (reset)
q = 1'b0; begin
qb=~q; q = 1'b0;
end qb=~q;
else end
begin else
q = d; if (t)
qb=~q;
end
begin
endmodule q = ~q;
qb = ~q;
end
endmodule
Wave form:D Flip Flop
Wave form: T Flip Flop
RESULT: Fliflop operations have been realized and simulated using Verilog code.
APPLICATIONS:
Program5 Date:___/____/_______
COUNTERS
Aim: Write Verilog code describe the functions of a Counter.
Theory:
Block Diagram: Block Diagram:

module bin_sync_4bit ( rst, clk, count); module bin_async_4bit ( rst, clk, count);
input rst,clk; input rst,clk;
output [3:0] count; output [3:0] count;
reg [3:0] count; reg [3:0] count;
initial
initial
begin
begin
count = 4'b0000;
end count = 4'b0000;
always @(posedge clk) end
if(rst) always @(posedge clk or posedge rst)
count = 4'b0000; if(rst)
else count = 4'b0000;
count = count + 4'b0001; else
endmodule count = count + 4'b0001;
endmodule
Block Diagram: Block Diagram: (T Flip flop)

module bcd_sync ( rst, clk, count); module bcd_async ( rst, clk, count);
input rst,clk; input rst,clk;
output [3:0] count; output [3:0] count;
reg [3:0] count; reg [3:0] count;

initial initial
begin begin
count = 4'd0; count = 4'd0;
end
end
always @(posedge clk)
always @(posedge clk or posedge rst)
if(rst)
count = 4'd0; if(rst)
else if(count < 4'd9 ) count = 4'd0;
count = count + 4'd1; else if(count < 4'd9 )
else count = count + 4'd1;
count = 4'd0; else
endmodule count = 4'd0;
endmodule
module any_seq_bin ( rst,load, clk,din,updown, count);

input rst,clk,updown,load;
input [3:0] din;
output [3:0] count;
reg [3:0] count;
always @(posedge clk)
if(rst)
count = 4'b0000;
else if(load)
count = din;
else if (updown)
count = count + 4'b0001;
else
count = count - 4'b0001;
endmodule
RESULT:
APPLICATIONS:
1. Counters are also used in Frequency counters, Digital clock, Time measurement, A to D converter, Frequency
divider circuits and Digital triangular wave generator.
2. Many automation systems use PC and laptops to monitor different parameters of machines and production data.
Counters may count parameters such as the number of pieces produced, the production batch number, and
measurements of the amounts of material used.
Program6 Date:___/____/_______
FULL ADDER
Aim: Write HDL code to describe the functions of a full Adder Using three modeling styles..
Theory: A Full Adder is a combinational circuit that performs the arithmetic sum of three input bits.
It consists of three inputs and two outputs. Three of the input variables can be defined as a, b, c and
the two output variables can be defined as Sum, Cout. The two input variables that we defined earlier
A and B represents the two significant bits to be added. The third input ‘c’ represents the carry bit.
Two digits arte to be used because the arithmetic sum of the three binary digits needs two digits.
The two outputs represents Sum for sum and Cout for carry.For designing a full adder circuit, two
half adder circuits and an OR gate is required. It is the simplest way to design a full adder circuit. For
this two XOR gates, two AND gates, one OR gate is required.
RESULT : Three modeling styles of full adder have been realized and
simulated using HDL codes.
APPLICATIONS :
Adders are basically used in calculators. They are used in all processors –
micrprocessors and microcontrollers and also DSP processors.
Part –B
Interfacing Programs
1. Write a VHDL code to control speed, direction of Stepper motor.

Aim: To control Speed and Direction of Stepper motor.
Procedure:
1. Make the connection between FRC9 of the FPGA board to the Stepper motor
connector of the VTU card2.
2. Make the connection between FRC7 of the FPGA board to the Keyboard
3. Make the connection between FRC1 of the FPGA board to the Dip switch
4. Connect the downloading cable and power supply to the FPGA board.
5. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial
mode and select the respective BIT file and click program.
6. Make the reset switch on (active low).
7. Press the HEX keys and analyze the speed changes.
VHDL CODING
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STEPPERnew is
Port ( dout : out std_logic_vector(3 downto 0);
clk,reset: in std_logic;
row:in std_logic_vector(1 downto 0);
dir:in std_logic);
end STEPPERnew;
architecture Behavioral of STEPPERnew is

signal clk_div : std_logic_vector(25 downto 0);
signal clk_int: std_logic;
signal shift_reg : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
clk_div <= clk_div + '1';
end if;
end process;
clk_int<=clk_div(21) when row="00"else
clk_div(19) when row="01"else
clk_div(17) when row="10"else
clk_div(15) ;
process(reset,clk_int,dir)
begin
if reset='0' then
shift_reg <= "1001";
elsif rising_edge(clk_int) then
if dir='0' then
shift_reg <= shift_reg(0) & shift_reg(3 downto 1);
else
shift_reg<=shift_reg(2 downto 0) & shift_reg(3); end if;
end if;
end process;
dout <= shift_reg;
end Behavioral;
UCF file (User constraint File)
NET "clk" LOC = "p52" ;
NET "dir" LOC = "p76" ;
NET "dout<0>" LOC = "p141" ;
NET "dout<1>" LOC = "p2" ;
NET "reset" LOC = "p74" ;
NET "row<0>" LOC = "p77" ;
NET "row<1>" LOC = "p79" ;
2. Write a VHDL code to control speed, direction of DC motor.

Aim: To control Speed and Direction of DC motor.
Procedure:
1. Make the connection between FRC9 of the FPGA board to the DC motor
2. Make the connection between FRC7 of the FPGA board to the Keyboard
7. Press the HEX keys and analyze the speed changes.
VHDL CODING
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dc_motor is
port(clk,rst,dir:in std_logic;
rly:out std_logic;
pwm:out std_logic_vector(1 downto 0);

pwm1:out std_logic_vector(1 downto 0);
keys:in std_logic_vector(3 downto 0));
end dc_motor;
architecture behavioral of dc_motor is

signal div:std_logic_vector(16 downto 0);
signal clkdiv:std_logic;
signal counter:std_logic_vector(7 downto 0);
signal dc:integer range 0 to 255;
signal tick:std_logic;
begin
process(clk) is
begin
if (rising_edge (clk)) then
div<=div+1;
end if;
end process;
clkdiv<=div(12);
tick<=keys(0) and keys(1)and keys(2) and keys(3);
process(tick) is
begin
if (falling_edge (tick)) then
case (keys) is
when "1110"=>dc<=50;
when "1101"=>dc<=20;
when "1011"=>dc<=10;
when "0111"=>dc<=5;
when others=>dc<=5;
end case;
end if;
end process;
process (clkdiv,rst) is
begin
if dir='1' then
if( rst='1') then
counter<="00000000";
pwm<="01";
elsif (rising_edge(clkdiv)) then
counter<=counter+1;
if (counter >=dc)then
pwm(1)<='0';
else
pwm(1)<='1';
end if;
end if;
else
if( rst='1') then

counter<="00000000";
pwm1<="10";
elsif (rising_edge(clkdiv)) then
counter<=counter+1;
if (counter >=dc)then
pwm1(0)<='0';
else
pwm1(0)<='1';
end if;
end if;
end if;
end process;
rly<=dir;
end Behavioral;
//ucf file

NET "dir" LOC = "p74" ;
NET "keys<0>" LOC = "p69" ;
NET "pwm1<0>" LOC = "p5" ;
NET "pwm1<1>" LOC = "p2" ;
NET "pwm<0>" LOC = "p4" ;
NET "pwm<1>" LOC = "p141" ;
NET "rly" LOC = "p44" ;
NET "rst" LOC = "p76" ;
3a. Write a VHDL code to generate Sine waveforms using DAC change the
frequency and amplitude.
Aim: To generate Sine wave using DAC change the frequency and amplitude.
Procedure:
1. Make the connection between FRC5 of the FPGA board to the DAC connector
of
the VTU card2.
connector of the
VTU card2.
mode and
select the respective BIT file and click program.
5. Make the reset switch on (active low) and analyze the data.
VHDL CODING
library IEEE;
entity digital_sine_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end digital_sine_wave ;
architecture Behavioral of digital_sine_wave is

signal temp : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;

end if;
end process;
process(temp(3))
begin
if rst='1' then
counter <= "00000000";
elsif rising_edge(temp(3)) then
if counter<255 and en='0' then
counter <= counter + 31 ;
en<='0';
elsif counter=0 then
en<='0';
else
en<='1';
counter <= counter - 31;
end if;
end if;
end process;
dac_out <=counter; end Behavioral;
UCF file(User constraint File)

NET "dac_out<0>" LOC = "p21" ;
3.b Write a VHDL code to generate Square waveforms using DAC change the
Aim: To generate Square wave using DAC change the frequency and amplitude.
Procedure:
of
the VTU card2.
VHDL CODING
--- Square wave

library IEEE;
entity DAC_Square is
Port ( clk : in STD_LOGIC; -- 4MHz XTL_CLK
rst : in STD_LOGIC;
dac_out : out STD_LOGIC_VECTOR ( 7 downto 0 ));
end DAC_Square;
architecture Behavioral of DAC_Square is

signal count : std_logic_vector (7 downto 0);
begin
process (clk, rst, count)

begin
if(rst='1') then
count <="00000000";
elsif rising_edge(clk) then

count <= count + 1;
end if;
if (count(7) = '1') then
dac_out <= "11111111";
else
dac_out <= "00000000";
end if;
end process;
end Behavioral;
ucf File
3c. Write a VHDL code to generate Traingular waveforms using DAC change the
Aim: To generate Triangular wave using DAC change the frequency and
amplitude.
Procedure:
of
the VTU card2.
VHDL CODING
----triangular wave
library IEEE;
entity triangular_wave is
rst : in std_logic;
end triangular_wave ;
architecture Behavioral of triangular_wave is

signal div : std_logic_vector(3 downto 0);
begin
process(clk)
begin
div <= div + '1' ;
end if;
end process;
process(div(3))
begin
if rst='1' then
counter <= "000000000";
elsif rising_edge(div(3)) then
if counter(0)='1' then
dac_out <=counter(1 to 8);
else
dac_out <=not(counter(1 to 8));
end if;
end if;
end process;
end Behavioral;
//ucf
3d. Write a VHDL code to generate Ramp waveforms using DAC change the
Aim: To generate Ramp wave using DAC change the frequency and amplitude.
Procedure:
of
the VTU card2.
VHDL CODING
library IEEE;
entity ramp_wave is
rst : in std_logic;
end ramp_wave;
architecture Behavioral of ramp_wave is

signal div : std_logic_vector(3 downto 0);
begin
process(clk)
begin
div<= div+ '1' ;
end if;
end process;
process(div)
begin
if rst='1' then
counter <= "00000000";
elsif rising_edge(div(3)) then

counter <= counter + 15 ; --for –ve ramp give -15
end if;
end process;
dac_out <=counter;
end Behavioral;
//ucf file
v
3e. Write a VHDL code to generate Sawtooth waveforms using DAC change the
.
Procedure:
1. Make the connection between FRC5 of the FPGA board to the DAC connector of
the VTU card2.
2. Make the connection between FRC1 of the FPGA board to the Dip switch connector
of the VTU card2.
4. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode
and
select the respective BIT file and click program.
VHDL CODING
library IEEE;
entity swatooth_wave is
rst : in std_logic;
end swatooth_wave;
architecture Behavioral of swatooth_wave is
signal temp : std_logic_vector(3 downto 0);
begin
process(clk)
begin
temp <= temp + '1' ;
end if;
end process;
process(temp(3))
begin
if rst='1' then
counter <= "00000000";
elsif rising_edge(temp(3)) then

end if;
end process;
dac_out <=counter;
end Behavioral;
UCF file (User constraint File)

4. Write VHDL code to display messages on the given seven segment display
accepting Hex key pad input data.
Write VHDL code to display messages on the given seven segment display accepting Hex key pad input
data.
Aim: To Display the message on the Seven Segment Display by accepting HEX key pad input Data.
Procedure:
1. Make the connection between FRC5 of the FPGA board to the Seven Segment connector of the VTU card1.
2. Make the connection between FRC4 of the FPGA board to the Key board connector of the VTU card1.
3. Make the connection between FRC6 of the FPGA board to the Dip switch connector of the VTU card1.
5. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective
BIT file and click program.
7. Press the HEX keys and analyze the data.
library IEEE;
entity keypad_led_display is
Port ( clk : in STD_LOGIC;
key_rl : in BIT_VECTOR (3 downto 0);
key_sc : out BIT_VECTOR (3 downto 0);
seg_out : out STD_LOGIC_VECTOR (6 downto 0));
end keypad_led_display;
architecture Behavioral of keypad_led_display is
signal clk_div:std_logic_vector(12 downto 0); -- 2 msec delay, 4Mhz clock source / 8 KHz = 500Hz ( = 2
msec)
signal key_sc_temp :bit_vector(3 downto 0):="0001"; -- 2 ^ 13 = 8KHz, 12 downto 0
begin
process(clk)
begin
if(clk'event and clk = '1') then
clk_div <= clk_div + '1';
end if;
end process;
process(clk_div(12))
begin
if (clk_div(12)'event and clk_div(12) = '1') then
key_sc_temp <= key_sc_temp rol 1;
end if;
key_sc <= key_sc_temp;
end process;
process(key_rl,clk_div(12))
begin
if (clk_div(12)'event and clk_div(12) = '1') then
if (key_sc_temp="0001" and key_rl="0001") then seg_out <= "1111110"; --1
elsif (key_sc_temp="0001" and key_rl="0010") then seg_out <= "0110011";
elsif (key_sc_temp="0100" and key_rl="0010") then seg_out <= "1011111"; --A
elsif (key_sc_temp="1000" and key_rl="1000") then seg_out <= "1000111"; --0
end if;
end if;
end process;
end Behavioral;
UCF file (User constraint file)
NET "clk" LOC = "p52";
NET "disp_cnt<0>" LOC = "p23";
NET "disp<0>" LOC = "p18";
NET "read_l_in<0>" LOC = "p112";
NET "scan_l<0>" LOC = "p123";
5. Write a VHDL code to test Elevator operation:

1. Make the connection between FRC4 to of the FPGA board to the LED
connector of
the VTU card2.
3. Make the connection between FRC5 of the FPGA board to the Seven Segment
VHDL CODING
library IEEE;
entity elev is
port(floor: in std_logic_vector(7 downto 0);
clk:in std_logic;
led_out: out std_logic_vector(7 downto 0):="00000000";
seg:out std_logic_vector(6 downto 0):="1111110";
dis:out std_logic_vector(3 downto 0));
end elev;
architecture elev_arch of elev is

signal sclk:std_logic_vector(21 downto 0);
signal nclk:std_logic;
begin
process(clk)
begin
if(rising_edge(clk)) then
sclk <= sclk+1;
end if;
end process;
nclk <= sclk(20);
process(nclk)
variable nxt:std_logic_vector(7 downto 0):="00000001";
variable temp:std_logic_vector(7 downto 0):="00000001";
begin
if(rising_edge(nclk)) then
dis<="1110";
if(floor>nxt ) then
case nxt is
when "00000001" => nxt:= "00000010";seg<="0110000";
when "00000010" => nxt:= "00000100";seg<="1101101";
when "00000100" => nxt:= "00001000";seg<="1111001";
when "00001000" => nxt:= "00010000";seg<="0110011";
when "00010000" => nxt:= "00100000";seg<="1011011";
when "00100000" => nxt:= "01000000";seg<="1011111";
when "01000000" => nxt:= "10000000";seg<="1110000";
when others => null;
end case;
temp := nxt;
led_out <= temp;
end if;
if(floor < nxt)then
nxt:= temp;
case nxt is
when "10000000" => nxt:= "01000000";seg<="1011111";
when "01000000" => nxt:= "00100000";seg<="1011011";
when "00100000" => nxt:= "00010000";seg<="0110011";
when "00010000" => nxt:= "00001000";seg<="1111001";
when "00001000" => nxt:= "00000100";seg<="1101101";
when "00000100" => nxt:= "00000010";seg<="0110000";
when "00000010" => nxt:= "00000001";seg<="1111110";
when others => null;
end case;
temp := nxt;
led_out <= temp;
end if;
end if;
end process;
end elev_arch;

NET "floor<0>" LOC = "p100";
NET " floor <1>" LOC = "p102";

NET " floor <5>" LOC ="p107";
NET "seg<0>" LOC = "p18";
NET "sep<2>" LOC = "p15";
NET "segp<5>" LOC ="p12";
NET "led_out<0>" LOC = "p112";
NET " led_out <1>" LOC = "p116";
NET " led_out <5>" LOC ="p131";
Extra programs
6. Write VHDL code to display messages on the given seven segment display
library IEEE;
entity msg is
port(clk:in std_logic;
seg:out std_logic_vector(6 downto 0);
disp: out std_logic_vector( 3 downto 0));
end msg;
architecture Behavioral of msg is

signal sclk:std_logic_vector(21 downto 0);
signal nclk:std_logic;
begin
process(clk)
begin
if(rising_edge(clk)) then
sclk <= sclk+1;
end if;
end process;
nclk <= sclk(10);
process(nclk)
variable temp:std_logic_vector(1 downto 0):="00";
begin
if(rising_edge(nclk))then
case temp is
when "00"=>disp<="1110";seg<="0110111";
when "01"=>disp<="1101";seg<="0111101";
when "10"=>disp<="1011";seg<="0001110";
when others=>null;
end case;
temp:=temp+1;
end if;
end process;
end Behavioral;

NET "sep<2>" LOC = "p15";
NET "segp<5>" LOC ="p12";
7. Write a VHDL code to control external lights using relays.

Aim: To control external lights using relays.
Procedure:
1. Make the connection between FRC9 of the FPGA board to the External light
VHDL CODING
library IEEE;
entity extlight is
Port ( cntrl1,cntrl2 : in std_logic;
light : out std_logic);
end extlight;
architecture Behavioral of extlight is

begin
light<= cntrl1 OR cntrl2 ;
end Behavioral;
UCF file(User constraint

NET "cntrl1" LOC = "P74";
NET "cntrl2" LOC = "P76";
NET "light" LOC = "P5";
Viva Quetions
BASIC GATES
1. What is HDL & What are the types of HDL’S.
2. Mention the different basic gates.
3. Mention the different Universal gates.
4. Mention the different Application gates.
5. What is De-Morgan's Law?
6. What is the practical application of the De-Morgan's Law
7. Write a program to realize the behavior of Xor gate using nand gates only.
8. What is the difference between Buffer and Inverter?
9. Expand VHDL & Verilog.
10. What is the difference between std_logic & bit data type.
11. What is the combinatorial circuit?
12. Representation of Different gates in VHDL & Verilog.
13. What is the difference between Keyword & a Identifier.
DECODER
1. What is a Decoder?
2. Difference between Decoder & encoder.
3. What is the use of designing Decoder using Logic gates?
4. Write a program to design Decoder in Data Flow description
5. Write a program to design Decoder with enable input and mention its advantages.
ENCODER
1. What is a Encoder?
2. What are the disadvantages of Encoder without Priority?
3. What are the types of Encoders.
4. What is Shaft Encoding?
5. Design a 16-4 line HEX keypad encoder to output 0000 when key 0 is pressed, 0001
when key 2 is pressed , 1010 when key A is pressed 101 when key B is pressed and so on.
6. Write the VHDL& Verilog program to design a 4:2 encoder with Data flow description.
MULIPLEXER
1. What is a Multiplexer?
2. What are the applications of Multiplexer?
3. Write the VHDL& Verilog program to design 2:1 Multiplexer with Data flow description.
4. What is the practical application of a Multiplexer?
5. How a Multiplexer can be used in a Communication systems?
DE-MULIPLEXER
1. What is a De-Multiplexer?
2. What are the applications of De-Multiplexer?
3. Write the VHDL& Verilog program to design 1:4 Multiplexer with Data flow description.
4. What is the practical application of a De-Multiplexer?
5. How a De-Multiplexer can be used in a Communication systems?
COMPARATOR
1. What is a Comparator?
2. What are the applications of Comparator?
3. Write the VHDL& Verilog program to design 2-bit Comparator with Data flow description.
4. What are the types of Comparators?
5. What is the use of Magnitude Comparator.
CODE CONVERTERS
1. Why we need code converters?

2. What are the applications of gray code, Excess-3 code & Binary code converters?
3. Write the VHDL& Verilog program to design Excess-3 code converter in Behavioral model.
4. What are the types of Code converters?
ADDERS
1. What is the Adder?

2. What are the types of Adders?
3. Write the VHDL& Verilog program to design a Full adder using 2 Half adders & a or gate in
Behavioral, Data flow & Structural model.
4. What is the advantage of Carry look ahead adder?
5. What are the applications of Adders.
6. Design a Full Adder using a Decoder?
7. Write the VHDL& Verilog program to design a Full adder using 2 Half adders & a or gate in
Behavioral, Data flow & Structural model.
8. What is the advantage of Carry look ahead adder?
9. What are the applications of Adders
FLIP-FLOP
1. What are Combinational Circuits and Sequential Circuits and their differences.
2. Define Synchronous Sequential circuits & Asynchronous Sequential circuits
3. What is the Latch?
4. What is the FLIP-FLOP?
5. What are the types of FLIP-FLOP?
6. Draw the functional table for SR, JK, T & D flip flops.
7. How to avoid race around condition using MS-JK flip flop?
8. Draw the circuit of SR Latch.
1. Explain it.
2. Truth Table, Characteristic Table, Excitation Table - SR Flip-Flop, JK Flip Flop
3. Implement D-Latch by JK Flip Flop. Explain the circuit.
9. Explain Clocked latch.

10. Explain the difference between Truth Table, Characteristic Table, Excitation Table,
Transistion table & State table.
11. Define State diagram.
12. How SR Flip flop is used as a Switch debouncer.
13. Explain the Toggle condition in JK flip flop.
COUNTERS
1. What is a Counter? What are the different types of Counters?
2. Explain Synchronous Counter & Asynchronous Counter.
3. What is a decade counter? What are the uses of it?
4. What are the applications of Synchronous Counter& Asynchronous Counter.
5. Explain the difference between Melay Model & Moore Model.
6. What are the advantages of Melay Model & Moore Model?
7. What is Sequence generator? Where it is used?
8. What is Register? Mention Classification of Shift Registers.
Appendix
1. Write the VHDL representation of Half-Subtractor in Behavioral & Structural models.
entity half_sub is
Port ( a,b : in std_logic;
diff,borrow : out std_logic);
end half_sub;
architecture data of half_sub is

begin
Diff <=a xor b ;
borrow <= ( not a and b);
end data;
entity half_struct is
Port ( a,b : in std_logic;
x : inout std_logic;
diff,borr : out std_logic);
end half_struct;
architecture half_struct of half_struct is

component and2
Port(i1,i2: in std_logic;
o1: out std_logic);
end component;
component inv
Port(i1: in std_logic;
o1: out std_logic);
end component;
component xor2
o1: out std_logic);
end component;
--signal x;
for all: xor2 use entity xor2(xor2_0);
for all: inv use entity inv(inv_0);
begin
X1: xor2 port map (a,b,diff);
A1: and2 port map (x,b,borr);

I: inv port map (a,x);
end half_struct;
library IEEE;
Entity and2 is
o1: out std_logic);
end and2;
Architecture and2_0 of and2 is
Begin
o1<= i1 and i2;
end and2_0;
library IEEE;
Entity inv is
o1: out std_logic);
end inv;
Architecture inv_0 of inv is
Begin
o1<= not i1;
end inv_0;
library IEEE;
Entity xor2 is
o1: out std_logic);
end xor2;
Architecture xor2_0 of xor2 is
Begin
o1<= i1 xor i2;
end xor2_0;
2. Write the VHDL & Verilog representation of Full Adder using 2 Half-adders in Structural
model.
entity full_struct is
Port ( a,b,c : in std_logic;
x,y,z : inout std_logic;
sum, cout : out std_logic);
end full_struct;
architecture fa_struct of full_struct is

component ha
o1,o2: out std_logic);
end component;
component or2
o1: out std_logic);
end component;
for all: or2 use entity or2(or2_0);
begin
ha1:ha port map (a,b,x,y);
ha2: ha port map (x,c,sum,z);
O1: or2 port map (y,z,cout);
end fa_struct;
library IEEE;
Entity ha is
end ha;
Architecture ha_0 of ha is
Begin
o1<= i1 xor i2;
o2<= i1 and i2;
end ha_0;
library IEEE;
Entity or2 is
o1: out std_logic);
end or2;
Architecture or2_0 of or2 is
Begin
o1<= i1 or i2;
end or2_0;
module fa_struct (a,b,c,sum,cout) ;

input a,b,c;
output sum,cout;
wire x,y,z;
ha x1 (a,b,x,y);
ha x2 (x,c,sum,z);
or o2 (y,z,cout);
endmodule
module ha (a,b,sum,cout) ;
input a,b;
output sum,cout;
assign sum= a ^ b;
assign cout= a & b;
endmodule
3. Write the VHDL & Verilog representation of Full Subtractor using 2 Half-Subtractors in
Structural model.
entity full_sub is
Port ( a,b,c : in std_logic;
x,y,z : inout std_logic;
diff,bor : out std_logic);
end full_sub;
architecture fa_sub of full_sub is

component hs
end component;
component or2
o1: out std_logic);
end component;
for all: or2 use entity or2(or2_0);
begin
hs1:hs port map (a,b,x,y);
hs2: hs port map (x,c,diff,z);
O1: or2 port map (y,z,bor);
end fa_sub;
library IEEE;
Entity hs is

end hs;
Architecture hs_0 of hs is
Begin
o1<= i1 xor i2;
o2<=(not i1 )and i2;
end ha_0;
library IEEE;
Entity or2 is
o1: out std_logic);
end or2;
Architecture or2_0 of or2 is
Begin
o1<= i1 or i2;
end or2_0;
library IEEE;
Entity inv is
o1: out std_logic);
end inv;
Architecture inv_0 of inv is
Begin
o1<= not i1;
end inv_0;
4. Write a VHDL & Verilog Program to solve the following Boolean expressions.
1.f1(a,b,c)=∑(2,4,5,6,7)
2.f2(a,b,c)=Π(1,4,5,6)
1) After simplifying the miminal expression by K-map technique f= a + b’c

entity fun1 is
port(a,b,c: in Std_logic;
f:out std_logic);
end fun1;
architecture Behavioral of fun1 is

begin
f<=a or ( not b and c);
end Behavioral;
module fun1_v(a,b,c,f) ;
input a,b,c;
output f;
assign f= a |( ~b& c);
endmodule
2) After simplifying the maximal expression by K-map technique f= a’c’ + bc
entity fun2 is
port(a,b,c: in Std_logic;
f:out std_logic);
end fun2;
architecture Behavioral of fun2 is

begin
f<=(not a and not c) or ( b and c);
end Behavioral;
module fun2_v(a,b,c,f) ;
input a,b,c;
output f;
assign f= (~a& ~c) |( b& c);
endmodule
5. Write the VHDL representation of 3 to 8 line Decoders Behavioral model.

entity decoder3_8 is
port( din : in STD_LOGIC_VECTOR(2 downto 0);
dout : out STD_LOGIC_VECTOR(7 downto 0) );
end decoder3_8;
architecture decoder3_8_arc of decoder3_8 is

begin
dout <= ("10000000") when (din="000") else
("01000000") when (din="001") else
("00100000") when (din="010") else
("00010000") when (din="011") else
("00001000") when (din="100") else
("00000100") when (din="101") else
("00000010") when (din="110") else
("00000001") ;
end decoder3_8_arc;
6. Write the VHDL & Verilog representation of Mod-6 up-down counter.

entity mod6_syn_reset is
Port ( d : in STD_LOGIC_VECTOR (2 downto 0);
q : inout STD_LOGIC_VECTOR (2 downto 0);
clk,reset,p : in STD_LOGIC);
end mod6_syn_reset;
architecture Behavioral of mod6_syn_reset is

begin
process(clk)
begin
if (rising_edge(clk)) then
if(reset = '1')then
q<="000";
elsif (p='1')then
q<=q+1;
if(q="101")then
q<="000";
end if;
else
q<=q-1;
if(q="000")then
q<="101";
end if;
end if;
end if;
end process;
end Behavioral;
module mod_syn_v(clk,reset,p,q,d);
input clk,reset,p;
input [2:0]d;
output [2:0]q;
reg [2:0]q;
always@(posedge(clk))
begin
if (reset==1)
q=3'b000;
else if (p==1)
begin
if(q==3'b101)
q=3'b000;
else
q=q+1;
end
else
begin
if(q==3'b000)
q=3'b101;
else
q=q+1;
end
end
endmodule
7. Write the VHDL & Verilog representation of 4-bit Magnitude comparator Behavioral model.
entity question2 is
port(
a,b :in integer range 0 to 31;
a2,b2,c2,d2,e2,f2,g2: out std_logic);
end question2;
architecture compare of question2 is
signal compares : std_logic_vector(2 downto0);
signal outputs : std_logic_vector(6 downto0);
begin
process (a,b)
begin
if a<b then
compares <= "001";
elsifa=b then
compares <= "010";
elsifa>b then
compares <= "100";
else
compares <= "000";
end if;
end process;
with compares select outputs <=
"1110001" when "001”
"0110110" when "010",
"0001001" when "100",
"1111111" when others;
a2 <= outputs(6);
b2 <= outputs(5);
c2 <= outputs(4);
d2 <= outputs(3);
e2 <= outputs(2);
f2 <= outputs(1);
g2 <= outputs(0);
end compare;
8. Write the VHDL representation of 4-bit Ripple carry Adder in Behavioral model.
entity RCA is
port(a, b : in std_logic_vector(3 downto 0);
cout : out std_logic;
sum : out std_logic_vector(3 downto 0));
end entity RCA;
architecture struct_RCA of RCA is

signal cin: std_logic_vector(3 downto 0);
component FA is
port(a, b : in std_logic;
cin : in std_logic;
sum : out std_logic);
end component;
begin
cin(0) <= '0';
FA0 : FA port map(a(0), b(0), cin(0), cin(1), sum(0));
FA3 : FA port map(a(3), b(3), cin(3), cout, sum(3));
end architecture struct_RCA;
library IEEE;
entity FA is
port(a, b : in std_logic;
c: in std_logic;
sum : out std_logic);
end entity FA;
architecture df_FA of FA is
begin
cout <= (a and b) or (b and c) or (c and a);
sum <= a xor b xor c;
end architecture df_FA;
9. Write the Verilog representation of MS-JK Flip-Flop in Behavioral model.

module msjk_ff(clk,j,k,reset,q,qb);
input clk,reset,j,k;
output q,qb;
wire p,r;
jk_ff u1(.clk(clk),.reset(reset),.j(j),.k(k),.q(p),.qb(r));
jk_ff u2(.clk(~clk),.reset(reset),.j(p),.k(r),.q(q),.qb(qb));
endmodule
module jk_ff(clk,j,k,reset,q,qb);
input clk,j,k,reset;
output reg q,qb;
always@(posedge clk)
begin
if(reset)
q=1'b0;
else
case({j,k})
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule

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C. Byregowda Institute of Technology: HDL Lab Manual

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C.

DEPT. OF ELECTRONICS & COMMUNICATION

Lab In charge’s : Mrs. SUJANI G

Scrutinized By : Mrs. SUJANI G

Approved By : Dr. SREERAMA REDDY G.M

Assisted by: Mr. Srikanth

02a Realize 2 to 4 Decoder, 3

02b Realize 8to 3 Encode 5

02c Realize 8to 1 Mux 7

02d Realize 1to 4 Dmux 9

02e Realize Binary to Gray 11

02f Realize bit Comparator 13

05 4 bit binary, BCD counters, any sequence counter 20

06 Full Adder using three modeling styles 22

All logic gates

Circuit Diagram and Truth table:

Block Diagram: Circuit Diagram:

Truth Table: Boolean Expression:

Verilog Code Alternate Code

Decoding is necessary in applications such as data multiplexing, 7 segment display and

Block Diagram: Circuit Diagram:

Verilog Code (WITHOUT PRIORITY) Verilog Code (WITH PRIORITY)

Block Diagram: Circuit Diagram:(8to1 mux)

Truth Table: Boolean Expression:

Verilog Code Alternate Code

Block Diagram: Circuit Diagram:(8to1 mux)

Truth Table: Boolean Expression:

BINARY TO GRAY CODE CONVERTER

Block Diagram: Circuit Diagram:(8to1 mux)

Truth Table: Boolean Expression:

Verilog Code Alternate Code

Block Diagram: Circuit Diagram:(8to1 mux)

Truth Table: Boolean Expression:

Verilog Code Alternate Code

Truth Table: Truth Table:

Verilog Code Alternate Code

Wave form:j k Flip Flop

Block Diagram: (D Flip flop) Block Diagram: (T Flip flop)

Truth Table: Truth Table:

Verilog Code Verilog Code

Wave form: T Flip Flop

Verilog Code Verilog Code

Block Diagram: Block Diagram: (T Flip flop)

Verilog Code Verilog Code

reg [3:0] count; reg [3:0] count;

module any_seq_bin ( rst,load, clk,din,updown, count);

1. Write a VHDL code to control speed, direction of Stepper motor.

architecture Behavioral of STEPPERnew is

2. Write a VHDL code to control speed, direction of DC motor.

pwm:out std_logic_vector(1 downto 0);

architecture behavioral of dc_motor is

tick<=keys(0) and keys(1)and keys(2) and keys(3);

if( rst='1') then

NET "clk" LOC = "p52" ;

architecture Behavioral of digital_sine_wave is

temp <= temp + '1' ;

UCF file(User constraint File)