Computer Science 421 Fall 2019

Computer Architecture

Lecture : 9 -13
Types of Memories;
Cache, Internal and External

Saad A. Malik
saad.ali@namal.edu.pk
 Lecture Outline

● Overview
● Cache memory
● Internal memory
● External memory

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 Computer System Memory Overview

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 Overview
➢ Although seemingly simple in concept, computer memory
exhibits perhaps the widest range of type, technology,
organization, performance, and cost of any feature of a
computer system.

➢ No one technology is optimal in satisfying the memory

requirements for a computer system.

● As a consequence, the typical computer system is equipped

with a hierarchy of memory subsystems, some internal to
the system (directly accessible by the processor) and some
external (accessible by the processor via an I/O module).

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 Chapter 4
Cache Memory

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 Cache Memory Principles

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 Structure of Cache Memory

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Cache Read Operation

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 Cache Organization

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 Elements of Cache Design

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 Introduction

● Caches performances are generally referred to

in High Performance Computing (HPC)
applications.
– Many researchers have found that HPC applications
perform poorly on computer architectures that employ
caches [BAIL93].
– Other researchers have since shown that a cache
hierarchy can be useful in improving performance if
the application software is tuned to exploit the cache
[WANG99, PRES01].

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Although there are a large number of cache implementations, but there are a few
basic design elements that serve to classify and differentiate cache architectures.
Table 4.2 lists key elements.

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 Cache Addresses

●
Virtual Memory
– Address fields of machine instructions contain virtual addresses
– A hardware memory management unit translates each virtual
address to physical address in main memory
– We shall not cover this topic in detail
● Physical Memory
– Map each line to a physical memory address
– A memory translation is required
– Placement of the memory translation becomes the bone of
contention

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 Cache Size

● Desirable
– Size of cache large enough or small enough
– Access time
– Cost per bit
● Large caches tend to be slower, because of
address translations
● Available chip and board area limits the size

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 Replacement Algorithms

● Problem:
– When a new block of memory is brought into a
cache, one of the existing blocks must be replaced
● Possible Solutions:
– Least Recently Used (LRU)
– First in First Out (FIFO)
– Least Frequently Used (LFU)

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 Write Policy

● If a word has been updated in Cache and not in main memory, which
memory should be updated
– The problem of identifying validity of word
● e.g. I/O device has changed word in main memory, where as instruction
changed the word in cache. Which is valid?
● e.g. when multiple processors are attached to the same bus and have own
local caches
– Then a write by one processor can invalidated other words
● Write Through
– All write operations are carried out in main memory as well as cache
– Add a new processor-cache monitoring module to maintain consistency of local
cahce
– This technique might cause

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 Write Policy - Techniques

● Write through
– Main and Cache memory are simultaneously written
– DisAdv : substantial memory traffic is generated
● Write Back
– To minimize memory writes, updates only cache
– Concept of dirty bit or use bit, associated with line is
set
● Case Scenario: Bus organization
– How to maintain cache coherency?

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 Line Size

● The size of Line incorporates

– The data block,
– The validity bit, dirty bit
– The address field (in case of set-
associative)
– In case of direct addressing no additional
fields need storage

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 Number of Caches

● Single or Multi Level

– Logic density increase
– Larger or multiple caches are possible
● Onchip vs Offchip Cache?

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Table 4.3 continued ..

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 Memory Mapping

● Direct Mapping
● Associative Mappings
● Set-associative Mapping

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 Key Terms

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 Recommended Readings

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 End of Lecture

Questions and Answers

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 Next Lecture

● Cache Mapping Functions

● Example Caches
– Intel
– ARM

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 Internal Memory

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 Memory Organization

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 Packaging

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 Memory Organization

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 Memory Organization

● In the case in which larger memory is required, an array of chips is needed. Figure 5.6 shows the possible
organization of a memory consisting of 1M word by 8 bits per word.
● In this case, we have four columns of chips, each column containing 256K words arranged as in Figure 5.5.
● For 1M word, 20 address lines are needed. The 18 least significant bits are routed to all 32 modules. The
high-order 2 bits are input to a group select logic module that sends a chip enable signal to one of the four
columns of modules.

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 SDRAM
● Synchronous Data RAM
●

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 DDR

● SDRAM restricted to send data

once per bus clock cycle
● Double Data rate (DDR)
SDRAM overcomes this
restriction by sending data on
both rising and falling edge of
the clock.

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 DRAMS Performance

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 Key Terms

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 Recommended Readings

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 External Memory

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 Types

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 Magnetic Disk

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 Read Write Mechanism

● Watch video

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 Layout of Data

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 Winchester Disk format
(HDD in PCs are mostly Winchester Type)

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 Disk Performance Parameters
When the disk drive is operating, the disk is rotating at constant speed. To read or write, the
head must be positioned at the desired track and at the beginning of the desired sector on that
track. Track selection involves moving the head in a movable-head system or electronically
selecting one head on a fixed-head system.
● Seek time
– On a movable-head system the time it takes to position the head at the track
– A typical average seek time on contemporary hard disks is under 10 ms.
● Rotational Delay
– The time it takes for the beginning of the sector to reach the head is known as rotational delay, or
rotational latency.
– At 3600 rpm
– At 20,000 rpm there is one revolution per 3 ms. Thus, on the average, the rotational delay will be 1.5 ms.
● Access time
– Seek time + Rotational Delay
● Additional Delays
– Availability of disks
– Availability of I/O channel

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 RAID

● As discussed earlier, the rate in improvement

in secondary storage performance has been
considerably less than the rate for processors
and main memory.
● This mismatch has made the disk storage
system perhaps the main focus of concern in
improving overall computer system
performance.

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 Optical

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 Optical Read Write

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 Recommended Reading

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 Review

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Quiz

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