Structure operates as a capacitor “mirroring” any charge

deposited on the top plate

Potential applied results in a “channel” of free electrons at

the interface between the insulator and the piece of silicon

If the electron density is sufficiently high it serves as a

conductive path
Since, Q = CV
Density of electrons in the channel varies with V1
V1 controls the resistivity of the channel

If a battery V2 is connected,
a current flows through the silicon bar

Current prefers least resistance path,

→ flows through the channel than through the entire bulk

→ We can build a voltage-controlled current source

Q = CV
→ for strong control of Q by V, C must be maximized

Reducing thickness of the dielectric layer can increase C

Typical thickness <20Å
The device is symmetric with respect to S and D

With n-type source/drain and

p-type substrate, device operates with electrons
Giving the name NMOS

Arrow in the symbol signifies the source terminal

 Typical dimensions of today’s MOSFETs

proper operation of the transistor requires the

diodes to be reverse-biased
Gate voltage at which the channel begins to appear is called the
“threshold voltage,” VTH, and falls in the range of 300 to 500 mV

Conductive channel between S and D can be viewed as a resistor

As VG becomes more positive, density of electrons in the channel

increases → the resistance changes with the VG
→ Can act as a voltage controlled resistor
If VG<VTH, no channel exists,
device is off,
ID=0 regardless of the value of VD

If VG>VTH, then ID > 0

S-D path acts as a simple resistor

slope = 1/Ron,
with Ron representing the “on-resistance” of the MOSFET
if VG increases?
We have higher density of electrons in the channel

→ Less Ron → greater slope

→ MOSFET is indeed voltage-dependent resistance

As the channel length increases, Ron increases

→ For VG > VTH, ID begins with lesser value

ID exhibits a smaller slope as a function of VD

Desirable to minimize the channel length so as to achieve large

drain currents

length is under the circuit designer’s control

can be specified in the “layout” of the transistor
 oxide thickness, tox and I-V characteristics

As tox increases, ‘C’ between the gate and substrate decreases.

Since, Q = CV,
For a given voltage we get less charge on the gate
→ lower electron density in the channel

→ higher Ron

→ less ID for a given gate or drain voltage

 width of the transistor

As W increases, Ron reduces → increase in ID

Can be viewed as two narrower transistors in parallel,

producing a high drain current
To get more ID, W must be maximized
→ total gate capacitance increases with W,
→ limits the speed of the circuit
 Channel Pinch-Off
To form a channel, the potential difference between the gate and
the oxide-silicon interface must exceed VTH

If drain voltage > source voltage,

as we go from the source towards the drain, voltage at each
point along the channel with respect to ground increases
potential difference between the gate and the oxide-silicon
interface decreases along the x-axis

Density of electrons in the channel follows the same trend,

falling to a minimum at x = L.
If the drain voltage is high enough to produce VG−VD≤VTH, then
the channel ceases to exist near the drain.

We say the channel is “pinched off”

 If VD > (VG−VTH)?
Voltage difference between the gate and substrate falls to VTH at
some point L1 < L

→ no channel between L1 and L

→ once the electrons reach the end of the channel, they

experience the high electric field in the depletion region
surrounding the drain junction and are rapidly swept to the
drain terminal

→ device still conducts

→ gate capacitance per unit area defined Cox (expressed in F/m2
or fF/μm2), we write C = WCox
 From Q = CV
C is the gate capacitance per unit length
V is the voltage difference between the gate and the channel,
Q is the desired charge density

Denoting gate capacitance per unit area by Cox (expressed in

F/m2 or fF/μm2),

we write, C = WCox to account for the width of the transistor

We also have V=VGS−VTH since no mobile charge exists for VGS<VTH

Then (Q is in C/m)
 Channel voltage varies along the length, and the charge density
falls as we go from S to D

Previous Eq. is re-written as

if the channel is not pinched off;

V(x) goes from zero (at S) to VD (at D)

Current ‘I’ is the total charge that passes through the C/S of the
bar in one second

If carrier velocity is ‘v’ m/s, then the charge enclosed in ‘v’

meters along the bar passes through the C/S in one second
Since the charge enclosed in ‘v’ meters is equal to Qv,

We can write
 Using above equations in

Since ID must be constant along the channel,

V(x) and dV/dx must vary such that,
[VGS−V(x) − VTH]dV/dx should be independent of x
As expected,
IDCox [ID1/tox] IDW ID1/L

Higher mobility (n) yields a greater current

For a constant VGS,

ID varies parabolically with VDS

Reaches Maximum at

W/L is written as ratio of two values [5μm/0.18μm]

rather than 27.8 to emphasize the choice of W and L
Individual values of W and L are also critical

If both W and L are doubled, the ratio remains unchanged but

the gate capacitance increases
 Plot of ID-VDS for different values of VGS

As VGS increases, IDmax and VGS−VTH also increases

Since, IDmax ∝ (VGS−VTH)2,

ID-VDS characteristics exhibit maxima that follow a parabolic shape
Nonlinear relationship between ID and VDS reveals that the
transistor cannot generally be modeled as a linear resistor

If VDS<<2(VGS−VTH),

Now the device exhibits linear behavior for a given VGS

On-resistance, Ron=VDS/ID,

Ron can be controlled by VGS

For VGS=VTH, Ron=,
→ Could be used as an
electronic switch
A switch connecting the transmitter to the antenna should not
attenuate the signal by no more than 10%. If VDD=1.8V,
μnCox=100μA/V2, and VTH=0.4 V, determine the minimum required
aspect ratio (W/L) of the switch. Antenna is modeled as a 50
resistor
Vout=VinRant/(Rant+Ron)

From given data

Rant/(Rant+Ron) = 0.9

With Rant=50

Setting VGS to the maximum value, VDD,

 Triode and Saturation Regions

For VDS>VGS−VTH, ID begins to fall

For VDS<VGS−VTH (the rising section of the parabola)

Device operates in the “triode” or “linear” region

For VDS< 2(VGS−VTH),

Device operates in the “deep triode region”
where the transistor operates as a resistor
 In reality, for VDS>VGS−VTH,
instead of reducing, ID saturates & becomes constant

For VDS>VGS−VTH, channel experiences pinch-off

Further increase in VDS simply shifts the pinch-off point slightly

toward the source

The ID expression is valid only where channel charge exists

→ Integration must be performed only in the channel region

i.e. from x = 0 to x = L1

Note that the integral on RHS is evaluated up to VGS − VTH rather

than up to VDS
If we assume L1 ≈ L, ID is identical to ID,max

VGS − VTH is Called the “overdrive voltage”

MOSFETs are called “square law” devices to emphasize the

relationship between ID and the overdrive voltage

Hereafter L1 is denoted with L

In the “flat” current (saturation) region
- MOSFET can operate as a current source

The square-law dependence of ID on VGS − VTH suggests that the

device can be used as a voltage-controlled current source
Calculate the bias current. Assume μnCox = 100 μA/V2, VTH =0.4V.
If the gate voltage increases by 10mV, what is the change in the
drain voltage?
Assume that M1 is saturated

→ = 200 μA = 200 μA

VX = VDD − RDID = 0.8V

As VX = VDS = 0.8V
→ VGS − VTH = 0.6V
VGS= 1V

Since VDS > (VGS − VTH) M1 indeed operates in saturation

If the gate voltage increases to 1.01 V, ID = 206.7μA

VX = VDD − RDID = 0.766V M1 is still in saturation
BJT with VBE = VCE operates at the edge of the active region
whereas a
MOSFET approaches the edge of saturation if VDS > VGS – VTH

BJT exhibits exponential IC -VBE characteristic

whereas a
MOSFET exhibits a square-law dependence

→ gm for BJT > gm for MOSFET

In BJT circuits, most BJTs have the same dimensions and hence
the same IS, whereas
in MOS circuits, the aspect ratio of each device may be chosen
differently to satisfy the design requirements

The gate of MOSFETs draws no bias current

 Determine the value of W/L that places M1 at the edge of
saturation and calculate the drain voltage change for a 1mV
change at the gate. Assume VTH = 0.4V.

With VGS = 1V,

VDS must fall below VGS − VTH = 0.6 V
for M1 to enter the triode region

→ ID = (VDD − VDS)/RD = 240 μA

Since ID scales linearly with W/L,

If VGS increases by 1 mV, ID = 248.04μA

→ΔVX = ΔVDS = ΔIDRD = 4.02mV

This can also be considered as a voltage gain of 4.02

If μnCox = 100μA/V2 and VTH = 0.4V, Calculate the maximum
allowable gate voltage if M1 must remain saturated

At the edge of saturation,

VGS − VTH = VDS = VDD − RDID
 Channel Length Modulation

L1 varies with VDS which is known as “channel length modulation”

L1 decreases as VDS increases

Since ID ∝ 1/L1, channel length modulation results in higher ID

Is similar to Early effect in BJT

To account for channel-length modulation, we assume L to be
constant, but multiply the RHS by a corrective term

λ - is called the “channel length modulation coefficient”

Unlike the Early effect , the amount of channel length modulation
is under the circuit designer’s control

This is because λ  1/L

→ for a longer channel, the relative change in L (and hence in ID)
for a given change in VDS is smaller
A MOSFET carries a ID = 1mA with VDS = 0.5 V in saturation.
Determine the change in ID if VDS rises to 1V and λ = 0.1V−1.
What is the device output impedance?

With ID1 = 1mA, VDS1 =0.5V, VDS2 =1V, and λ =0.1V−1, ID2 = 1.048mA

→ ΔID = 48μA

→ output impedance = 10.42 k

Assuming λ ∝ 1/L, if both W and L are doubled, calculate ΔID and
rO in the previous example

Doubling W and L does not alter W/L ratio

λ  1/L → when L doubles, λ halves → λ = 0.05V-1

= 1.024mA

→ ΔID = 24μA

= 20.84 k
 MOS Transconductance

We have

for a given VGS − VTH, gm is linearly proportional to W/L

for a given W/L, gm is linearly proportional to VGS − VTH

In saturation, how does gm and VGS − VTH change if both W/L and ID
are doubled?

→ gm doubles

If VGS is constant and W of the device is doubled, it is as if two

transistors carrying equal currents are placed in parallel
 Velocity Saturation
At high electric fields,  degrades, eventually leading to
constant velocity
Channel length for Modern MOS devices is of the order of 0.1μm

They experience velocity saturation even with VDS as low as 1 V

Due to this, the I/V characteristics does not follow the square-law
behavior

Let saturated velocity be vsat, → ID = vsatQ = vsatWCox(VGS − VTH)

ID now exhibits a linear dependence on VGS − VTH

no dependence on L

gm = ∂ID/∂VGS = vsatWCox, a quantity independent of L and ID

 Second Order Effects

As the source becomes positive with respect to the

substrate/Bulk (VSB),
VTH increases - known as “body effect”

VTH0 - threshold voltage with VSB = 0

 and F are technology-dependent parameters having typical
values of 0.4 √V and 0.4V, respectively
 Assume VS = 0.5V, VG = VD = 1.4V, μnCox = 100μA/V2, W/L = 50,
and VTH0 = 0.6V. Determine ID if λ =0

Since, VSB = 0.5 V

With  = 0.4 √V and F = 0.4V VTH = 0.698 V

VGS = VG – VS = 0.9V VGS - VTH = .202V

VDS = VD – VS = 0.9V Since VDS > VGS – VTH FET is in saturation

→ = 102 μA
Large-Signal Model
Sketch ID versus V1 as V1 varies from zero to VDD. Assume λ = 0.

VGS = VDD – V1 VDS = VDD – V1

→ VDS > VGS – VTH FET is in saturation

A diode connected FET is always in saturation

V1 = 0 → VGS = VDD → ID is maximum

As V1 rises, VGS falls → ID falls

If V1 = VDD − VTH, VGS = VTH → device turns off

Note that, due to body effect, VTH varies with V1 if the substrate
is tied to ground
Small Signal Model
A MOSFET has ID of 0.5 mA. If μnCox = 100 μA/V2, W/L = 10, and λ
= 0.1V−1, calculate its small-signal parameters

Similar to BJT, the intrinsic gain = gmrO = 20

for the choice of device dimensions and bias current
Determine the small-signal resistances RX and RY. Assume λ 0

NMOS PMOS

If λ → 0, resistance R=1/gm
An NMOS device carries 1mA with VGS−VTH = 0.6V and 1.6mA
with VGS−VTH = 0.8V. If the device operates in the triode region,
calculate VDS and W/L

1.0 [2(0.6)VDS – VDS2]

1.6 [2(0.8)VDS – VDS2]

Dividing the two equations and solving for VDS

VDS = 0.533V
We wish to use an NMOS transistor as a variable resistor with
Ron = 500 at VGS = 1V and Ron = 400 at VGS = 1.5V. Explain
why this is not possible.

500 = 400 =
[1-VTH] [1.5-VTH]

5(1-VTH) = 4(1.5-VTH) → VTH = -1V

We can not get negative VTH for NMOS

In the circuit, M1 is an electronic switch. If Vin ≈ 0, determine W/L
such that the circuit attenuates the signal by only 5%. Assume
VG = 1.8 V, μnCox=100μA/V2, VTH=0.4 V, and RL = 100.

Vin ≈ 0
→ M1 can be considered as a linear resistor

Vout=VinRL/(RL+Ron)
Rant/(Rant+Ron) = 0.9

RL/(RL+Ron) = 0.95

With RL=100, Ron= 5.3

With VGS = 1.8 V, μnCox=100μA/V2, VTH=0.4 V, and Ron=5.3

→ W/L =
 For very short channel MOS devices, the square-law behavior
is not valid, and we may instead write: ID = WCox(VGS − VTH)vsat.
Determine the transconductance of such a device.
gM=ID/VGS =

Determine the region of operation of M1. Assume VTH=0.2V

VGS = VG – VS VDS = VD – VS Status

Case 1 -1V -1V -ve VGS →off

Case 2 0 1V VGS =0 →off
Case 3 0.8V 0V VGS>VTH & VDS=0 → Linear
Case 4
Two current sources realized by identical MOSFETs match to
within 1%, i.e., 0.99ID2 < ID1 < 1.01ID2. If VDS1 = 0.5V and VDS2 = 1V,
what is the maximum tolerable value of λ?

current source → M1 and M2 are in saturation

Since VDS2 > VDS1, ID2 > ID1

→ 0.99ID2 = ID1

→=
Assuming W/L = 10/0.18, λ = 0.1V−1, μnCox=100μA/V2, VTH=0.4 V,
and VDD = 1.8 V, calculate ID

Since diode connected – it is in saturation

→ ----- (1)

Also, VDD – IDRD = VGS -------(2) → ID= (VDD – VGS)/RD

Two equations must result in same ID

Start with a initial guess of VGS=0.5V

OR

Use VGS from equation (2) in (1) and solve the resulting
quadratic equation for ID
 Biasing
We assume M1 operates in saturation

In most bias calculations, we can neglect

channel-length modulation

Since no gate current

Also,

→ -----(1)

Also, -----(2)

Using (1) & (2)

With
On using this VGS in (1) we can solve for ID

-----(1)

We can use this equations as long as VY > VX − VTH

→ as long as device operates in saturation region
Determine the bias current of M1 . Assume VTH = 0.5V, μnCox =
100 μA/V2, W/L = 5/0.18, and λ = 0. What is the maximum allowable
value of RD for M1 to remain in saturation?

Voltage across RS =

→
 = 1.286V

Start with initial guess VGS=1.000V

1.000V 0.286V 0.286mA 0.954

0.954V 0.332V 0.332mA 0.989
0.984V 0.302V 0.302mA 0.966
0.966V 0.320V 0.320mA 0.980
0.980V 0.306V 0.306mA 0.969
0.969V 0.317V 0.317mA 0.978
0.978V 0.308V 0.308mA 0.971
0.971V 0.315V 0.315mA 0.976
0.976V 0.310V 0.310mA 0.972
0.972 0.314V 0.314mA 0.975
0.975V 0.311V 0.311mA 0.973
Determine the bias current of M1 . Assume VTH = 0.5V, μnCox =
100 μA/V2, W/L = 5/0.18, and λ = 0. What is the maximum allowable
value of RD for M1 to remain in saturation? (prob. in slide 54 contd...)
=0.36V

= 1.286V

= 0.974V

= 312A

For saturation, VDS = VGS – VTH = 0.974 – 0.5 = 0.474

→ VY = VDS + (VX – VGS) = VX – VTH = 0.786V

→ RD = (VDD - VY)/ID = VX – VTH = 3.25k

Assume M1 is in saturation and RD = 2.5 k, μnCox =100 μA/V2
and λ = 0. Compute (a) maximum allowable value of W/L
(b) minimum allowable value of RS (with W/L = 5/0.18)

Part (a)
With VX = 1.286 V,
→ VY = VX – VTH = 0.786V

Maximum allowable value of ID is given by

= 0.406A

→ W/L = 56.2
Assume M1 is in saturation and RD = 2.5 k, μnCox =100 μA/V2
and λ = 0. Compute (a) maximum allowable value of W/L
(b) minimum allowable value of RS (with W/L = 5/0.18)

Part (b)
With VX = 1.286 V,
→ VY = VX – VTH = 0.786V

= 0.406A

= 1.041V

= 604
 Biasing

→
Calculate ID. μnCox = 100 μA/V2, VTH = 0.5V, and λ = 0.
What value of RD is necessary to reduce ID by a factor of two?

1.44106ID2 – 3842ID + 1.69 = 0 → ID = 556A

To reduce ID to 278μA,

= 2.867k
 Current Sources

NMOS – can be used as a current source with one end grounded

PMOS - current source with one end connected to VDD

If λ = 0, these currents are independent of VX or VY

Do not operate as current sources

VX or VY changes VGS, thus changing ID

Small-signal model of these are identical to that of the diode-

connected devices with impedance of 1/gm (if λ = 0) rather than 
 COMMON-SOURCE AMPLIFIER

vin = v1 vout = −gmv1RD → Vout/vin = −gmRD

Rin =∞ Rout = RD

If ID or RD is increased to increase gain, voltage drop IDRD increases

Voltage gain is limited by the supply voltage

For M1 to remain in saturation,

VDD − RDID > VGS − VTH → RDID < VDD − (VGS − VTH)
 COMMON-SOURCE AMPLIFIER

If  = 0 If   0
Calculate Av if ID = 1 mA, μnCox = 100 μA/V2, VTH = 0.5V, and λ = 0.
Verify that M1 operates in saturation.

= 1/(300 )

Av = −gmRD = -3.33

= 1.1V

VDS = VDD − RDID = 0.8V VGS − VTH = 0.6V

VDS > VGS − VTH → the device is in saturation with a margin of 0.2V

If RD is doubled to double Av, then M1 enters triode region and

gm drops
Assuming M1 is in saturation, determine Av and plot the result
as a function of ‘L’ while other parameters remain constant

Ideal current source → RD =

Av = −gmrO

With gm =

With

→ Consequently, |Av| increases with L

 CS Stage With Current-Source Load

With gate of M2 grounded, v1 = 0

→ gm2v1 = 0 → rO1 and rO2 are in parallel

→ Av = −gm1(rO1||rO2)

Rout = rO1||rO2
With gate of M1 grounded, v1 = 0
→ gm1v1 = 0 → rO1 and rO2 are in parallel

→ Av = −gm2(rO1||rO2)

Rout = rO1||rO2
 CS Stage With Diode-Connected Load

λ = 0 → rO1 and rO2 are zero

Gain is given by the dimensions of M1 and M2 and is

independent of ID and process parameters μn and Cox

The difference is because, in MOS, gm depends on device

dimensions whereas that of the later does not
CS Stage With Diode-Connected Load

λ  0 → rO1 and rO2 are 0

Determine Av if λ = 0

M1 (NMOS) serves as a common-source device

and M2 (PMOS) as a diode-connected load
 CS Stage With Degeneration

λ=0

λ0
Compute Av if λ = 0Compute the output resistance of the
circuit in Fig. 7.18(a) if M1 and M2 are identical
Compute Rout if M1 and M2 are identical

Diode-connected device M2 → (1/gm2)||rO2 ≈ 1/gm2

→ Transistor M1 is degenerated by 1/gm2

Determine Rout and compare the result with previous example.
Assume M1 and M2 are in saturation

With VGS fixed, M2 operates as a current source, with a

resistance of rO2 from the source of M1 to ground

With gm1rO1 >> 1,

With gm1rO2 >> 1, Rout ≈ gm1rO1rO2

Rout here much higher than
CS Amplifier With Biasing
Design the CS for Av = 5, Rin =50k, power budget of 5 mW.
Assume μnCox = 100μA/V2, VTH = 0.5V, λ = 0, VDD = 1.8V, VRS=400mV

Power budget = 5mW

VDD = 1.8V
→ Supply current = 2.78mA

Let, ID=2.7mA and

rest 80μA through R1 and R2

→ RS = VRS/ID = 148

Let, VGS =1V, → gm = 2ID/(VGS − VTH)

= 1(92.6)

Av = gmRD =5 → RD = 463

→ W/L = 216
VGS = 1V and VRS=400mV → VG =VDDR2/ (R1+ R2) = 1.4V
Also, Rin = R1R2/(R1+ R2) = 50k

→ R1 = 64.3k R2 = 225k

VD= VDD − IDRD = 1.8V − 1.25 V = 0.55 V

VD < (VG – VTH) → triode region
We have chosen an excessively large RD

→ increase gm and lower RD

halve RD double gm by increasing W/L by a factor of 4

→ W/L = 864 → gm = 1/(46.3)

gm = 2ID/(VGS − VTH) → VGS = 750mV

→ VG = VGS + VRS) = 1.15V

VD= VDD − IDRD = 1.8V − 0.625V = 1.175V

VD > (VG – VTH) → Saturation region

 Common Gate Stage

v1 = Vin vout = −gmv1RD → Vout/vin = gmRD

→ Rin = 1/gm
A microphone with zero dc level drives a CG stage biased at
ID=0.5 mA. If W/L = 50, μnCox =100 μA/V2, VTH =0.5 V, and VDD=1.8V,
determine RDmax and Avmax. Neglect channel length modulation

→ VGS = 0.947 V

For M1 in saturation, VDD − IDRD > (Vb − VTH) → RD < 2.71 k

gm = 2ID/(VGS − VTH) = 2.24mA/V

Av = gmRD  6.1
Common Gate Stage with Source Resistance
For the circuit, calculate Av if λ = 0 and Rout λ > 0
For the circuit, calculate Av if λ = 0 and Rout λ > 0
CG Stage With Biasing
Design a C-G stage with Av = 5, RS = 0, R3 = 500, 1/gm = 50,
power budget = 2 mW, VDD = 1.8V. Assume μnCox = 100μA/V2, VTH
= 0.5 V, and λ = 0.
Power budget 2mW and VDD = 1.8V
→ Supply current = 1.11mA

Let, ID=1.1mA and

rest 10μA through R1 and R2

→ VR3 = IDR3 = 0.55V

→ if VGS = 0.8V → W/L = 244.4

gm = 2ID/(VGS − VTH) = 1/(136.4)

Av = gmRD =5 → RD = 682
Design a C-G stage with Av = 5, RS = 0, R3 = 500, 1/gm = 50,
power budget = 2 mW, VDD = 1.8V. Assume μnCox = 100μA/V2, VTH
= 0.5 V, and λ = 0.

VGS = 0.8V and VR3=550mV

→ VG = 1.35V

VD= VDD − IDRD = 1.8V − 0.75V = 1.05V

VD > (VG – VTH) → Saturation region

VGS = 0.8V and VR3=550mV → VG =VDDR2/ (R1+ R2) = 1.35V

Also, VDD / (R1+ R2) = 10A

→ R1 = 45k R2 = 135k
In the previous problem, suppose we wish to minimize W/L,
What is the minimum acceptable value of W/L?

→ For a given ID, as W/L decreases,

VGS − VTH increases

→ We must compute the maximum allowable VGS

Condition for saturation : VDD − IDRD > VGS + VR3 − VTH ----(1)

----(2)

From (1) & (2) →

→
→
 Source Follower

If the gate voltage of M1 increases by a small amount,

VGS tends to increases
→ source current increases
→ output voltage increases
→ Vout “follows” Vin

Note: dc level of Vout is lower than that of Vin by VGS

Hence, can serve as a “level shifter”

Calculate the voltage gain of the circuit

Design a source follower to drive a 50 load with Av= 0.5 and a
power budget of 10mW. Assume μnCox = 100μA/V2, VTH = 0.5V,
λ = 0, and VDD = 1.8V.

RL = 50, rO =  and →

Power budget = 10mW and VDD = 1.8V → IDmax = 5.56mA

→
Design the circuit with ID = 1mA and AV = 0.8. Assume VTH = 0.5V,
μnCox =100μA/V2, λ = 0, VDD = 1.8V, and RG = 50 k

gm = 2ID/(VGS − VTH)

→ =867

→ =0.933V

→
Calculate Av and Rout
Compute Av. Neglect channel-length modulation in M1.

Determine Av, assume rO1 =.

Calculate Av with λ = 0.

Vout = gm2v2 RD ---- (1)

gm1v1 = gm2v2 → v1 = (gm2v2)/gm1

vin = v1 - v2

vin = [(gm2v2)/gm1] - v2 ---- (2)

Using (1) and (2)

Calculate the two voltage gains, with λ = 0 for M1.
For the circuit calculate gmmax. μnCox = 200μA/V2, λ = 0, VTH =0.4V

VGS = VDD − ID(100)

VDS = VDD − ID(1k + 100 ) > VGS − VTH

VDD − ID(1k + 100 ) > VDD − ID(100) − VTH

ID(1k + 100 ) < ID(100) + VTH → ID <

gmmax = 2IDmax / (VGS - VTH) = 2IDmax / (VDD − IDmax(100) - VTH)

→ gmmax=
 Due to a manufacturing error, a parasitic resistor, RP has
appeared in the circuit. Samples free from this error exhibit VGS
= VDS + 100mV whereas defective samples exhibit VGS = VDS + 50
mV. Determine the values of W/L and RP.

Without RP:

VGS = VDD = 1.8 V

VDS = VDD − ID(2k) = VGS − 100 mV

VDD − [0.5 μnCoxW/L](VGS − VTH)2(2k) = VGS − 100 mV → W/L =

With RP:

VGS = VDD – IRP (30k) IRP = (VGS – VDS)/RP = 50mV/RP

VGS = VDD − (ID − IRP)2k + 50 mV ID = [0.5 μnCoxW/L](VGS − VTH)2

→ IRP = RP =
In the circuit, M1 and M2 have L = 0.25μm, λ = 0.1V−1. Determine
W1 and W2 such that IX = 2IY = 1mA. Assume VDS1 = VDS2 = VB =
0.8V. Calculate Rout of each current source? Use μnCox =
200μA/V2, λ = 0, VTH =0.4V

IX = 1mA, μnCox = 200μA/V2

L = 0.25μm, λ = 0.1V−1 → W1 =
VDS1 = VGS1 = VB = 0.8V

IY = 0.5mA, μnCox = 200μA/V2

L = 0.25μm, VDS2 = VGS2 = VB = 0.8V → W2 =
λ = 0.1V−1

rO1 = 1/IX = rO2 = 1/IY =

A student mistakenly uses the circuit as a current source. If W/L
= 10/0.25, λ = 0.1V−1, VB1 = 0.2V, μpCox = 100 μA/V2, VTH = -0.4V
and VX has a dc level of 1.2 V, calculate the impedance seen at
the source of M1

Looking into the source of M1

we see a resistance of 1/gm

→ Rout =
The two current sources must be designed for IX = IY = 0.5 mA.
If VB1 = 1V, VB2 = 1.2V, λ = 0.1V−1, and L1 = L2 = 0.25μm, calculate
W1 and W2. Compare the output resistances
Since, VDS is not known,
we need assume =0 in calculating ID
Design the circuit with Av = 5, W/L ≤ 20/0.18. Determine the
required value of RD if power dissipation must not exceed 1 mW.
μnCox = 100 μA/V2

P = VDDID < 1 mW → ID <

Av = 5 = gmRD = (2μnCoxIDW/L) RD → RD <

Design the circuit for Av=15 with ID=0.5mA. If λ1=0.15 V−1, λ2=0.05
V−1, determine the required value of (W/L)2. μnCox=100 μA/V2
rO1=1/1ID rO2=1/2ID

Av = 15 = gm2(rO1//rO2) → gm2 =

gm2 = (2μnCoxIDW/L)(rO1//rO2) → W/L =

 Design the circuit for a AV = 3. If (W/L)1 = 20/0.18, determine
(W/L)2. Assume λ = 0.

In the above example, (W/L)1 = 10/0.18 and ID1 = 0.5 mA.

(a) If λ = 0, determine (W/L)2 such that M1 operates at the edge
of saturation. b) Calculate AV c) Explain why this choice of
(W/L)2 yields AV. μnCox=100 μA/V2, VTH = 0.5V

ID1 = 0.5 μnCox (W/L)1(VGS1 - VTH)2 → VGS1 =

VDS1 = VGS1 - VTH = VDD – VGS2 → VGS2 =

ID2 = 0.5 μnCox (W/L)2(VGS2 - VTH)2 → (W/L)2 =

The circuit must provide AV = 0.6 at 100MHz. Design the circuit
such that the dc voltage at node X = VDD/2. Assume the input
impedance exceeds 20 k.