Professional Documents
Culture Documents
Accurate Modeling of Submicron Symmetric-Load Ring Vcos
Accurate Modeling of Submicron Symmetric-Load Ring Vcos
8.0E-03
0.0E+00 Vds
0.0 1.1 2.2 3.3
Id
4.0E-03
Fig. 1. Points for Npower model generation
Fig. 4. VCO Symmetric loads differential buffer VI. NEW VCO MODEL
Frequency
which accounts for the symmetric load transistor
1.4E+08
operating regions should be derived. Yet, the
accuracy of the results we have obtained for
1.0E+08
several examples is quite good, thus making a
more complex model unnecessary.
6.0E+07
The second limitation of the model proposed is
1.0E+00 1.2E+00 1.4E+00 Vc
that it contains no information regarding the limits
of validity of the model. This additional
information will be considered in future work.
Fig. 5. Frequency vs. Vc for a 1.8V SMIC018
VII. APPLICATION EXAMPLE seven stage VCO: (*)Hspice; (__) New model; (__)
Model [8]
TABLE 3
As an application example we have considered
MAXIMUM AND AVERAGE RELATIVE ERRORS.
a seven-stage symmetrical load differential VCO.
Typical Corner C1 Corner C2
Each stage considered is illustrated in Figure 4, New Model New Model New Model
with the transistor sizes shown in Table 1. The Model [8] Model [8] Model [8]
results obtained for the typical case as well as for Av. 2.0% 13.0% 3.4% 16.0% 1.8% 3.8%
corners C1(upper lines) and C2 (lower lines) are Max 3.0% 24.0% 7.0% 29.4% 3.0% 9.0%
illustrated in figure 5.
In Table 3 we present the maximum and REFERENCES
average relative errors of results obtained from [1] W. Schokley, “ A Unipolar field effect transistor”,
proceedings of IRE, vol. 40, pp. 1365-1376, Nov. 1952
both models. From them we may see that the [2] T. Sakurai, A. R. Newton, “ A simple MOSFET Model
proposed model shows an average error in the for Circuit Analysis”, IEEE transactions on Electron
order of 3%, much smaller then what we obtain Devices, Vol. 38, Nº 4, pp. 887-893, April 1991.
with the model proposed in [8]. [3] L.Bisdounis, S. Nikolaidis, O. Koufopavlou, “ Analytical
Model for CMOS Short-Circuit Power Dissipation”,
Integrated Computer-Aided Engineering Journal, Vol. 5,
VIII. CONCLUSIONS Nº 2, Special issue on Low-power electronic systems, pp.
129-140, April 1998.
This paper described an accurate model for [4] Hamoui, N.Rumin, “ An Analytical Model for Current,
PMOS Symmetric Load ring VCOs. The adoption Delay and Power analysis of Submicrometer CMOS
of the Npower model for transistor Logic Circuits”, IEEE Transactions on Circuits and
Systems-II: Analog and digital Signal Processing,, Vol.
characterization enabled us to obtain a VCO Nº47, Nº10, pp. 999-1007, October 2000.
characterization producing quite accurate results [5] J.L.Rossello, J.Segura, “ Charge-Based analytical model
even for sub micrometer technologies. for the evaluation of power consumption in sub-
micrometer CMOS buffers”, IEEE transactions on
The automatic generation of the Npower Computer-Aided Design, Vol.21, Nº 4, pp. 433-448,
parameters granted us the straightforward April 2002.
generation of VCO models for any given [6] J.G. Maneatis, M. Horowitz “Precise Delay Generation
technology. The simplicity and accuracy of our using Coupled Oscillators”, IEEE Journal of Solid-State
Circuits, Vol. 28, Nº 12, December, 1993
model as well as its robustness against [7] J.G. Maneatis, “Low-Jitter Process-Independent DLL and
technological evolution makes it suitable for using PLL Based on Self-Biased Techniques”, in IEEE Journal
in the automation of VCO design. of Solid State Circuits, Vol. 31, No. 11, pp.1723-1732,
November 1996.
[8] T. H. Toifl, “Integrated Circuits for The Synchronization
ACKNOWLEDGMENT of High-Energy Physics Experiments”, PdD. Dissertation,
M. Helena Fino would like to thank Chipidea - Technische Universitat Wien, February 1999.
Microelectronica, S.A., for providing excellent working