Solid State Device Fundamentals

MOS Capacitor
Solid State Device Fundamentals

Metal-Oxide-Semiconductor capacitor
MOS capacitor is the central part of semiconductor
field effect transistor.
Vg Gate
Vg
Vd
metal Source gate
Drain
SiO2 SiO2
N+ N+

Si body P-silicon body

MOS capacitor MOS transistor

Solid State Device Fundamentals

Energy band diagram of MOS capacitor

Ec
N+polysilicon

Ec
P-Silicon body
SiO2

Ef , E c Ef
Ev
Ev

Gate Si
Body

Ev
No bias, Vg = 0

In MOS capacitor with p-type Si substrate, the energy bands

of silicon bend down at the oxide-silicon interface.
Solid State Device Fundamentals

Flat-band condition and flat-band voltage

Flat band is the condition where the energy band (Ec and Ev) of the substrate is flat at
the Si–SiO2 interface
E0
cSiO2 =0.95 eV
Ec
qg q s= cSi + (Ec –Ef )
3.1 eV 3.1 eV cSi
=4.05eV

Ec, Ef Ec
Vfb Ef
Ev Ev
N+ -poly-Si 9 eV P-body

E0 is vacuum level The band is flat at the

E0 – Ef =Ψ is work function flat band voltage Vfb:
4.8 eV
E0 – Ec is electron affinity
V fb   g  s
Si/SiO2 energy barrier for Ev
electrons is 3.1 eV. SiO2
Solid State Device Fundamentals

Band diagram at negative bias of gate

At negative gate voltage: Vg < Vfb

3.1eV Vg  V fb  s  Vox
Vox
Ec , Ef s - surface potential, band
bending
Ev E0 Vox- voltage across the oxide
accumulation of holes
qVg q s Ec Since hole concentration is
high, the potential drop in
Ef
Ev semiconductor Φs is
negligible, thus:
M O S Vg  V fb  Vox
Solid State Device Fundamentals

Surface accumulation

Vg < Vfb

Vox  Vg  V fb

Qacc  Cox (Vg  V fb )

Vox  Qacc / Cox  Qs / Cox

Solid State Device Fundamentals

Positive bias on gate

Vg > Vfb
qVox
Ec
gate
++++++ Ef
SiO 2 Ev
qs
- --- --- --- --- --- --- -- qVg
V depletion layer Ec, Ef Wdep
charge, Q dep depletion
region
Ev
P-Si body

M O S
Qs Qdep qN aWdep
Vox    
Cox Cox Cox
qN a 2 s s
2 ss Vox 
Wdep  Cox
qN a
Solid State Device Fundamentals

Surface depletion

qN a 2 s s
Vg  V fb   s  Vox  V fb   s 
Cox

This equation can be solved to yield s .

Solid State Device Fundamentals

Condition of threshold voltage of inversion

Threshold (of inversion): Ec

ns = Na , or st
Ei
A C =qB
(Ec–Ef)surface= (Ef – Ev)bulk , or Ef
D B
Ev
qVg = qVt
A=B, and C = D Ec, Ef

kT  N a  Ev
st  2B  2 ln   M O S
q  ni 

Eg kT  N v  kT  N v  kT  N a 
qB   ( E f  Ev ) bulk  ln   ln   ln 
2 q  ni  q  N a  q  ni 
Solid State Device Fundamentals

Inversion threshold voltage

Vg  Vfb φs Vox

kT  N a 
At threshold,  st  2B  2 ln  
q  ni 

qN a 2 s 2B
Vox 
Cox

qN a 2 s 2B
Vt  Vg at threshold  V fb  2B 
Cox
Solid State Device Fundamentals

Threshold Voltage

Tox = 20nm

V t(V), N+ gate/P-body

Vt (V), P+ gate/N-body
Body Doping Density (cm-3 )

(a)2 s 2 B
qN sub + for P-body,
Vt  V fb  2 B  – for N-body
Cox
Tox = 20nm

ody
ody
Solid State Device Fundamentals

Strong inversion

2 s 2B
Vg > Vt Wdep  Wdmax 
qN a Accumulation
of electrons

Ec
Vg > Vt
Ef
Ev
gate
++++++++++ qVg
SiO2
- - - - - - - - Ec, Ef
V - - - - - - -
Q dep Qinv Ev
P - Si substrate
M O S
Solid State Device Fundamentals

Inversion layer charge, Qinv [C/cm2]

Qdep Qinv qN a 2 s 2B Qinv

Vg  V fb  2B    V fb  2B  
Cox Cox Cox Cox
Qinv
 Vt 
Cox Qinv  Cox (Vg  Vt )
Vg > Vt Vg > Vt
Solid State Device Fundamentals

Threshold voltage and gate doping type

Vt is generally set at a small

positive value so that, at Vg = 0,
the transistor does not have an
inversion layer and current does
not flow between the two N+
regions.

p-body is normally paired with n+-gate to achieve a small

positive threshold voltage.

n-body is normally paired with p+-gate to achieve a small

negative threshold voltage.
Solid State Device Fundamentals

Band bending and depletion width versus gate voltage

s

2B

Vg
accumulation Vfb Vt inversion
depletion

Wdep

Wdmax
Wdmax = (2s2B /qN a )1/2

 (s)1/2

Vg
Vfb Vt inversion
accumulation depletion
Solid State Device Fundamentals

Summary

N-type device: N+-polysilicon gate over P-body

P-type device: P+-polysilicon gate over N-body

V fb   g  s  (Qox / Cox )

Vg  V fb  s  Vox   poly
 V fb  s  Qs / Cox   poly
Solid State Device Fundamentals

Summary

st  2 B

kT N substrate
B  ln
q ni

qN sub 2 s |  st |
Vt  V fb   st 
Cox

+ for N-type device, – for P-type device

Solid State Device Fundamentals Ef Ef
N-type Device P-type Device
+ +
Summary
(N -gate over P-substrate) (P -gateover N-substrate)
Accumulation
Vg<Vfb<0 Flat-band V
Vgg>V
=Vfb>0
E Vg=Vfb<0
f
fb>0
N-type
Ef Device P-type DeviceEEff
(N+-gate over P-substrate)
Ef
E
(P+-gate
Ef
E
over N-substrate)
f f

Flat-band
Vg=Vfb<0 Depletion Vg=Vfb>0
Ef V 0>V Vg0<Vfb Ef
g fb

Ef E
Eff Ef
Ef Ef

Depletion
Vg0>Vfb Vg0<Vfb
Threshold Vg=Vt <0
Vg=Vt>0
Ef Ef
Ef Ef Ef
Ef
Ef
Ef

Threshold Vg=Vt <0

Vg=Vt>0 Inversion
V >V>0 E Vg<Vt