A MINI PROJECT REPORT ON

DESIGN AND SIMULATIO N OF 4-BIT ALU

USING GDI TECHNIQUE

A mini project submitted in partial fulfillment of the requirement for the award of

the degree of

B A CH E L O R O F T E CH NO L O G Y
IN
E L E CT RO NI C S A N D C O M M UNI CA T I O N E N G I N E E RI N G

SUBMITTED BY

V . R AM Y A 1 6 S 1 1 A0 4 F1
J A Y DE E P P A T E L 1 6 S 1 1 A0 4 D3
V . S A NT H O S H 1 6 S 1 1 A0 4 G 1

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MALLA REDDY INSTITUTE OF TECHNOLOGY AND SCIENCE
Permanently affiliated to JNTUH and approved by AICTE, New Delhi

NBA & NAAC Accredited, ISO 9001:2015 certified, Approved by U.K Accreditation centre,

Granted status of 2(f) and 12(b) under UGC act 1956, Govt. of India.

MAISAMMAGUDA, DHULAP ALLY, SECUNDRABAD-500 100

2016-2020
MALLA REDDY INSTITUTE OF TECHNOLOGY AND SCIENCE

Permanently affiliated to JNTUH and approved by AICTE, New Delhi

NBA & NAAC Accredited, ISO 9001:2015 certified, Approved by U.K Accreditation centre,

Granted status of 2(f) and 12(b) under UGC act 1956, Govt. of India.

MAISAMMAGUDA, DHULAPALLY, SECUNDRABAD-500 100

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE

This is to certify that the mini project report entitled “DESIGN AND SIMULATION
OF 4 BIT ALU USING GDI TECHNIQUE” being submitted by
V.RAMYA(16S11A04F1), P.JAYDEEP(16S11A04D3), V.SANTHOSH(16S11A04G1)in
partial fulfillment of the degree of Bachelor of Technology in Electronics and
Communication Engineering during the academic year 2019-2020.

Certified further, to the best of my knowledge, the work reported here is not a part of
any other project on the basis of which a degree or an award has been given on an earlier
occasion to any other candidate. The results have been verified and found to be satisfactory.

Head of the Department, ECE External Examiner

Mr. K.Y. SRINIVAS

Associate Professor
 ACKNOWLEDGEMENT
We express a whole hearted gratitude to Dr.K.Ravindra, Principal and Professor of
Electronics and Communication Engineering Department, Malla Reddy Institute of
Technology and Science for providing us the conductive environment for carrying our
academic schedules and projects with ease.
We thank Mr. K.Y Srinivas, Associate professor and Head, Department of
Electronics and Communication Engineering for providing his seamless support and
knowledge during our B. Tech course period and also for providing right suggestions at every
phase of the development of our project.
We sincerely thank to all the staff members, friends and parents without whose
support project would have been deferred.
 ABSTRACT
In day to day development of transportable digital applications, the requirement for
reducing delay, decreasing in size, and low power dissipation various analysis efforts. We
would like to enhance the performance of logic circuits, once supported ancient CMOS
technology, and resulted within the development of the many logic style techniques
throughout the last twenty years. GDI (Gate diffusion input) is a method of low power digital
combinable style. This method permits less power consumption and reduced propagation
delay with minimum range of transistors as compare to alternative presently used logic style
designs, like CMOS, PTL, CPL and TG. XOR was enforced victimization the accessible
technologies & ascertained that GDI technology is giving less power consumption. But
within the GDI technology output voltage swing degradation, fabrication complexness, &
power consumption issues are the disadvantages. Attributable to this reason changed GDI
was planned. Modified GDI technology is additional economical in terms of power
consumption, fabrication complexness, and low output voltage swing degradation when put
next to GDI technology. The ALU consists of 2×1MUX, 4×1MUX and full adder circuits.
These circuits were implemented using Tanner EDA tools. The 4-bit ALU and its blocks
were designed using
 CONTENTS
Topics Page No
Acknowledgement ii
Abstract iii
List of Figures vi
List of Tables viii
Abbreviations ix
CHAPTER 1: OVERVIEW OF THE PROJECT 1-5
1.1 Introduction 1
1.2 Problem Statement 4
1.3 Motivation 4
1.4 Objective 4
1.5 Methodology Adopted 4
1.6 Tools Required 4
1.7 Organization of the Report 5
CHAPTER 2: LITERATURE SURVEY 6-8
2.1 Introduction 6
2.2 Genesis of the Report 6
2.3 Conclusion 8
CHAPTER 3: BASIC ALU CIRCUIT DESIGNS 9-20
3.1 Introduction 9
3.2 CMOS Inverter 9
3.3 AND Gate 11
3.4 OR Gate 13
3.5 EX-OR Gate 14
3.6 EX-NOR Gate 15
3.7 2×1 Multiplexer 16
3.8 4×1 Multiplexer 18
3.9 full adder 20
CHAPTER 4: IMPLEMENTATION OF BASIC ALU USING 21-24
GDI TECHNIQUE
 4.1 Introduction 23
4.2 1-bit ALU 23
4.3 4-bit ALU 24
CHAPTER 5: RESULTS AND DISCUSSIONS 26-38
5.1 Introduction 26
5.2 invertor based GDI 26
5.3 invertor based GDI waveforms 26
5.4 AND gate based GDI 27
5.5 AND gate based GDI waveforms 27
5.6 OR gate based GDI 28
5.7 OR gate based GDI waveforms 28
5.8 EX-OR gate based GDI 29
5.9 EX-OR gate based GDI waveforms 29
5.10 EX-NOR gate based GDI 30
5.11 EX-NOR gate based GDI waveforms 31
5.12 2×1 multiplexer based GDI 31
5.13 2×1 multiplexer based GDI waveforms 32
5.14 4×1 multiplexer based GDI 32
5.15 4×1 multiplexer based GDI waveforms 33
5.16 Full adder based GDI 33
5.17 Full adder based GDI waveforms 34
5.18 1-bit ALU based GDI 34
5.19 1-bit ALU based GDI waveforms 35
5.20 4-bit ALU based GDI 36
5.21 4-bit ALU based GDI waveforms 36
5,22 Conclusion 38
CHAPTER 6: CONCLUSION AND FUTURE SCOPE 39
6.1 Conclusion 39
6.2 Future Scope 39
REFERENCES
40
APPENDIX
 LIST OF FIGURES
Figure no Figure description Page no
Figure 1.1 Symbol of NOT gate 2
Figure 1.2 Symbol of OR gate 2
Figure 1.3 Symbol of AND gate 3
Figure 1.4 Symbol of EX-OR gate 3
Figure 3.1 Modified GDI cell 9
Figure 3.2 Symbol of Invertor 10
Figure 3.3 circuit diagram of CMOS invertor
using GDI technique 10
Figure 3.4 basic CMOS invertor 11
Figure 3.5 Schematic diagram of AND gate 12
Figure 3.6 Schematic of OR Gate 13
Figure 3.7 Schematic of EX-OR Gate 14
Figure 3.8 Schematic of EX-NOR gate 15
Figure 3.9 Symbol of 2×1 multiplexer 16
Figure 3.10 Circuit diagram of 2×1 multiplexer 17
Figure 3.11 Schematic of 2×1 Multiplexer 18
Figure 3.12 Circuit diagram of 4×1 multiplexer 19
Figure 3.13 Block diagram of 4×1 multiplexer 19
Figure 3.14 circuit diagram of full adder using 21
GDI
Figure 3.15 block diagram of full adder 21
Figure 4.1 circuit diagram of 1-bit ALU 23
Figure 4.2 Circuit diagram of 4-bit ALU 24
Figure 5.1 Invertor based GDI 26
Figure 5.2 waveform of invertor based GDI 27
Figure 5.3 AND gate based GDI 27
Figure 5.4 waveform of AND gate based GDI 28
Figure 5.5 OR gate based GDI 28
Figure 5.6 waveform of OR gate based GDI 29
Figure 5.7 EX-OR gate based GDI 29
Figure 5.8 waveform of EX-OR gate based GDI 30
Figure 5.9 EX-NOR gate based GDI 30
Figure 5.10 waveform of EX-NOR gate based GDI 31
Figure 5.11 2×1 multiplexer based GDI 31
Figure 5.12 waveform of 2×1 multiplexer based GDI 32
Figure 5.13 4×1 multiplexer based GDI 32
Figure 5.14 waveform of 4×1 multiplexer based GDI 33
Figure 5.15 Full adder based GDI 33
Figure 5.16 waveform of Full adder based GDI 34
Figure 5.17 1-bit ALU based GDI 34
Figure 5.18 waveform of 1-bit ALU based GDI 35
Figure 5.19 4-bit ALU based GDI 36
Figure 5.20 waveform of 4-bit ALU based GDI 36
 LIST OF TABLES

Table. No Table Description Page. No

Table 3.1 Truth table of CMOS Inverter 11
Table 3.2 Truth table of AND Gate 12
Table 3.3 Truth table of OR Gate 13
Table 3.4 Truth table of EX-OR Gate 14
Table 3.5 Truth table of EX-NOR Gate 15
Table 3.6 Truth table of 2×1 multiplexer for S=0 17
Table 3.7 Truth table of 2×1 multiplexer for S=1 17
Table 3.8 Truth table of 4×1 multiplexer 20
Table 3.9 Truth table of Full Adder 22
Table 4.1 Truth table for proposed 4-bit ALU 25
Table 5.1 Comparison table 38
 ABBREVIATIONS
ALU : Arithmetic and Logical Unit

CPU : Central Processing Unit

CMOS : Complementary Metal Oxide Semiconductor

PMOS : Positive Channel Metal Oxide Semiconductor

NMOS : Negative Channel Metal Oxide Semiconductor

GDI : Gate Diffusion Input

EX-OR : Exclusive OR

EX-NOR : Exclusive NOR