DIGITAL

ELECTRONICS
CIRCUIT
Assignment - 2

Summited to: Rohan Sharma

Summited by: Rubal Sharma

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Q. 1 Design and realise a 4-bit magnitude

comparator using logic gates. Also
explain the applications of comparators
Ans.
A comparator used to compare two binary numbers each of
four bits is called a 4-bit magnitude comparator. It consists of
eight inputs each for two four-bit numbers and three outputs to
generate less than, equal to and greater than between two
binary numbers.
In a 4-bit comparator the condition of A>B can be possible in
the following four cases:
1. If A3 = 1 and B3 = 0
2. If A3 = B3 and A2 = 1 and B2 = 0
3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0

Similarly, the condition for A<B can be possible in the

following four cases:

1. If A3 = 0 and B3 = 1
2. If A3 = B3 and A2 = 0 and B2 = 1
3. If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1
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The condition of A=B is possible only when all the individual

bits of one number exactly coincide with corresponding bits of
another number.
From the above statements logical expressions for each
output can be expressed as follows:

AA, 831331 r: (A3 Ex-Nor 33) A2132′ a (A3 Ex-Nor 133) (A2
Ex-Nor 132) A131′ a (A3 Ex-Nor 33) (A2 ENor132) (Al Ex-
Nor 31) A01301

,13: A3’03 a (A3 Ex-Nor 33) A211:12 a (A3 Ex-Nor 83) (A2
Ex-Nor 132) Ar131 a (A3 Ex-Nor 33) (A2 Ex-Nor32) (Al Ex-
Nor 131) A0N30

A=B: (A3 Ex-Nor B3) (A2 Ex-Nor 82) (Al Ex-Nor BI) (AO Ex-
Nor BO)

By using these Boolean expressions, we can implement a logic circuit

for this comparator as given below:
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Applications of Comparators –
1. Comparators are used in central processing units (CPUs)
and microcontrollers (MCUs).
2. These are used in control applications in which the binary
numbers representing physical variables such as
temperature, position, etc. are compared with a reference
value.
3. Comparators are also used as process controllers and for
Servo motor control.
4. Used in password verification and biometric applications.
5. Null detectors
6. Zero-crossing detectors
7. Relaxation oscillator
8. Level shifter
9. Analog-to-digital converters
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10. Window detectors

Q. 2 How does a priority encoder differs

from an ordinary encoder?
Ans.

Unlike a multiplexer that selects one individual data input line and
then sends that data to a single output line or switch, Digital
Encoder more commonly called a Binary Encoder takes ALL its data
inputs one at a time and then converts them into a single encoded
output. So, we can say that a binary encoder, is a multi-input
combinational logic circuit that converts the logic level “1” data at its
inputs into an equivalent binary code at its output.
Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit
codes depending upon the number of data input lines. An “n-bit”
binary encoder has 2n input lines and n-bit output lines with common
types that include 4-to-2, 8-to-3 and 16-to-4-line configurations.
The output lines of a digital encoder generate the binary equivalent of
the input line whose value is equal to “1” and are available to encode
either a decimal or hexadecimal input pattern to typically a binary or
“B.C.D” (binary coded decimal) output code.

4-to-2 Bit Binary Encoder

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One of the main disadvantages of standard digital encoders is that

they can generate the wrong output code when there is more than
one input present at logic level “1”. For example, if we make
inputs D1 and D2 HIGH at logic “1” both at the same time, the resulting
output is neither at “01” or at “10” but will be at “11” which is an output
binary number that is different to the actual input present. Also, an
output code of all logic “0” s can be generated when all of its inputs
are at “0” OR when input D0 is equal to one.
One simple way to overcome this problem is to “Priorities” the level of
each input pin. So if there is more than one input at logic level “1” at
the same time, the actual output code would only correspond to the
input with the highest designated priority. Then this type of digital
encoder is known commonly as a Priority Encoder or P-encoder for
short.

Priority Encoder
The Priority Encoder solves the problems mentioned above by
allocating a priority level to each input. The priority encoders output
corresponds to the currently active input which has the highest
priority. So, when an input with a higher priority is present, all other
inputs with a lower priority will be ignored.
The priority encoder comes in many different forms with an example
of an 8-input priority encoder along with its truth table shown below.

8-to-3 Bit Priority Encoder

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Priority encoders are available in standard IC form and the TTL

74LS148 is an 8-to-3 bit priority encoder which has eight active LOW
(logic “0”) inputs and provides a 3-bit code of the highest ranked input
at its output.
Priority encoders output the highest order input first for example, if
input lines “D2“, “D3” and “D5” are applied simultaneously the output
code would be for input “D5” (“101”) as this has the highest order out
of the 3 inputs. Once input “D5” had been removed the next highest
output code would be for input “D3” (“011”), and so on.

The truth table for a 8-to-3 bit priority encoder is given as:

Digital Inputs Binary Output

D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0

0 0 0 0 0 0 0 1 0 0 0
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0 0 0 0 0 0 1 X 0 0 1

0 0 0 0 0 1 X X 0 1 0

0 0 0 0 1 X X X 0 1 1

0 0 0 1 X X X X 1 0 0

0 0 1 X X X X X 1 0 1

0 1 X X X X X X 1 1 0

1 X X X X X X X 1 1 1

Where X equals “don’t care”, that is logic “0” or a logic “1”.

From this truth table, the Boolean expression for the encoder above
with data inputs D0 to D7 and outputs Q0, Q1, Q2 is given as:
Output Q0
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Output Q1

Output Q2

Then the final Boolean expression for the priority encoder including
the zero inputs is defined as:

Priority Encoder Output Expression

In practice these zero inputs would be ignored allowing the

implementation of the final Boolean expression for the outputs of the
8-to-3 priority encoder. We can construct a simple encoder from the
expression above using individual OR gates as follows.

Digital Encoder using Logic Gates

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Digital Encoder Applications

Keyboard Encoder
Priority encoders can be used to reduce the number of wires needed
in a particular circuits or application that have multiple inputs. For
example, assume that a microcomputer needs to read the 104 keys of
a standard QWERTY keyboard where only one key would be pressed
either “HIGH” or “LOW” at any one time.
One way would be to connect all 104 wires from the individual keys
on the keyboard directly to the computers input but this would be
impractical for a small home PC. Another alternative and better way
would be to interface the keyboard to the PC using a priority encoder.
The 104 individual buttons or keys could be encoded into a standard
ASCII code of only 7-bits (0 to 127 decimal) to represent each key or
character of the keyboard and then input as a much smaller 7-bit
B.C.D code directly to the computer. Keypad encoders such as the
74C923 20-key encoder are available to do just that.

Positional Encoders
Another more common application is in magnetic positional control as
used on ships navigation or for robotic arm positioning etc. Here for
example, the angular or rotary position of a compass is converted into
a digital code by a 74LS148 8-to-3-line priority encoder and input to
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the systems computer to provide navigational data and an example of

a simple 8 position to 3-bit output compass encoder is shown below.
Magnets and reed switches could be used at each compass point to
indicate the needles angular position.

Priority Encoder Navigation

Binary Output

Compass Direction

Q0 Q1 Q2

North 0 0 0

North-East 0 0 1

East 0 1 0
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South-East 0 1 1

South 1 0 0

South-West 1 0 1

West 1 1 0

North-West 1 1 1

Interrupt Requests
Other applications especially for Priority Encoders may include
detecting interrupts in microprocessor applications. Here the
microprocessor uses interrupts to allow peripheral devices such as
the disk drive, scanner, mouse, or printer etc, to communicate with it,
but the microprocessor can only “talk” to one peripheral device at a
time so needs some way of knowing when a particular peripheral
device wants to communicate with it.
The processor does this by using “Interrupt Requests” or “IRQ”
signals to assign priority to all the peripheral devices to ensure that
the most important peripheral device is serviced first. The order of
importance of the devices will depend upon their connection to the
priority encoder.
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IRQ Number Typical Use Description

IRQ 0 System timer Internal System Timer.

IRQ 1 Keyboard Keyboard Controller.

IRQ 3 COM2 & COM4 Second and Fourth Serial Port.

IRQ 4 COM1 & COM3 First and Third Serial Port.

IRQ 5 Sound Sound Card.

IRQ 6 Floppy disk Floppy Disk Controller.

IRQ 7 Parallel port Parallel Printer.

IRQ 12 Mouse PS/2 Mouse.

IRQ 14 Primary IDE Primary Hard Disk Controller.

IRQ 15 Secondary IDE Secondary Hard Disk Controller.

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Because implementing such a system using priority encoders such as

the standard 74LS148 priority encoder IC involves additional logic
circuits, purpose built integrated circuits such as the 8259
Programmable Priority Interrupt Controller is available.

Digital Encoder Summary

Then to summaries, the Digital Encoder is a combinational circuit
that generates a specific code at its outputs such as binary or BCD in
response to one or more active inputs. There are two main types of
digital encoder. The Binary Encoder and the Priority Encoder.
We have seen that the Binary Encoder converts one of 2n inputs into
an n-bit output. Then a binary encoder has fewer output bits than the
input code. Binary encoders are useful for compressing data and can
be constructed from simple AND or OR gates. One of the main
disadvantages of a standard binary encoder is that it would produce
an error at its outputs if more than one input were active at the same
time. To overcome this problem priority encoders were developed.
The Priority Encoder is another type of combinational circuit similar
to a binary encoder, except that it generates an output code based on
the highest prioritized input. Priority encoders are used extensively in
digital and computer systems as microprocessor interrupt controllers
where they detect the highest priority input.
In the next tutorial about combinational logic devices, we will look at
complementary function of the encoder called a Decoder which
convert an n-bit input code to one of its 2n output lines.

Q. 3 How do you realise a parity bit

checker?
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Ans.
The parity generating technique is one of the most widely used error
detection techniques for the data transmission. In digital systems,
when binary data is transmitted and processed, data may be
subjected to noise so that such noise can alter 0s (of data bits) to 1s
and 1s to 0s.

Hence, parity bit is added to the word containing data in order to

make number of 1s either even or odd. Thus, it is used to detect
errors, during the transmission of binary data. The message
containing the data bits along with parity bit is transmitted from
transmitter node to receiver node.

At the receiving end, the number of 1s in the message is counted and

if it doesn’t match with the transmitted one, then it means there is an
error in the data.

Parity generator and checker

A parity generator is a combinational logic circuit that generates the
parity bit in the transmitter. On the other hand, a circuit that checks
the parity in the receiver is called parity checker. A combined circuit or
devices of parity generators and parity checkers are commonly used
in digital systems to detect the single bit errors in the transmitted data
word.

The sum of the data bits and parity bits can be even or odd . In even
parity, the added parity bit will make the total number of 1s an even
amount whereas in odd parity the added parity bit will make the total
number of 1s odd amount.
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The basic principle involved in the implementation of parity circuits is

that sum of odd number of 1s is always 1 and sum of even number of
1s is always zero. Such error detecting and correction can be
implemented by using Ex-OR gates (since Ex-OR gate produce zero
output when there are even number of inputs).

To produce two bits sum, one Ex-OR gate is sufficient whereas for
adding three bits two Ex-OR gates are required as shown in below
figure.

Parity Generator
It is combinational circuit that accepts an n-1-bit stream data and
generates the additional bit that is to be transmitted with the bit
stream. This additional or extra bit is termed as a parity bit.

In even parity bit scheme, the parity bit is ‘0’ if there are even
number of 1s in the data stream and the parity bit is ‘1’ if there
are odd number of 1s in the data stream.

In odd parity bit scheme, the parity bit is ‘1’ if there are even number
of 1s in the data stream and the parity bit is ‘0’ if there are odd
number of 1s in the data stream. Let us discuss both even and odd
parity generators.
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EVEN PARITY GENERATOR

Let us assume that a 3-bit message is to be transmitted with an even
parity bit. Let the three inputs A, B and C are applied to the circuits
and output bit is the parity bit P. The total number of 1s must be even,
to generate the even parity bit P.

The figure below shows the truth table of even parity generator in
which 1 is placed as parity bit in order to make all 1s as even when
the number of 1s in the truth table is odd.

The K-map simplification for 3-bit message even parity generator is

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From the above truth table, the simplified expression of the parity bit
can be written as

The above expression can be implemented by using two Ex-OR

gates. The logic diagram of even parity generator with two Ex – OR
gates is shown below. The three-bit message along with the parity
generated by this circuit which is transmitted to the receiving end
where parity checker circuit checks whether any error is present or
not.
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To generate the even parity bit for a 4-bit data, three Ex-OR gates are
required to add the 4-bits and their sum will be the parity bit.

ODD PARITY GENERATOR

Let us consider that the 3-bit data is to be transmitted with an odd
parity bit. The three inputs are A, B and C and P is the output parity
bit. The total number of bits must be odd in order to generate the odd
parity bit.

In the given truth table below, 1 is placed in the parity bit in order to
make the total number of bits odd when the total number of 1s in the
truth table is even.
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The truth table of the odd parity generator can be simplified by using
K-map as

The output parity bit expression for this generator circuit is obtained
as
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P = A ⊕ B Ex-NOR C

The above Boolean expression can be implemented by using one Ex-

OR gate and one Ex-NOR gate in order to design a 3-bit odd parity
generator.

The logic circuit of this generator is shown in below figure, in which.

two inputs are applied at one Ex-OR gate, and this Ex-OR output and
third input is applied to the Ex-NOR gate, to produce the odd parity
bit. It is also possible to design this circuit by using two Ex-OR gates
and one NOT gate.

Parity Check
It is a logic circuit that checks for possible errors in the transmission.
This circuit can be an even parity checker or odd parity checker
depending on the type of parity generated at the transmission end.
When this circuit is used as even parity checker, the number of input
bits must always be even.
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When a parity error occurs, the ‘sum even’ output goes low and ‘sum
odd’ output goes high. If this logic circuit is used as an odd parity
checker, the number of input bits should be odd, but if an error occurs
the ‘sum odd’ output goes low and ‘sum even’ output goes high.

EVEN PARITY CHECKER

Consider that three input messages along with even parity bit is
generated at the transmitting end. These 4 bits are applied as input to
the parity checker circuit which checks the possibility of error on the
data. Since the data is transmitted with even parity, four bits received
at circuit must have an even number of 1s.

If any error occurs, the received message consists of odd number of

1s. The output of the parity checker is denoted by PEC (parity error
check).

The below table shows the truth table for the even parity checker in
which PEC = 1 if the error occurs, i.e., the four bits received have odd
number of 1s and PEC = 0 if no error occurs, i.e., if the 4-bit message
has even number of 1s.
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The above truth table can be simplified using K-map as shown below.
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The above logic expression for the even parity checker can be
implemented by using three Ex-OR gates as shown in figure. If the
received message consists of five bits, then one more Ex-OR gate is
required for the even parity checking.

ODD PARITY CHECKER

Consider that a three-bit message along with odd parity bit is
transmitted at the transmitting end. Odd parity checker circuit receives
these 4 bits and checks whether any error are present in the data.

If the total number of 1s in the data is odd, then it indicates no error,

whereas if the total number of 1s is even then it indicates the error
since the data is transmitted with odd parity at transmitting end.

The below figure shows the truth table for odd parity generator
where PEC =1 if the 4-bit message received consists of even number
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of 1s (hence the error occurred) and PEC= 0 if the message

contains odd number of 1s (that means no error).

The expression for the PEC in the above truth table can be simplified
by K-map as shown below.
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After simplification, the final expression for the PEC is obtained as

PEC = (A Ex-NOR B) Ex-NOR (C Ex-NOR D)

The expression for the odd parity checker can be designed by using
three Ex-NOR gates as shown below.

Parity Generator/Checker ICs

There are different types of parity generator /checker ICs are
available with different input configurations such as 5-bit, 4-bit, 9-bit,
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12-bit, etc. A most commonly used and standard type of parity

generator/checker IC is 74180.

It is a 9-bit parity generator or checker used to detect errors in high

speed data transmission or data retrieval systems. The figure below
shows the pin diagram of 74180 IC.

This IC can be used to generate a 9-bit odd or even parity code or it

can be used to check for odd or even parity in a 9-bit code (8 data bits
and one parity bit).

This IC consists of eight parity inputs from A through H and two

cascading inputs. There are two outputs even sum and odd sum. In
implementing generator or checker circuits, unused parity bits must
be tied to logic zero and the cascading inputs must not be equal.
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THANK
YOU