A Double Regulated Footer And Header Voltage
Technique For Ultra-Low Power IoT SRAM
Huan Minh Vo
Ho Chi Minh University of Technology and Education
huanvm@hcmute.edu.vn
Abstract—This work presents an ultra low power SRAM
circuit which is suitable for tight power budget of IoT
microcontrollers. The leakage power reduction technique using
double regulated footer and header voltage in order to meet the
requirements for retaining data SRAM in IoT applications. In
normal SRAM operation, header and footer voltage are regulated
full rail voltage by VDD and VSS, respectively. In idle mode,
SRAM cell supply voltage should be lowered as much as possible
to reduce more leakage current but still keep data without loss.
Body effect is more efficient by lowering supply voltage on double
header and footer than just only header or footer at same noise
margin. By doing so, the author compares three techniques of the
single regulated footer voltage (SRFV), single regulated header
voltage (SRHV) and double regulated footer and header voltage
(DRFHV) to make conclusion in term of power saving. In the fair
comparison in active mode, author realizes that double regulated
footer and header voltage technique is more efficiency power
saving than three other techniques in retention mode.
Index Terms— Low power solution, Power Gating, SRAM,
IoT, retention mode.
I. INTRODUCTION
The Internet-of-Thing is a term defined to connect devices
to internet that can be monitored and controlled remotely.
These IoT applications require low power consumption for
longer battery life, smaller battery for greater utility [1].
Sensors are used to monitor various applications such as
environmental conditions [2]. Sensing data is analyzed by
processor unit which is built in sensor nodes. This
microcontroller sends warming alerts to present information for
the working status [2]. This MCU includes SRAM cells that are
occupied more than 60% in Strong ARM and 30% in Alpha
2126 [3]. This is reason that power dissipation has become an
important concern including both higher density and explosive
growth of battery operated appliances. In the development of
technology, the microprocessor designs occupy a large area
portion to memory structure such as multiple levels of
instruction, data caches, translation look-aside buffer,
prediction table, lookup tables. Caches are a dominant
component of leakage energy dissipation in the recent designs.
Leakage energy accounts for 30% of catch energy and 80% of
L2 catch energy [3]. Thus, conserving energy has raised
considerable concerns in SRAM design.
Normally, as the circuit is going to idle state, we should cut
off power lines by turning off switches that is inserted between
power rails. By doing so, the circuit will go to deep sleep
mode. Thus, leakage power will be suppressed quite
completely. However, SRAM cells often store data for
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operation of system. Thus, retention mode is more attractive
than deep sleep mode. In retention mode, the circuit needs to be
kept at certain voltage between supply line and ground line. An
enough large voltage is necessary for both PMOS and NMOS
operating correctly to get a state at output of SRAM. Many
researchers published the technique of NMOS-connected diode
or PMOS-connected diode [4-7] to keep voltage of footer or
header at a determined voltage in retention mode. By using
these diodes, voltage swing of schemes will be smaller than
VDD. Thus, a large amount of power consumption will be
saved. The smaller voltage swing, the more power saved. It is
important that how small the voltage swing is to keep data
safety even in process and environment variations. Amount of
noise margin is essential for these techniques to define robust
against noises. If output voltage of an inverter can be input of
another inverter, and data can be guaranteed at logic 1 or 0, we
can clam that lowering voltage swing is allowable to SRAM
cells in retention mode. Here, as long as data is saved, we can
reduce voltage swing as small as possible. In this paper, we try
to lower voltage swing as much as possible but still keep data
to minimize power consumption in retention mode. By using a
voltage level controller, the proposed SRAM is applied to a
smaller supply voltage than SRAM technique of NMOS-
connected diode or PMOS-connected diode. By regulating this
footer or header to a determined voltage, the voltage swing is
smaller than normal VDD level. In retention mode, we try to
both keep data safety and reduce leakage current where the
circuit is idle mode.
Leakage power is a dominant part of total power
consumption in integrated circuit design. There are many
leakage mechanisms existing in CMOS circuits. Among
various mechanisms, sub-threshold leakage current consumes
the largest portion [8]. Amount of sub-threshold current
consumption is proportional inversely to threshold voltage [8].
It means that sub-threshold current will decrease exponentially
very much according to the threshold voltage increase.
Therefore, a slight decrease of threshold voltage will cause a
significant reduction on leakage current. However, threshold
voltage cannot increase forever so that sub-threshold current
reaches to zero. Particularly, sub-threshold current dramatically
rises in nanometer technology. Threshold voltage will get
saturated at a specific source to body difference.
To gain power saving efficiency, the paper proposed double
regulated voltage technique to save more power consumption
in SRAMs in retention mode. Author compares three schemes
of single regulated footer voltage, single regulated header
voltage and double regulated header and footer voltage in term
of leakage power saving in a fair comparison in active mode.
Thus, author proposes the double regulated header and footer
voltage as a promising candidate for reducing leakage current
in low power SRAM cell solutions in retention mode.
II. ULTRA-LOW POWER IOT SRAM
The change in NMOS threshold voltage is as a function of
source to bulk potential
VTHN (VSB ) = VTHN 0 + γ n ( 2 V fp + VSB − 2 V fp ) (1)
Here, VTHN (VSB) is voltage threshold of NMOS at a VSB
(the voltage between source and body terminal). VTHN0 is
zero-bias threshold voltage. γn is body effect parameter.
2 V fp is surface to bulk potential. The equation in (1) shows
that threshold voltage increases as the source voltage is higher
than bulk terminal voltage. This change is called body effect.
For PMOS we have the equation:
VTHP (VBS ) = VTHP 0 + γ p ( 2 V fn + VBS − 2 V fn ) (2)
The figure 1 shows a plot of threshold variation according
to VSB as a more clear explanation for equation 1 and 2. The
figure 1 shows threshold voltage changes with increasing
source-to-body potential. For large values of VSB, the
threshold voltage does not change considerably while there is
a big change regarding small values as shown in figure 1.
VTHN(VSB)
VTHN(0)=VTHN0
VSB=0 VSB
Fig. 1. The simulation in variation of threshold voltage with source to bulk
potential.
The threshold voltage change slope will go faster at
smaller VSB compared to large VSB. The change at large VSB is
slower than that in small VSB. It means threshold voltage will
not increase proportionally to VSB voltage variation. When a
large VSB voltage is applied to NMOS, threshold voltage will
get almost saturated. Thus, we should divide VSB change into 2
parts which is shared on both NMOS and PMOS, instead of
applying a large VSB to NMOS (footer) or PMOS (header).
Using one smaller amount of VSB voltage applied to NMOS
and the other smaller amount of VSB voltage is applied to
PMOS. So that, the body effect will get greater efficiency at
two smaller VSB than just a large VSB which is applied to only
header or footer.
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A CMOS SRAM cell is constructed by six MOSFET
transistors. The SRAM cell has two stable states denoted by 0
and 1. The storage cell is low power consumption in standby
mode and great immunity to transient noise and voltage
variation. The SRAM cell has two additional access transistors
to control the access to a storage cell during read and write
operations. Access to the cell enabled by word line that
controls whether the cell should be connected to bit lines of
BL or BLB, in turn. Figure 2 gives three schemes of low
power SRAM techniques. Figure 2a illustrates solution of
lower leakage reduction circuit by decreasing VM. A DC level
controller is designed to apply difference voltage levels to
source terminal of PMOS transistor. When the SRAM is active
mode, VM = VDD, else VM < VDD in inactive mode as in figure
2a. In active mode, SRAM operates normally in reading and
writing process. In inactive mode, circuit is idle, voltage
supply should be reduced to a voltage level which still has
enough voltage to keep data without lost at VM=VDD-2Δ. By
doing so, the body effect will occur at pull-up network of
SRAM cells. In this case, a large VSB voltage difference causes
a rise in threshold voltage of PMOS network while threshold
voltage of NMOS pull down network still keeps the same
previous value.
Similarly, figure 2 b provides scheme of Single Regulated
Footer Voltage method which increases VSL with DC level
controller to reduce leakage current in sleep mode. Here, VSL
is applied to a VSSH voltage which is as large as 2Δ in inactive
SRAM mode at WL=’0’. The body effect also happens to
NMOS pull down network which climbs the voltage threshold
of NMOS transistors due to a rise of VSB. In other hand, the
PMOS pull up network still keeps voltage threshold the same
active mode value. The VSL signal will be connected to
ground at WL=1, then SRAM is in normal mode. The figure 2
c) shows the proposed technique which is applied to SRAM
cell by merging decreasing VM and increasing VSL. Here, VM
is applied to a voltage of VDD – Δ and VSL is applied to a
voltage of Δ. Therefore, body effect occurs in both NMOS
pull down network and PMOS pull up network. By dividing
the 2 Δ voltage for separately applying to header and footer
switches, the body effect will gain more advantage than just
header or footer which has been mentioned in figure 2a and
figure 2b.
VDD VDD
WL
DC level VM
controller
VDD
active
VM
inactive
Inactive: VM < VDD BL
Active : VM = VDD BL
VSS VSS VSS VSS
a)
 level in SRAM retention mode. Likewise, VSL2 signal gets
VDD VDD VSS at active mode of scheme in figure 2 b. The VSL2 is rose to
WL 2Δ in idle mode of SRAM. By doing so, the voltage swing of
VDD two power rails will be VDD-2Δ which is applied as same as
SRHV technique. Here, delta value is designed to make sure
VDD that inverter output is considered at logic “0” with anything
WL
VSS below 2Δ value. Finally, VM3 and VSL3 are applied to power
line and ground line for the proposed circuit of figure 3 c). It is
VDD seen that VM3 is went down to amount of Δ and VSL is went up
VSL VSS
to amount of Δ. In summary, voltage swing of proposed
BL BL SRAM scheme is also VDD-2Δ in idle mode. Voltage swing of
VSS VSS the proposed technique still VDD in active mode. As figure 3
VSL shown, the voltage swing of three schemes is the same as VDD-
Vssh 2Δ in retention mode. Consequently, vulnerable noise
VDD DC level
controller characteristics of three SRAM circuits can be considered to
the same condition. As a result, this comparison is fair in
making conclusions for three schemes.
WL

Active time Sleep time Active time

b) VDD
WL
VSS
VDD VDD
WL VDD
VM1
DC level 2
VM
controller VSS

VDD
VSL2
VDD 2
WL VSS VSS

VDD BL VDD
VM3
VM VSS VSS VSS BL
VSL VSS
VDD
VSL DC level Vssh
VDD
VSS controller VDD
VSL3

WL VSS

Fig. 3. Waveform of signals in three low power SRAM schemes

c)
Fig. 2. Three schemes of low power SRAM cell a) single regulated footer
voltage. b) single regulated header voltage .c)double regulated header and
footer voltage.
Figure 3 illustrates waveform of WL, VM and VSL of three
schemes. The WL signal is applied to enable word line access.
When WL is “1”, BL is saved to cross-coupled inverter. This
WL signal is applied to three schemes of SRAM circuit. VM1 is
supply voltage applied to SRAM of figure 2.a). When SRAM
is in active, VM1 is VDD. So, SRAM is operated normally.
When SRAM is idle, VM1 is lowered to VDD-2Δ to apply to
SRAM. To keep data without loss, just enough voltage is used
to save power dissipation. Here, voltage swing between two
rails is VDD-2Δ. The Δ value is determined to allow noise
voltage on input of a gate so that the output will not be
corrupted. Hence, an inverter output voltage of VDD-2Δ
should be large enough to become input of another gate fully.
In other words, that data will be kept safely at that voltage
Figure 4.a) illustrates block of DC level controller
including PMOS transistors of MP1, MP2, MP3 in series. Gate
terminal of MP1 is connected with Drain terminal forming a
diode. Drop voltage on MP1 is VDD – VTHP leading to output
voltage of MP1 VDD – VTHP. Here, VTHP is defined threshold
voltage of PMOS. In the same way, the connection is applied
to MP2 explaining for why we get voltage of VM = VDD –
2VTHP as MP3 is turned on. In other way, MP3 or MP4 is turned
on in turn by WL and WL . In active mode, WL signal is logic
“1”, MP4 is turned ON, MP3 is turned OFF. Then VM is
achieved at value of VDD supply voltage, the SRAM circuit is
in normal mode. In retention mode, WL signal is logic “0”,
MP4 is turned OFF, MP3 is turned ON. As a result, VM is
dropped to voltage of VDD – 2VTHP in theory. We can optimize
the voltage of VM by adjusting the channel width of MP1 and
MP2.

109
 Figure 4 b) describes the DC level controller for NMOS
switch. Here, VSL is connected to VSS or VSSH depending on
WL signal. When WL is “1”, MN1 is turned ON, WL is
connected to VSS. Here, VSS is equal to 0V. When WL is “0”,
MN1 is turned OFF, WL is connected to VSSH that is converted
from DC level controller at VSSH = VDD – VX. Here, VX is
designed to 2Δ for using in scheme of figure 2b and a, Δ value
for implementing in scheme of figure 2c.
(a) (b)
Fig. 4. (a) DC level controller for VM (b) DC level controller for VSL.
III. SIMULATION RESULTS
In these simulation results of SRAM cells, author uses
45nm Predictive Technology Parameter [9]. To make a fair
comparison in active mode, author compares three schemes
including Single Regulated Header Voltage (SRHV), Single
Regulated Footer Voltage and Double Regulated Header and
Footer Voltage. A circuit consisting of 16 SRAM cells in
parallel is used to evaluate the three schemes in term of
leakage current consumption. We use a short active time as
much as possible compared to sleep time to calculate the
leakage current in these schemes. A shortest active time is
used to ignore this active current portion to total current
consumption. For this reason, the current simulation results
almost consume from leakage current portion.
In active mode, the VDD supply voltage is applied to the
Single Regulated Header Voltage scheme through a PMOS
switch, while VSS supply voltage is applied to the Single
Regulated Footer Voltage scheme through a NMOS switch.
Both VDD supply voltage and VSS supply voltage are applied to
the Double Regulated Header and Footer Voltage. Here, a WL
signal enables to turn on this PMOS switch as seen in figure 4.
Because schemes use different techniques to exploit supply
voltage, different voltages will drop on PMOS or NMOS
switches for three schemes. By doing so, voltage swing is not
the same in active mode. It leads to different timing among
these schemes. We analyzed to make a fair timing comparison
among three schemes by adjusting the width of these switches
[8]. Here, the channel width of MP4 for SRHV is two times
larger than that of MN1 for SRFV. In DRFHV, channel width
of PMOS switch is two times larger than that of SRHV and
channel width of NMOS switch is two times larger than that of
SRFV [8]. Author uses the same width of these switches for
next analysis in retention mode
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In retention mode, WL signal is disabled to turn off supply
voltage which is applied directly to SRAM. A DC level
controller is exploited to decrease VDD to VM and increase VSS
to VSL as presented in figure 4. By adjusting the size of
transistor to create VM, VSL, VSL3, VM3 as demonstrated in
figure 3. Figure 5 shows leakage current results of SRAM cell
at various voltage levels of 1 V, 1.2 V and 1.4 V. The sleep
time is 1µs at 27oC in this operation. As shown, increasing
supply voltage will lead to the leakage current growth in
retention mode of SRAM Cell. The Full Power Rail technique
uses full supply voltage swing in SRAM operation which is
VDD for VM and VSS for VSL. Thus Full Power Rail technique
consumes the largest power lost in retention mode as given in
figure 5. Here, the Full Power Rail has VDD voltage swing in
retention mode. The technique of Double Regulated Header
and Footer Voltage (DRHFV) is the lowest consumption
current which VM is smaller than VDD and VSL is greater than
VSS. By dividing large VSB into two smaller VSB portions,
DRHFV achieves better body effect. So, threshold voltage of
pull up and pull down network increases faster comparing to
just only applying a large VSB, which almost gets saturated in
retention mode. Where the voltage swing is the same among
various schemes, which is VDD-2Δ at retention mode.
Full Power Rail
SRHV
1000
SRFV
Leakage current [nA]
DRHFV
100
10
1,0 1,2 1,4
Voltage supply [V]
Fig. 5. Leakage current versus various supply voltages
Figure 5 illustrates the leakage current comparison among
four SRAM techniques according to various supply voltages.
Here, Full power Rail SRAM technique uses both VDD and
VSS for power supply. A full VDD voltage swing is applied to
SRAM. It means that it does not use low power technique for
SRAM in retention mode. It makes sense that the power lost is
the largest among the other techniques in this case. The
proposed DRHFV scheme is the lowest power lost which is
lower than 23% compared to SRFV, 49% compared to SRHV
and 93% compared to full power rail technique at nominal
voltage of 1.2 V.
Figure 6 investigates the impact of temperature to leakage
current of SRAM cell in three leakage reduction techniques.
Here, the temperature is varied from -27oC, 0oC, 27oC, 100oC
with simulation time about 1µs sleep time. The leakage
current consumption is proportional to temperature as given in
figure 6. The full power rail SRAM consumes the largest
leakage current while the proposed DRHFV technique is the
smallest leakage current lost. Increasing the temperature leads
to rise the leakage current. The proposed technique saves
leakage current up to 95%, 63%, 39% at 100oC , compared to
Full Power Rail, SRHV, SRFV, respectively.
nA
Full Power Rail
SRHV
Leakage current [nA]
SRFV
1000 DRHFV
100
10
-27 0 27
Temperature [ C]
Fig. 6. SRAM leakage current in various temperatures
By increasing the various sleep time, the author compares
the leakage current among three regulated voltage techniques
at 1.2 V supply voltage and at 27 oC. The definition of sleep
time is duration of WL signal at falling to “0” logic and next
rising edge of WL as shown in waveform of figure 3. With
Full Power Rail technique, the leakage current is constant with
438.2nA. This is because voltage swing is VDD applied to
SRAM cells regardless of sleep time. The other techniques
reduce power consumption according to sleep time of SRAM.
The reason is that VM and VSL signals of three schemes are
lower down gradually according to amount of sleep time.
When sleep time rises to 10µs or longer than 10µs as shown in
figure 7, the voltage swing will get saturated and keep at
specific voltage level. At that time, leakage current also does
not change significantly. The comparison shows that using
technique of merging increasing VSL and decreasing VM will
achieve the smallest leakage current. The proposed technique
is saved to 97%, 72%, 45% compared to Full Power Rail,
SRHV, SRFV, respectively.
1000
Leakage Current [nA]
100
10
0,1 1 10
Sleep time [us]
Fig. 7. Leakage current versa sleep time.
IV. CONCLUSION
In this paper, the Double Regulated Header and Footer
Voltage technique is proposed to reduce power consumption
on SRAM cell in 45nm Technology. The fair comparison in
active mode is conducted to make the conclusion. The author
compares the proposed technique with Full power Rail
technique, Single Regulated Header Voltage, Single Regulated
Footer Voltage technique in tem of leakage power loss. By
analyzing the different circumstances of operating conditions
such various supply voltage, temperature and sleep times to
prove that the proposed DRHFV technique is the promising
candidate for lower power consumption in SRAM design in
retention.
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SRHV
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DRHFV
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