Init 3 © Bk - 1 Comoinerionar Loeic ©) Gequential cheuits Combinational civeuite + PA combinational chet eonstele oF logic garter wohose outputs Lot ony aime —detamined toon only the present Combination oF inputs I) A combinational circuit perfoams an gpevation that can bbe specivied —tngicalty by a set of Foolean -functions Sequential cheuits! [> sequential chcuits consists 0+ employ stonage etements fn aasition to logic gates + sequential cixcuits Outputs oie function oF ane inputs nid the state of StoIEge elements- Because the state of the storage elements is q function of Phevious inputs , the outputs of a sequential civeuit depend not onty on present values of inputs, put also past inputs» Combinational circuits i 94 >A combination! cult Conds oF input sevonte, gic yo qutes amd Dutput Vputaies "ogg A Combinational logic gates act 40 the Vmluer oF “pba signals ot Ue inputs and piodece “the Value BP Mie output signal, -tanstoaming fiom the given fnput data’ 10 « Antyoduetion = > logic ecufts for cgital systems may be combinational | |requeed ouput data fo 7 ; on | Combinational 3] Saeed = cineuit | Fig: Block diagram of — Combinational cinuit PF them input binary variables come fom an extemal scuuces the mM utput Vasiabter cue prnduced by the intanal combinational logic circuit Fach input and output \Youiante evices phycicalty as analog signal whore values are intcaprered 40 be | a binaay signal that repicsents —togic + and legie 0. For M1 fhpue Vovigbier, theve ave 2" pessibte binaoy input combinations . Fox each possible input cembinations, there Sone pocsible ouput vmtue. “thes, a Combinational cincuit cam be spesiffed with 9 ANH table that tists ane output Values for each —combihations of input vaniabless Examples for combinational circuits > 2 Adaers 1 > cebbtiacctoas + Comparators oth 0 Ws Decodeas 5 Eneodeas | 6. Muripleress> these components ove used as “Standaad celle “they Potorm specific aigital functions —commorty needed in the design of digital systoms - “they alto used as Standard ces in Comper vey lange scale integrated (esa) circuits such as apptication - specific integrated cheats (sies) ha Analyste procedtuve the analysis of O Combinational ciacuit xequher that we deteammne the function that the chcuit implements the analysis can be performed manually by finding ane poclean functions 0+ ud table or by cing comput simulation — pregrame ‘obtaining the output Boolean -function fiom logic diagram: Ja abet all gate outputs that ore a function of input cay Symbole bat with meaningful ‘for each gate Variables with a Determme the Boolean functions names output Label the gates that are a function oF input Vaviables and pleviously abled — gates with other aabitany these symbols. find he poolean functions “for gates Py dpeated — substitution of —_prewiously designed pootean functions inteams OF functions , Obtain the eutput input — Veaiables- |- : Logie diagsom for analysis 4 | i ; | L | =e ar pO | 4> , ° on 7 4 | ¢ z | | | 6. | —_ | i anputs > ABs ¢ putput: 9H? ‘the outpute of gater ‘that are function enty OF input Voriabiec Tr and % - Output Fe Can eatily be derived ftom — the input Voviables Fa -> © ts age; [eehe Atfac f= (AB + ACT BC) fl = (apt acipe)' = (ayey) (Asc) (Blac!) wee (asic) [ael) Case wed] bie (a atcha glare Bic!) we'd] 2 casero) [le ee) celsed] = paere [neanel see tee) ce (rapic) [ate ae ante] | cs Apicl 4 Avec! + age Fis At Tr Ape Age + Asie! + ABC A Obtaining -buth ‘taller 1 petermine the number of input Voviabler in the ciecuit for on inputs fom the 2” possible input Combinations and ust the binary numbers feorn o to2"t in table.Ptabel the outputs of selected gates with quoitary symbols & pbtain the tuth rable fOr the — gutpute of — those | gates which are functions of input —Vaaiabler only uy pinceed {0 Obtain the table for the outputs Df those gates aphich ale a functlon oF paevicudy defined values: umiil the Columns for all putpute 1 are determined Fige uth table for the Logie diagram. ; aAeiec a] ef n[ oe} e[ on oo D of|tfojleofo}o \ eo of’ frfofelt | oto efi {tfoft | “ptt 1 of: folo | 0D oy 1 fa fott | to! ‘fo flr fofo Lt oo ryo}tfofo rr Poel drfo Ext Obtain the simplified Boolean eXpretsion or Outputs F and & intcims of — Input Varlables- ep 3—— ——D—— Fr —— } yp :Decign procedure: the fesigo of Combinational cheuits Staats wom the cpectication of the design Obtective and culminates in a logic cheuit —diagiam cr a set of Peoolean functions fiom uihich the togic diagram eon be Obtained. she procedaue involve the foltowing steps la. raom the specifications of the chcuit , deteamine the acquited number of — inputs and — gutputs and a symbol to each assign jo. Derive the uth table that defines the dequiaedl yelationship between tnputc and outputs a 2 pltain the — sivvplified Poolean_-functions -fow Fas a. function cf te input Vaasabter Heh each output [us prow the logic Magram — and Verity the conectnecs Fane design (monuaity @) ty simutation) “uth “Table importance: 1A tauth table foe a Combinational circuit input columnc and output —Columne 1 94 n' input Variables thee ae 2” lary consiete OF Nnumbeas: > The binary Values ‘708 the outputs are — detaminedt fiom the Started specificationc ‘the output functions specified tn the taut table give the evact of Combinational cheuit definition oFCode Conversion example = > pidfernt digital sycteme see different coder - 4c cometimes —necessaay 40 ce the output OF one system at the input {40 another mq conversion cieuit rust be fnserteel between the two systems cach wer allttaent coder forthe came trfamaion. thus, a code conver fe a circuit that maker the — 40 Systeme Compatible even though each wer a different binary code Ext Bep to excecs-3 Code inputs 9 A, Bre OD putputs wo mY) Z Fev fou bits 16 combinations exist, but 6 Combinations for input 10 to 1S does not exist, they panne with x Cdontt cared“truth table for Code Conversion: ee Qutput xs-2 code a 8 ¢ D wor y 2 o 0 © Oo o op tt po ot } pet 2D o Oo tO o 1 ot o 0 1 D ' 'o do 1 0 0 ° oud o 1 oO] t,o ood o 1 10 1 o ot ot ' 7 lo 1 0 oO ya tt too ot ' 1 0 0 Maps for scp 40 xs-3 code Converter wo wD ep oT TN coo Abe vo um os bre Ag Cl eS , edhe ag! The AE e10 yy |e we A+ Be 46Dmig iinws A+ Bc BD = AdD CUD) m Bc'D' + Bip sete + Belo! + BICCHD Y= cept cd = cOp =) COD | z= p! Circuit diagram: A B > | Fig! BiD tO Xs-2 ConverterBinary Adder: > pigital compute —peeform co it Li O Vmviety OF infoumation ~ processing jack. prong the functions encountered ye the Vmioue ainthematic opevations the most baste aithematic operation ts the addieion of two binary — digits’ The simple adaition, consists oF foun possible elementary operations . ? addend augend <0 1 | ott zt | t4o st 7 | iat 210s | chet gue Opaations produce sum of one digit, but hen both auigend and qadend bits gue equal to | usher ¢ 4 , [ane ptrtaay sum Conefsts OF 40 digits » the higher signisicant bit oF rete ie called cany- ex: ttre tO ’ L—5 tower signiticont bit higher signiicast bit fsum) (coary) ny : hal adder p combinational chrcult tut prayorms the addition | of + two bits is calted “haw adderFull addere A combinations! chcuit that Performs the addrtion of ahve bite [two cignticont bite and previous coary) fa full adder @ Half Adder: the hal 3 halt odde operation needs two binary inputs: auger and added — bits ; nd two binaey —cueputs: sum and Coury shuth ‘Table: Anputs Outputs | AB Coury sum oo ° oO | ° ' o ! | i 0 ° ! | ' ' ' | 0 cory outputs —~ sum lo Fig: Block Schematic OF hak adder ) | | | | | | | | | |k- map simplification for @ cary 6 @O sum sy For cowry (et) For sums) sumld = AB+AB cany (o> AB > ADB Logic piaguam: Dp camto = ADB Ff tarts = 98 Limitations of Haif~ Adder? an muttidigit addition we have to add wo | vite ateng with HE cowy OF previous digit ation exfecively such addon acquner addition OF tine bits thic i not — posible with halt adder Hence att - adder are not ued IP practiceFull Adder > | A fut adder is a — Combinarional ctrcuit thy at 7 1wO OF the input Variables, denoted by A and B, repaeient the Aw significant bis 40, be added input Gi? represents the camry faom the prewioue the Ane huhematic sum of hte input its and two putpetc | | lower significant position. | ein Go | | : | | | eaut | -uth ‘Tate for futaddert | i Anputs Oueputs a me 5 mn | cay ‘sim | ° o |e © 0 | ° ° V oO Lo ° ' © a) Po ft i | : jo © | | ae i | ! tor ty | {ou i 1 | |ke map simpliteation for Cory and sums For Carry (Cour) Cin + ABein + Agcin + ABCn + Clo CAR +A + Zin (ABANB) = Gin (nOe) + Gin (NOB) cin (ADB) 4 cin (AOD) = cin (AB) Logic diagrams =D m= Gn@ (AB) Gout AB4Atin +BCinArplementation OF futl adder using hair adders A full adder con atsy pe implemented with 4wo ha adders” and “one oR gate" 2 Aer (n06Xin o——_L = From the 41th sable Cony (Cout) = ABCin + AB Cin +ABGin + ABCin Pp | © cin TABAAB) + (Zinrendas Oe Tout_= ABT Cin ADB) Sr o fo | ' sok} yer now cow] ; jo | s poeh [EP Ofef io ty Cour = ab + cin (RBANB) . 4yiol1 oT “i cas | = Abt ABCin 4 ABC couy of 1 | | } eth = ABCHGn) FABGn FABIO AE | = AB ABtin + ABCin-+ ABCin Dot depend 6 = ABT Adin (BIB)+ ABcin es [oo ctndr + ABE Adin + ABOn 5 AB Cont) 4 Aint ABN = ABein +AB+ ACing ABCIN+ ABT ACin¢ Ben (ATA) = ABE Atin + BGn From uth table sum( = ABGnt ABlin + ABCn + ABA Gn (AB-4AB) + cin (AB1 KB) = Gm (AO#) cin (ROB) = Gin (OB) + cin (ADB) bo bo, oY = 4 tami) = cme (nos) a Logic diagram + p=} pt Age (Aes) Cin air Adder fait Adder j Logie diagram funn adteter using two hal adders[vx oe Half Adder in NAND and NOR Logie + NAND @ sumls) = ADB — a | ‘— i L sums BHT | ‘ rt — - noe Ae Algebnc pioot + {Fo drawing gate suuctaue) os AB + AB | SAP +AR+ AA +B Alaib) + BCA) = AAR + BAR | | | | Coury | |on Fig Logie diagram of halt adder wing only NAND gates. nor Logic: em Ate >t 3 ae Algebaaic. prooks { For drawing gate stactard) Se AB TAB | = AB + AAt APY BE | = A(ASE) + BLAFB) fin) Care) 2- input = (ar) (at8) Bot ae = ROBNow? * 419 implement Hol Adder the numberof aw tec acquired me & a > 70 implement NAH Adder the number of NOR gates required gee Ss Hialy Adder using Basie gater (ano, ok. NOT) or AoT Logic. gates sum = A@B Coury (Cour) = AB = ABAAB i nc 2 SS , —p* couyto Fig: Realization using nox logic Notes | 1-10 implement — Half Adder Basic gates (ano, OR, NOT) aequiied is 6Full qoleler using NAND gates: rook am O = AAR = AdAR ome) ®= FB: (at) + ALAAB) > BAB aa) (a4 A8) = BA +AB © > (HrA8) cin = @ 5 (Aerag) cin Cio = (ABE AB) Cin + Cin[lana AB) cin ta] + [(x8-4 8) cin 4 to] + [tient 4G] tot 08) + [[Re7AH Gel co] = (ag4 AB) Ga + Uapt AB) Cin ABO cin Cony (0 c= (AB+AB) tin = (age) cin +8 Coat = AB + (ADB) Cin Nokes To implement full adder the number oF NAND gatec vequived fg 3Fall adder using Nor Logic © 3 xprare = (A+B) Lai) = AB+AB > jravaty + Borat) > Anne | ® 2 jabra) tein | © Gn ———[imeranyan] [1assan) tie] n+ ae] [Unesan) +64) “ = | Fy (nes ab) + UREA AB cin t Go taeinal aon) | STAB) cin + Ge (04 88) sumio = A@BOdN Notes ro implement — fulladdes NOR gaicc required — are ‘a!Full aeictea using easic gates (Ao, OR, NOI) AOT logic SUM= AB cin + ARG + ABGn + ABC Cay = AB+ Acin + BCin a Cout” Binary Adder + (Or) Parallel Adder (OH) Ripple comy Addex 2 A binary Adele i a aligital chcuit that producer the qiikematic sum Of two binary numbers at can be constaucted eoith full adders Connected in fostade , with the Output Cony fom each Sul! adder Connected 40 the input Coury oF the next full austen A single full adder = Capable of addiry two one-hit numbers and input Grory + ‘An order to add binny number with more than One bit, additiona full adders must Le employed A n-Bit poral adder can be constiucted using ‘nN’ Number of full adder —civeetits connected fr? paaaliet. Bn An BL An Br AY Bo Ao out Gy din feat] rt cel awe. adder ms se rig: Bloce diagam OF n-bit pavailel adderJo rther halt gate can be used for tne least significant position oy the Cay input of O full adder is made ©. Design a U-biL paialel adder using fut adaers Bay [ [ I i fo r 6 ‘ a I J Se 8 . co Four bit Adder exe rw binary numbers voith y- bits A= tor Br O01! Ag Aa Ar fs By eB to. it o oO tf | ui oo 6 4 St % hem A A toot 183) (82) (Br) (Po) o ot ! wo G & G o Oo | 1 t—— re = Ko ra Qe lp fet} rr beLogic diagram: opeand 2 pperand ar ‘ i att cout Ue bie Adler co “yee 3 ss 1 Son. Ripple Cony Addert- “the parallel gdder in which the Cauy Cut Of each fult-adder i the Cany-in #0 the next most signisicant adders & cated 2 “ aipple coy adder” “the sum and coory-out bits OF Any Stage Cannot produced, until come -time ater the Canry- in OF that stage occurs: this tx due to the propagation delays in the logic circuHary » which tad too ie delay in addition aes 51 “the camy plopayation delay for each full-adde ir the time beeween the capplicatin Of the Coury in and the occurance OF the Caary mm = 8SThe surmsi) and Camyrout (cd bits given by FAY ave Net valid, until ate the propagation delay of Fay similasty, the Sum G and omy que {GJ bles given by FAp axe noe valid until axe the cumulative “puepagati deny of two full adders (Fay and FA), and so on. At each stage, “the sum bit i noe vatid until bits in alt the Pleceding —Stager ave cay bits must —plopagate or aippte ofter tne canny Valids an effect before the most significant sum bit hacugh, all stages is vould Problem : wDesign an S-bit adder using two “Wy263s fy eB By Ay a6 Ar Ay fa papi fo ASALAL AD u-bit pnaatte! Adder “THLs263 ino. un u-bit parallel ion eo Adder 1418263 r & iS Hy & Seu oo St sur Cours fc “input 40 the — second Adderthe Look Ahead ~ Crary Adder (Carry Look Ahead Adder) fm he Cae of the parallel adder, the speed with which an addition Can he peifcomed ic goweuned by the dime vequired for the Comier to prcpogate 6D ripple thaough al Of the stages OF adder. The look-ahead Cady adder speeds up tne — paocess by eiminacting this ripple Camy delay. st fs posible by giving input’ bits and coy bits forall Stages cimuttaneousty. the metnod of speeding up the audition process fs based on the additional functions Of the full adder called the ony generate and camry pyepagate functions the cary piopagation dime fs an impoitant attribute Of the adder because it fimits the speed wath) which 4wd numbers ave added» “the most widely used Acchnique employs tne — principle OF “ Comy look ahead Logic ” for inueasing speed comider te cincutt’ of the full adder OT fies +44 fo Full adder with p and Gthe new binay variables fi Gi AB AiO the output cum ancl Cay Can acspectively expressed ar Cony Generate (GJ Gi cated A Cony gnaiate , both Ai and Bi me veguadlecs OF and i pacduces a Camy of t when te fnput cnary © any propagate 1P) pi is called a Corry propagate, because it determines lwhether a Cary MEO stage "i ” will propagate into stage t41 Now athe Rorlean -functionc for the Couey outputs OF and substitute Value OF eath Ch ‘each stage Panne Coe input cary AS i poe 10 Oo | | Cre Got Polo ae | ' i Clos | GG th corset o | r ooo } G14 P [G04 Hoe Git Pi [44 focol Lett 0 ° ' rors d ae @the = Git PB [art RGo tM Poco G24 ProGirt PrPaGio + PiPe Polo | | G4 Got POD yDCys Gat Ps @ Gs th [42+ G14 BP Go + B-Pr-Po- 0) cas G24 Ps: Gast Py Pret Bs-Pr- Prego + Ps - Bae Pi Po °C “The general expiesion for mn stages designated as © trvough (4) would be en= Gina th fpclean function For cach cutput Cony i exprested The In sum-of - products form, each function can be frnplemerted| gollowed by an OR gate with one fevel of AND gates fox 4wo level reno) f 3 - Pe I) & ED ; st) |e — TT?) vy et r | he -_ 4 a ee i b> « rane degen ofa Luot-sload Corry. genoraty IB “VN 9 Com ai ) > Loo K ahead Generator cate?) NWN og a )» - I Po hs + 4 t } Lh | oo / [LS rigs Fou bit adder with Camry lookahead ‘the cum output vequives 4W0 exclusive ~ OR gate generate py Voniable, and the AND gate generates Gi Vaviable the Camies ave puopogated — Ayouph the Coury lookahead generartor and — applied to setond — exelusive~ OR pte.1s Decimal Adder Computers oF Caltutators that Patom — aixthemasic rumber system represent decimal numbers in binay coded fom An adder tor uth operations divectly inthe dlecimat % Computer must employ aiathmetic, ciacuits that accept | Coded decimal numbes and pacent desults th the same | code. | . . i A decimal odder requives aq mifnimum of nine input and. five outputs, since fou bis ove required 40 code | cach decimal digit and the cixcuit must have an input | and output cosy there & a wide Variety oF pustible i decimal adder ciacuits , depending upon the Code used to | vepresent decimal digits: exe Bey Addew BeD Adder s consider the owthematic addition oF tuo digits in Reo, with an input Comy from a previous ctage logether to digits, ‘o°t0'9? Which ave aepacsemted Pep numbeas use tm gne binary ou 0000 t0 1001. Fe eath Ben digit Yepresented OS a yebit_binaay number - BD addition cannot be greater thanExit sum 246 e— BO ford 2+ cum greater than q with Cay 0 6 +0110 6 = 1000 w To < ‘Invalid Boo 11 DAG pool 0 D<— BLD for 14 cum equals q or les with Crary | < Aneoweet A o> AA b 1 e—B0D for 19 ain Bed addition each input digit does moe exceed 9, athe output sum cannot be gueater than gtadt= 19, the 1 tn the cum being an input coary. ror two bir @cO adder will panduce a derult that ranger fiom 6 tO 195Rep adders Derivation -for 8 - o-o- 8 = 8m © = o- alae -oea ..c el, _@ 4 ol meac ggecee-- -- e880 -- 5800 ae) oe aa oe see ~ oe ce BT jo ee c00 0 0 009 00 9 8 OFT HFhe table ‘ihe bi oom the: ‘table: “anes (biaay um Ie Get Wks Hig toor, the covesponding Fcp number is idenvcal and therefore no convesion is needed - When the binary cum if guata than 1901, ic Wwalid Bed . The addition OF binary 6 [o110) 10 binary Sunt Converts it to he conect pep depresentation and alin Plodutes an Dutpute cany as required: the logic Cheuk What ddetects the netesiany Cosrection can be desived fiom the —embiet in the table. at is phuious conection fe needed when ye Binary sum hac an output Caaty Ke I co ce REC ) For Cony Cel yee © D bo O° ° ° o © 2 ° ' 0 ° ° . to. ce © a 0 o © ° i 0 ‘ o ° ' 1 o 0 0 1 t t © 1 oo o 0 ° ' o oO i t . in) : 1 oO ' It : 120. ae x y » n k-map for ¢ ayo. . BON Bh Ba we , 2, Fen o| ! 3 2 . Fry om : | weal |g U Lo | ' Ce Zety 62 Ze must one either Zy oe Z% must be | she condition for @ conection and an output coy be expresed by Boolean function. | can Qos ot Ft zatu 1262, 4 Binnig Gneey | v ' When ct ik 1S necesay to add olln to the { binay cum anc! rode? oH casny aor He ret stage-Block diagram Of a BED adders b 2 ‘Addend ——_Augend goto eo Coy an ol? - coure—| y-bit binmy adder |= enzo fagnove®) Se SY SS) i) Workings the two decimal digits, together with the input Cony, | que siost added i the top Sow bit adden 10 produce binay tm Duuput Coy I equal to Oe amy IS equal 40 0, moving 1 added 0 Linney sume output Cary equal to 1 Cony is equat 40 1, binawy o1/0 ic added to the binaey cum though te bottom four bik adlertttt rit coun (e615) xb erecta loons ay 2 nope aN ae 9) Te Reo 30-7 hooug 3q-4 TH dd ss iS 05 15 t5 O= wy (eaennud Gems | fewer gh sapoy Arowg gen | ave? TTT mi eww og tag bx! Design SL adder using Te-1I263A serial adder is used 40 add binay numbers én sesial for the tW0 binary numbers 40 be added seuiait ove closed in two ad Shi aegisters x and ys : Aceumuitor suri Addend vegistet 44 Dade are clock Operations she shi-e | antiatty the actumutator x, the adden register contains ¥, and the Coury —riip-Flep ic cleow “The amy cut lis connected © input of FlipFlop D- the Output 14) is connected . the Serial adder requbes | 2-"the number oF full adder only one full adder circuit] ciacuits in the praaltel adder | equal to the number OF i bits fn the binaay marmbers | 3 the seial adda & a 3 excluding, the registers | | [sequential —cheuit the — paraitel adder ic @ purely combinational circuit | | Jin time vequied for addition | 4 time vequired —-foa addition depends 0 number of bite] does net depend on rats | of bits: | | 5 at is slower 5H Sates es2 SUBTRACTORS ? is subtaacted Halt Subteactore | . subtracts one Pit difference Block diagam lemintend) a it 40 fom a diferente bit rainuend — SUbtiahend Tf o- 0 =0 o-t ’ qn subbaction, each subtiahend bit oF the number fiom Hs coreesponding Significant minuendl with 9 bonow fiom the other A halt subuactor is a combinavional cacuit that and producer the a (vitserence) Haig subtiactot (subteahens? > Hore subtiactor has two inputs b (Basvov) and two cutpets-uth Table Snputs Outputs -eol, op a k-map simpliffcation:~ For pifferente B B ; o | 12, 4 eo] || ee sono ae A@B | logic diagrams Dp dlitterence | imitations oF faye Subtaactors- | Haig subliqctor Can perform subteaction between Fenty wo bite, multi bit. subtraction is mot possible | with halk subtuadtor- lHalf subbactor using MAND NAND. Logic ® a AB ® 2 AB = tae + WAAR TAB AABLAWA) RB Oo HAE = B+AB > p+ BAtAB A AB = AGB Note: 100 input NANP gates and nog Logie 5' xequised for halt suppactor® = AB p> Korat = ABE AB = ADB Note: 1 implement yates ate v A (MB = AB Hatt subliactor °s’ g-input NOR vequireal.fase gquiee requised for hal subbeactor- Fasc gates 9 AND, OR NOT sum: A@B = ABAAB cay = AB A—_o-—______ \_ Ae, — a —d = AatAB oe the Full sublactors= A fyi cubuoctor is a combinational ci wo bits, taking into uit that subpaction — between op the fower — signifitant stage perfoams 0 actount — howow = fut subuactor hat 3-fnputs and. two “outputs Blocte dfagram’- |__-5 diferente (b) fminuiend) A, ' Fut substroctor > hasrow (8) (cupteahersl Bin (previous Boarov0)“uth “Table t= inputs Outputs B | Bin Bout | © ° 0 3 ° 1 ' t 1 ° oo 1 ;' ya ! ° | 2 o © \ ° | a | 2 1 ° B 0 : ‘ 1 j k- map simplification - Bout ne pti, B Bin tin Bin Ben vBin —_Béin u a eo o| Jo a ul sli] | {Or} « Rout = ABin+ AB+ BBin D> BBBin + AB Bin + ABBin + ABBinDifference (0) Logie Diagam = D> AB Bin + ABBin + ABBin + ABBin ~ tin L ‘the Boolean function ov D (didverence) simplified ac { D> AB Bind ABBin + AB Bint ABBIn Bin (HB4+A8) + Bin [AB+AB) Bin (AOB) + Fin ADB 1 Bin ® (A we) 26Bowe Bin “Tull Subtiactor using halt subtiactors = ABU Bin) + ABBin | sin io hale piterenced= (ABB) BB | ln ; subleacty | hai hod soos pep eee L. From -nuth Table A+ (A@B) Bin Bue = ABBin + ABBin + ABBin + ABBIn ‘A | B| Bin] Bout | -D - ae nate olo}o-po | o = in (AB -4A8) + AB (Bin Bin) : - fo fo }rpr 2 AB+ AGB) Bis | { ) Bie ofr toty [a |i Ab+ [ADB) Bin ° i" rPrto 1 joje ws = AB + (aBeAi) Bn a | rfol) = AGE ABBin + AR Bln yijo 7? o|o | 1 rytloAB + ABBin + ABBin + ABBin = AB4 ABin (RIB) + ABBin = Apt A Bin + ABBIn = AB + ABin + ABBIn > ABly# Bin) + ABin + AgBin” = AB + ABEin + ABin + ABLin = Apt BBin (AtA) 4 ABN = Apt BBin + ABI | [net (ame) ein = ABT Abin + BBin Difference (0) = D = ABBin+ ABBin + ABBin + ABR = ‘Bin (mB -+A8) 4 Bin ( ABAAB) = pin (AB) + Bn (008) { | | = [n8) @ Bin 24 _logic diagram :- hs LC A Fhe ROR | Salteoclos = not (768) Bin | Full adder using NAND/NOR. gates! | | NAND gates: ” Loely | o«s | Oo Afb nae = (AtmB) +A8 AtAB> A = Ate> B4AR > BHA — Oo Re = Ae = RE +AB AmB — © > (ree. Bin — @ ~ hos. AOE Bin = FOB + (nos) ein = ROE + Ein ===, © > aps) sin te = (wenn) ein 4 io - Oo [ree + Bin] + [awed Bie + fin} = tae) (hin) + (awe) (") = (aoe) ©8in os) © Bio02 [@@a) Bin + Bin] (Bay © (NOB) Bin » Bin 4 BA [awe + Bin] Bin + AB > [A@B) Bin +B | | [Borowin = AB» (ADB) Bin | lok gate: O- Ae @o Ara = BR CAtB) = AB | os aa = Be (ais) = BA© 5 Adee Bin (ADB) = [Roe] [oie +008) = aoe) Bin © 3 Kav HOB) Bin ie + (A@# BI pigference (0) <—amieie Bin (A08)* Bin @ + [Bint (ace) fin | = non) fn oe © 2 (oH Bin + (OB) Hin = (aoe) oeinle Bit povattet suberactor ext roy ~ Ot) the subwaction OF bingy numbes can be Comied Gut mipst Conveniently by means OF complements: 2° complens subtiaction fs wed for subtraction: Ly the dc Complement can be Obtained by taking the is Complement and adding ¢ 10 the Lease significant pain oF bits togie diagearn = oo a ! Fu? nu! fs nA Br Ay L tl, ott, th. ° ! \ 6 jee cay (et coal gna (to 24 ppp fem ar ’ i so ‘sa 0 5) 0 Fig: 4 -bit posaltel subtvactor| value oF Binary Addex - subbactors the additions and ct Combined into one dreuit adder: thic “is done by ft with each ° full adder when ; =o, the chcuit i Mer, the cieult & gach x-0R gate eceives 2@o =B @ when M=ey pearoums A¥P 2 B@le B ® when M Complemenied and at i conty: the intuit pentoems the oy Bote AB) cubation with - one Operations ave Common binary including an x-OF gate anager “the Mode input (mM) coniuols the operation an cubvactor ingut mand One input B the full adder veeciver: the fg, tne input Cony & 9 and the circuit and Cinzh, the & inputs ave added —ahvough the input oper action pr m4 [2 ComplementWo piv on oe oN Beane Pete meas C2 yoy ' fy Ay A 6 aad bom 2 a L nny = ™ met . lo lo 8 “ 5 Fay (-=——] FAs | ran | rar | 1 3 | J Te iby Sal a? oy AD | vw o eo , iat trod} rigs Logic diagiars oF 8 bit binary adder-subbactor Binary Muttiplien muttiptication of binaay numbers came way 4 multiplication of decimal ic performed the numbers » The | muttiplication is multiplied by each bit oF the murtiptien,| stoating fiom the leart significant bit. €ach such mmuniplicatio fons a poatial practuct - successive partial Products ave shifted one position to the left. the final — product obtained fiom tne Sun OF the. partial §— paoducts. tet us consider Ae An--- Aras Ao Be Bn Bs er Eo OM Axe A> multiplicand Be Mubipliena OQ wv RKAa fg. Muniglicand a= Multiplier bee consider rune pica Tog Nar eiBe x AVAD yoaucts coh [ob Ao®o) poatiol | v ‘aver \ Arbo} © * AND 9x - rerun of two bit Dtherwite , it Produces ‘0’. cuch ac Ap and Ro pede ye ig bow bits oe! fdentical «40 an AND operation. so, Ppastial proclucts this I fave implemented with AND gates ait adders: the second —postial product is Somed by muriplying fibe by AL and shifting — one position to the Nee the two partial products ave added — with {wo hath adder (nay circuits gue ompie bits in the pastial products and i necesaryto use — Full adders 40 produce the sum oF the -——poatiat —procluces-two- bit by Twar bit binaay Multiplier de I new Abr AaB : Aisi AP oe Co cr o product net added lo any other 50, it is divectly given to tne + AoBo — poatial portial —puooluct AND gate:|{conkinatoral cacuit. autuipliey with more bite > For Hiptic ve a muliptier bits and Kk murtiplicand bits, @ (sxe) ano gater © (ry Kbit adden 40 pioauce 9 product pany bits ere Four-bit by three bit ynuntiptien bits tr) = bingy rmoutsiPlien ux 3 ss 4 multipticand bits 02 % & rnurtipicand — muniplier ® pnp gate: = bre) = aru =P | (yy -bit oddlees © adders =lT)K = ta Be Br Bo Toate | Pa Bs Br Bo X Ay AD rons ABD |@u-ble by y-bit Binary muttiplication wnurtiplicantl biéstr) = mutupliee bits (7) -u By BaP Bo X As ALA Ad (Dano gates = Fre = Wye Ib = : Aots Avk: Mobi Anko lo nio-oF adders = (5-1) Kbit adders Aikg Auta Arby 41 BO = tyDy-bit adders ALB: A By Ar By foto | AaB AB ASL AQLO. —— ty Go uw @ & 4 oo - m—— peeled Coy Co igi Vet i ey er LD | = 3) yobit adders na i | yebil Adder ; | | b. 4Problem b Design aes mauntipliea (J) =2 mu ttiplicand (63 =2 multiplier AnD gater = ark = 3x4 26 Adders = (4-1) F- bit adders = )2-bit adders Ae Aas at = BB - B= B00 rene fo XA AIAD = a AoBr Ao 0 AB ALB | mo Me a cg &rauttiplicand bits © pecign 3x2 multiplier Ue) 23 muldiptier bits (3) =2 Be Bs Br Bo A> AiAp Bp Br Bo X AIM yon ha vga) aves ARO go Half Adders aMagnitude com pourtor:— Comparator > A Comparator is a logic circuit used to compare the magnitudes Of two binary num bers oy) A cheuit at compares Wo bingy words and indicates whether they are equal ts called @ Comparator | Magnitude comparators: | Compmcrtors that interpret wen input woids as cignat or unsigned numiets and alo indicate quithemaic yelationship Lgueater less than) fetween the words thee devices gue often called magnitude — Comparatols- iagrams Block diag ae PR AB ACB buttputs Fig: glock diagiam — OF nebit — Compaeator