The Multicycle Datapath with Control Signals

Design a MIPS Processor (II)

PCWriteCond
PCWrite
° Instruction set overview of MIPS processors PCSource
IorD ALUOp
MemRead Control ALUSrcB
° Single cycle MIPS processor MemWrite ALUSrcA
MemtoReg RegWrite
• Datapath design IRWrite RegDst

Instr[31-26]
• Controller design PC[31-28]

° Multiple cycle MIPS Processor Instr[25-0]

Shift 28
left 2
2
• Datapath design 0
• Controller design Memory 0
1

PC
0 Read Addr 1

A
Address
- finite state machine; sequencer; microcode.

IR
Read
1 Register 1 zero
Read Addr 2 Data 1

ALUout
Read Data
° Design a Multiple cycle MIPS Processor with Verilog at 0 File
(Instr. or Data) ALU
Behavioral/Structural Level (Project 5) Write Addr
1 Read

B
Write Data Data 2 0
1 Write Data
4

MDR
1
0 2
Instr[15-0] Sign Shift 3
Extend 32 left 2 ALU
Instr[5-0] control

1 2

Five Execution Steps Operations in Each Step

° Instruction Fetch
° Instruction Decode and Register Fetch Action for R-type Action for memory-reference Action for Action for
Step name instructions instructions branches jumps
° Execution, Memory Address Computation, or Branch Completion
Instruction fetch IR = Memory[PC]
° Memory Access or R-type Instruction Completion PC = PC + 4
Instruction A = Reg [IR[25-21]]
° Memory Read Completion (Write-back)
decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
INSTRUCTIONS TAKE FROM 3 - 5 CYCLES! Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] II
computation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)
jump completion
Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]
completion ALUOut or
Store: Memory [ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] = MDR

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 ALU Controller
func
Op code 6 ALU ALUctr
Main to ALU
ALUop Control
6 Control 3
(Local)
2
31 26 21 16 11 6 0
R-type op rs rt rd shamt funct

° ALUop is 2-bit wide to represent:

• “I-type” requiring the ALU to perform:
- (00) add for load/store and (01) sub for beq
• “R-type” (10), need to reference func field

R-type lw sw beq jump

ALUop (Symbolic) “R-type” Add Add Subtract xxx
ALUop<1:0> 10 00 00 01 xxx

5 6

Logic Equation for ALUctr

ALUctr ALU Operation funct<5:0> Instruction Operation
0000 AND 10 0000 add
0001 OR 10 0010 subtract
0010 add 10 0100 and
ALUop func ALUctr
0110 sub 10 0101 or bit<1> bit<0> bit<5>bit<4>bit<3> bit<2> bit<1> bit<0> bit<3>bit<2> bit<1> bit<0>
0111 set-on-less-than 10 1010 set-on-less-than 0 0 x x x x x x 0 0 1 0
ALUop func ALU ALUctr x 1 x x x x x x 0 1 1 0
bit<1> bit<0> bit<5>bit<4>bit<3>bit<2> bit<1> bit<0> Operation bit<3>bit<2> bit<1> bit<0>
1 x x x 0 0 0 0 0 0 1 0
0 lw 0 x x x x x x Add 0 0 1 0
1 x x x 0 0 1 0 0 1 1 0
0 sw 0 x x x x x x Add 0 0 1 0
1 x x x 0 1 0 0 0 0 0 0
0 beq 1 x x x x x x Subtract 0 1 1 0
1 x x x 0 1 0 1 0 0 0 1
1 R 0 1 0 0 0 0 0 Add 0 0 1 0
1 x x x 1 0 1 0 0 1 1 1
1 R 0 1 0 0 0 1 0 Subtract 0 1 1 0
1 R 0 1 0 0 1 0 0 And 0 0 0 0
1 R 0 1 0 0 1 0 1 Or 0 0 0 1
1 R 0 1 0 1 0 1 0 Set on < 0 1 1 1

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Logic Equation for ALUctr2 Logic Equation for ALUctr1

ALUop func
ALUop func
bit<1> bit<0> bit<5> bit<4> bit<3> bit<2> bit<1> bit<0> ALUctr<1>
bit<1> bit<0> bit<5> bit<4> bit<3> bit<2> bit<1> bit<0> ALUctr<2>
0 0 x x x x x x 1
x 1 x x x x x x 1
x 1 x x x x x x 1
1 x x x 0 0 1 0 1
1 x x x 0 0 0 0 1
1 x x x 1 0 1 0 1
1 x x x 0 0 1 0 1
This makes a case for don’t care 1 x x x 1 0 1 0 1

ALUctr2 = ALUop0 + ALUop1‧func2’‧func1‧func0’

ALUctr1 = ALUop1’ + ALUop1‧func2’‧func0’

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Logic Equation for ALUctr0

ALUOp
ALU control block
ALUop func
bit<1> bit<0> bit<5> bit<4> bit<3> bit<2> bit<1> bit<0> ALUctr<0> ALUOp0
1 x x x 0 1 0 1 1
ALUOp1
1 x x x 1 0 1 0 1

Operation2
F3
ALUctr0 = ALUop1‧func3’‧func2‧func1’‧func0 Operation
F2 Operation1
F (5– 0)
+ ALUop1’‧func3‧func2’‧func1‧func0’ F1
Operation0
F0

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 The Multicycle Datapath with Control Signals
Control Signals from the Main Control Unit
PCWriteCond
Single Bit Control

Signal name Effect when deasserted Effect when asserted PCWrite

PCSource
ALUSrcA 1st ALU operand = PC 1st ALU operand = Reg[rs] IorD ALUOp
RegWrite None Reg file is written MemRead Control ALUSrcB
MemtoReg Reg. data input = ALU Reg. write data input = MDR MemWrite ALUSrcA
RegDst Reg. write dest. no. = rt Reg. write dest. no. = rd MemtoReg RegWrite
IRWrite RegDst
MemRead None Memory at address is read

Instr[31-26]
MemWrite None Memory at address is written
PC[31-28]
IorD Memory address = PC Memory address = ALUout
IRWrite None IR = Memory Instr[25-0]
Shift 28
PCWrite None PC = PCSource left 2
2
PCWriteCond None If zero then PC = PCSource 0
Signal name Value Effect 1
Memory 0
Multiple Bit Control

PC
ALUOp 00 ALU adds 0 Read Addr 1

A
Address

IR
01 ALU subtracts Read
1 Register 1 zero
10 ALU operates according to func code Read Addr 2 Data 1

ALUout
Read Data
ALUSrcB 00 2nd ALU input = B 0 File
(Instr. or Data) ALU
01 2nd ALU input = 4 1 Write Addr
Read
10 2nd ALU input = sign extended IR[15-0]

B
Write Data Data 2 0
11 2nd ALU input = sign ext., shift left 2 IR[15-0] 1 Write Data
4

MDR
1
PCSource 00 PC = ALU (PC + 4) 0
01 PC = ALUout (branch target address) 2
10 PC = PC+4[31-28] || IR[25-0] << 2 Instr[15-0] Sign Shift 3
Extend 32 left 2 ALU
Instr[5-0] control

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Truth Table
input output
op S Datapath control NS
000000 0000 100101000000100 0001
000000 0001 000000000011000 0110
000000 0010 000000000010100 xxxx

000000 1010

000000 1111
000001 0000

000010 0000 100101000000100 0001

000010 0001 000000000011000 1001
000000 0010 000000000010100 xxxx

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From FSM to Truth Table
Output Equation
PCWrite state0 + state9
PCWriteCond state8
IorD state3 + state5
… …
NextState0 state4 + state5 + state7 + state8
+state9
NextState1 state0
NextState2 state1 • ((op = ‘lw’) + (op = ‘sw’))
NextState3 state2 • (op = ‘lw’)
… ...
Output Current states
0 1 2 3 4 5 6 7 8 9
PCWrite 1 0 0 0 0 0 0 0 0 1
PCWriteCond 0 0 0 0 0 0 0 0 1 0
IorD 0 0 0 1 0 1 0 0 0 0
… … 17 18

4-bit Next State: {NS3, NS2, NS1, NS0}

NS0 is 1 for the following next state
0001, 0011, 0101, 0111, 1001

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 21 22

O p5

O p4
ROM Implementation
O p3

O p2
° Need a ROM of 10-bit address, 20-bit word (16-bit datapath control, 4-bit next
O p1 state)
O p0 Address ROM content
S3
op S Datapath control NS
S2
000000 0000 100101000000100
S1
000000 0001 000000000011000
S0
000000 0010 000000000010100
P C W r it e
P C W r it e C o n d
Io rD
M em Read 000000 1010
PLA Implementation M e m W r it e
I R W r it e
M e m to R e g
P C S o u rce 1
P C S o u rce 0 000000 1111
ALU O p1
ALU O p0
A L U S rc B 1
000001 0000
A L U S rc B 0
A L U S rc A
R e g W r it e
R egD st 000010 0000 100101000000100
NS3
NS2
NS1
000010 0001 000000000011000
NS0
000000 0010 000000000010100
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ROM Implementation(Truth Table)
Address ROM content
op S Datapath control NS
000000 0000 100101000000100 0001
000000 0001 000000000011000 0110
000000 0010 000000000010100 xxxx

000000 1010 Could break up into

two smaller ROMs
000000 1111
000001 0000

000010 0000 100101000000100 0001

000010 0001 000000000011000 1001
000000 0010 000000000010100 xxxx

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ROM vs PLA Use Counter for Sequence Control

° ROM: use two smaller ROMs (Fig. C.3.7, C.3.8) C ontro l un it P C W rite
P C W rite C on d
• 4 state bits give the 16 outputs, 24x16 bits of ROM IorD
M e m R ea d
PLA o r R O M M e m W rite
• 10 bits (op + state) give 4 next state bits, 210x 4 bits of ROM IR W rite
BW rite
• Total = 4.3K bits of ROM (compared to 210x 20 bits of single O u tp uts M e m toR eg

ROM implementation) P C So urce

A LU O p
A LU S rcB
° PLA is much smaller A LU S rcA
R eg W rite
R eg D st
• can share product terms In pu t AddrC tl

• only need entries that produce an active output 1

• can take into account don't-cares Sta te

• Size is (#inputs × #product-terms) + (#outputs × #product-

Ad de r

terms) A ddress select log ic

For this example = (10x17)+(20x17) = 460 PLA cells

Op[5– 0]
° PLA cells usually about the size of a ROM cell (slightly bigger)
Instruc tion registe r
op code field

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Address Select Unit
Dispatch ROM 1 Dispatch ROM 2
AddrCtl Value:
PLA or ROM Op Opcode name Value Op Opcode name Value
000000 R-format 0110 100011 lw 0011
0 Set state to 0 jmp sw
000010 1001 101011 0101
1
1 Dispatch ROM 1 beq
000100 1000
State 2 Dispatch ROM 2 100011 lw 0010
3 Use incremented 101011 sw 0010
Adder
state
Mux AddrCt
3 2 1 0 State number Address-control action Value of AddrCtl
0 Use incremented state 3
0 1 Use dispatch ROM 1 1
2 Use dispatch ROM 2 2
Dispatch ROM 2 Dispatch ROM 1 3 Use incremented state 3
4 Replace state number by 0 0
Address select logic 5 Replace state number by 0 0
6 Use incremented state 3
Op

7 Replace state number by 0 0

Instruction register
opcode field 8 Replace state number by 0 0
9 Replace state number by 0 0

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Controller Design Review Microprogram

° Several possible initial representations, sequence control and ° Control is the hard part of processor design
logic representation, and control implementation => all may be • Datapath is fairly regular and well-organized
determined indep. • Memory is highly regular
• Control is irregular and global
Initial Rep. Finite State Diagram Microprogram
° But, the state diagrams that define the controller for an
instruction set processor are highly structured
Sequencing Explicit Next State Microprogram
Control Function Counter + • Use this structure to
Dispatch ROMs construct a simple sequencer datapath control
“microsequencer” control
• Control reduces to
Logic Rep. Logic Equations Truth Tables programming this microinstruction
simple device
Implementation PLA ROM
=> microprogramming …..
micro-PC
sequencer control
signals
“hardwired control” “microprogrammed control”

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Microinstruction Designing a Microinstruction Set

° Control signals : 1) Start with a list of control signals

• Think of the set of control signals that must be asserted in
a state as an instruction
• Executing a microinstruction has the effect of asserting the
control signal specified by the microinstruction
° Sequencing
• What microinstruction should be executed next ?
- Execute sequentially (next state unconditionally)
- Branch (next state also depends on inputs)
° A microprogram is a sequence of microinstructions executing
a program flow chart (finite state machine)
2) Group signals together that make sense (vs. random): called
fields
3) Places fields in some logical order
(e.g., ALU operation & ALU operands first and microinstruction
sequencing last)
4) Create a symbolic legend for the microinstruction format,
showing name of field values and how they set control signals
• Use computers to design computers
5) To minimize the width, encode operations that will never be
used at the same time

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 Control Signals
The Microprogram
Field name Value Signals active Comment
Add ALUOp = 00 Cause the ALU to add.
ALU control Subt ALUOp = 01 Cause the ALU to subtract; this implements the compare for
branches.
Func code ALUOp = 10 Use the instruction's function code to determine ALU control.
SRC1 PC ALUSrcA = 0 Use the PC as the first ALU input.
A ALUSrcA = 1 Register A is the first ALU input. ALU Register PCWrite
B ALUSrcB = 00 Register B is the second ALU input.
SRC2 4 ALUSrcB = 01 Use 4 as the second ALU input. Label control SRC1 SRC2 control Memory control Sequencing
Extend ALUSrcB = 10 Use output of the sign extension unit as the second ALU input.
Extshft ALUSrcB = 11 Use the output of the shift-by-two unit as the second ALU input. Fetch Add PC 4 Read PC ALU Seq
Read Read two registers using the rs and rt fields of the IR as the register
numbers and putting the data into registers A and B.
Add PC Extshft Read Dispatch 1
Write ALU RegWrite, Write a register using the rd field of the IR as the register number and
Register RegDst = 1, the contents of the ALUOut as the data.
Mem1 Add A Extend Dispatch 2
control
Write MDR
MemtoReg = 0
RegWrite, Write a register using the rt field of the IR as the register number and
LW2 Read ALU Seq
RegDst = 0,
MemtoReg = 1
the contents of the MDR as the data. Write MDR Fetch
Read PC MemRead,
lorD = 0
Read memory using the PC as address; write result into IR (and
the MDR).
SW2 Write ALU Fetch
Memory Read ALU MemRead, Read memory using the ALUOut as address; write result into MDR. Rformat1 Func code A B Seq
lorD = 1
Write ALU MemWrite, Write memory using the ALUOut as address, contents of B as the Write ALU Fetch
lorD = 1 data.
ALU PCSource = 00 Write the output of the ALU into the PC. BEQ1 Subt A B ALUOut-cond Fetch
PCWrite
PC write control ALUOut-cond PCSource = 01, If the Zero output of the ALU is active, write the PC with the contents JUMP1 Jump address Fetch
PCWriteCond of the register ALUOut.
jump address PCSource = 10, Write the PC with the jump address from the instruction.
PCWrite
Seq AddrCtl = 11 Choose the next microinstruction sequentially.
Sequencing Fetch AddrCtl = 00 Go to the first microinstruction to begin a new instruction.
Dispatch 1 AddrCtl = 01 Dispatch using the ROM 1.
Dispatch 2 AddrCtl = 10 Dispatch using the ROM 2.

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The Controller The Dispatch ROMs

C o n tro l u n it P C W r ite
P C W r ite C o n d
Io rD
Dispatch ROM 1
M icr o c o d e m e m o ry M em R ea d
M e m W rite
D a ta p a th Op Opcode name Value
IR W rite
000000 R-format Rformat1
0110
B W rit e
O u t p u ts M e m to R e g
P C S o u rc e 000010 jmp JUMP1
1001
ALUOp
A L U S rc B 000100 beq BEQ1
1000
A L U S rc A
R e g W rite
R eg D st
100011 lw Mem1
0010
A d d rC tl
In p u t
101011 sw 0010
Mem1
1

M ic ro p ro g ra m c o u n te r

A dder
Dispatch ROM2
A d d re s s s e le ct lo g ic
Op Opcode name Value
Op[5– 0]

100011 lw LW2
0011
101011 sw SW2
0101
In s tru c tio n r e g is te r
o p co d e fie ld

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