SSAP.I i a computer because it stores a program and data before calculations begin; then it automatically caries out the program instructions without human intervention. Ad Yet, SAP-1 isa primitive computing machine. Ie compares toa modern computer the way a Neandertal human would ‘compare ta modern perso. Something is missing, some thing found in every modem computer SAP-2 js the next step in the evolution toward moder computers because itinclades jump instructions. These new imsructons force the computer to repeat or skip part of rogram. AS you will discover, jump instructions open up 4 whole new word of computing power 11-1 BIDIRECTIONAL REGISTERS To reduce the wiring capacitance of SAP-2, we will ran only one set of wits between each register and the bus Figure 11-La shows the idea. The inpot and output pins are shorted: oly one group of wire is connected to the bus Dos this shoring the input and outpt pins ever cause tmoable? No. During a computer ran, either LOAD o¢ ENABLE may be active, but po both at the same time. An active LOAD means that a binary word lows fom the bas to the register input during a Toad operation, the output lines are floating. On the ober hand, an active ENABLE meats that a binary word flows from the register 10 the bs inthis case, the inp ines fou ‘The IC manufacturer can internally connect he inpt aed ‘output pins of a three-state register. This nt only reduces the wiring capacitance; it also reduces the number of LO pins. For instance, Fig. 11-16 has four VO pins instead of ight, Figure 11-1 the symbol for a three-state register with inteally coonesed input and output pins. The double- headed arrow reminds us tht the path is Bidirectional: dts can move either way. 11-2 ARCHITECTURE Figure 11-2 shows the architecture of SAP.2, All register ‘outputs to the W bus are three-state; thse not connected Woe bus are two-site. As before, the controller sequencer sends control signals (aot shown) to each register. These onto signas load, enable, orotberise prepa the register forthe next postive cock edge. bret description ofeach box is given now Input Ports SSAP-2 has two input pons, numbered 1 and 2. A herade- ‘imal Keyboard encoder is connected t0 port 1. allows 1s fo ener hexadecimal instructions and data through port 1. Notice thatthe hexadecimal keyboard encoder sends a ‘READY signal obit O of por 2. This signa indicates when the data in port is valid. Also notice the SERIAL 1N signal going opin 7 of port 2. A later example will show you how to convert serial impat data to parallel dita, Program Counter This time, the program counter has 16 bits; therefor, it «an count from PC = 0000 0000 000 0000 un nanan ‘This is equivalent to O000H to FFFFH, oF decimal 0 to 65535. A low CLR signal resets the PC before each computer run; so the data processing stats withthe instruction stored in memory location O000H, 173cx—p te Tope Fig. It Bidston reise (MAR and Memory During the fetch eye, the MAR receives I6-it addresses ‘om te program counter. The two-state MAR output then adresses the desired memory location. The memory has 2 2K ROM with adresses of QODDH to OTFFH. This ROM. ontins a program called a monitor that inilizes the ‘computer on power-up, interprets the Keybourd inputs, and so forth, The rest of the memory is 2 62K RAM with aresses from OBDOH to FFFFH. ‘Memory Data Register ‘The memory data ester (MDR) ian 8-it buffer register. Is output ses up the RAM. The memory data register receives data fom the bus before awrite operation, and it Sends data tothe bus after ated operation. Instruction Register ‘Because SAP-2 has mor instructions than SAP-1, we wll se 8 bts for the op code rather than 4, An Bit op code can accommadate 256 instructions. SAP-2 has only 42 174 digtat computer Electronics instructions, so there willbe no problem coding them with 8 bits. Using an $-bit op coe also allows upward compat: ily with the 80808085 instruction set because itis based ‘on an S-it op code. As mentioned earlier, all SAP instructions ar iesial with SOSOBOSS instructions. Controller-Sequencer The conor sequencer produces the contol words or microinsrctons tht coordinate and direct the rest of the ‘computer. Because SAP-2 has a bigger instruction set, the como sequencer has more hawar. Although the CON word i bigger, the idea isthe same: the contol word or microinstrcton determines how the reps react to the ext positive clock ede, Accumulator ‘The tworsate ouput ofthe accumulator goes to the ALU; the three-state output to the W bus. Therefore, the 8bit word in the accumulator continuously dives the ALU, but this same word appears on the bus only when Es activeacevomecet —lHoatninw P| wot Los} oe [ TY scevwtaron TA sresy Ole . pate LA 1] = av EN nes semen] tt ea) 5 BOS w 7] co am . a ig SAP2 block white, ALU and Flags Standard ALUs ae conmerialy availble a inter cicnis, These ALUs tae 4 oF toe contol bis at Aeterine the atthe: lope operation performed on ‘ord A and, The ALU wid in SAP. ices artic 2 logic operons In ths Bok a flag is a ipo hat keeps rack of changing condkon daring a ‘competr nn. The SAP-2 compe has to tgs. The sig lop st when the ‘ccomultor comes Deo net sr he exon Omen Meadecima wr et tnt mea i semis oor o SE we Pe scemcnceoce of some instructions. The zero flag is set when the accu- ‘multor contents become zero, ‘TMP, B, and C Registers Instead of using the B regis o hold the data being aed or subtracted from the accumlator. a temporary (TMP) register is wed. This allows us more freedom in using the Brepise. Besides the TMP and Breistrs,SAP-2 includes aC register. This gives us more flexibility in moving data during a comptes run. Chapter 11 sap2 175Output Ports SAP-2 has two output ports, numbered 3 and 4. The contents of the ascumlator can be leaded into pot 3, ‘which drives a hexadecimal display. This allows ust se the procesed data "The costes ofthe sccumlator can also be seat 0 pot 4. Notice that pin 7 of port 4 sends an ACKNOWLEDGE signal to the hexadecimal encode. Ths ACKNOWLEDGE Signal andthe READY signal are par of a concept called handshaking, tobe discussed hte. ‘Aso notice the SERIAL OUT signal from pin 0 of port “4, one of the examples will show you bow to conver parallel dita inthe accumulator ino serial owput data, 11-3 MEMORY-REFERENCE INSTRUCTIONS “The SAP-2 ftch cycle isthe same as before. Tis the ‘adress stat, 7 isthe increment sate, and 7, the memory sate, All SAP-2 instructions therefore use the memory ‘ering the Fetch eycle because a. program instruction is transfer rom the memory to the instuction register. Daring the execution cyee, however, the memory may ‘or may not be used it depends on the type of instruction that his boen fetched. A memery-efrenc insction (MRI is one tat uses the memory dating the exeetion ele ‘The SAP-2 computer hss an instruction set with 42 instructions. What follows isa description ofthe memory: reference instreton, LDA and STA [LDA has the sume meaning as before: lad the accumulator withthe adresed memory daa. The ony iffereace is that more memory Ineations can be accesed in SAP-2 because the adresses ae from OICOH to FFFFH. For example, LDA 2000H means t lead tbe ascumulator with the contents of memory location 200. To distinguish the diferent prs of an instraston the mnemonic is sometimes called the op cde andthe rest of the instntion isknown athe operand. With LDA 20001, LDA is te opcode and 2000H isthe operand. Therefore, "opcode has a double meaning in microprocessor work, ity stand fo the maemenic or Fr the Baary code used to represent the mnemonic. The intended meaning is clear fro the context. 'STA isa mnemonic for store the accumulator. Every SIT inseuction needs an adiss. STA TFFFH means 19 store the accumulator conten at memory location TFFFH, " A= sai the execution of STA 7FFFH stores BAH at adress FFF, 176 digtat Computer tiecroics vt MVL is the mnemonic for move immediate. It tells the ‘computer to lad a designated repser withthe byte tat immediately follows the op code. For instance, MVIASTH tel the computer to load the accumulator with 37H. After this instruction hasbeen executed. the binary contents of the acumolatoe ae A= coro ‘You can use MV with the A, B, and C registers, The formas for hese instructions ae MVE A.bye MVI Byte MVI Cy Op Codes Table 11-1 shows the op codes forthe SAP.2 insircton set. These are the SO8OBDRS op codes. As you can see, 3A isthe op code for LDA, 32 i the op code for STA, ttc. Refer to this able i the remainder ofthis chapter EXAMPLE 11-1 ‘Show the mnemonics for a program that leads the accu ‘mulator with 49H, the B register with 4AH, andthe C register with 4BH: then have the program sore the accu ‘molto data st memory location 628SH. SOLUTION Here's one program that will work: Mnemonics MYL. MVIBAAH. MVIC ABH STAG2SSH HT “The fs thee instruction loud 49H, 4AH, and ABH into the A Band registers. STA 628SH sores th accumlator contents 3 62854, Note the use of HLT inthis rogram, It has the same meaning a before: halt the data processing,‘TABLE 11-1. SAP-2 OP CODES Instraction Op Code Instruction Op Code ADD B 80 MOVBA ” ADDC 31 MOVBC 4L ANAB AQ MOVCA F ANAC AL MOVCB 4 ANT byte BH MVIA‘yte —3E. CALL addess = CD MVIBibyte 06 CMA 2F -MVICtye OE DOR A. 3D NOP 0 DCR B 05 ORAB Bo DCR C oD oRAC BL HLT 76 ORL byte 6 INbye DB OT byte Ds INRA aC RAL 7 INRB. 0} RAR IF INRC oc RET ° IM address FA STAabdress 32 IMP address C3. SUBB 0 INZaddress = C2_— SUB oT Tairess CA XRAB AB LDA adress. == 3A. XRAC a9 MOV A.B 78 XRLbyte EE Mov A.c 9 EXAMPLE 11-2 ‘Translate the foregoing program into 8080/8085 machine language using the op codes of Table H1-1, Stat with ress 2000H, SOLUTION Address Contents Symbolic 2000 3H MVIA.OH 201K 9H 20008 6H MIB SAH 203K 4AH 2004 oe MVIC4BH 200K BH 20064 2H STA 628SH 2007H as 08H oH 200981 76H aur ‘Thete are couple of new ideas inthis machine-language program, With the MVIA,9# {nsructon, notice that te opcode goes into the fs adress and the byte imo the second address. This is true of all 2- byte instructions: op code into the fist avilable memory locaton and bye into the next The insration STA 62851 is a Mbyte instruction (1 byte forthe op code and 2 forthe address). The op code for STA is 32H. This byte goes into the fist availble memory location, whichis 20061. The tudress 6285H has 2 bytes. The lower byte 85H goes into the next memory locaton, and the uppe byte 62H int the next locaton ‘Why does the adiress get programmed withthe lower byte first andthe upper byte second? This is a peculiarity ‘ofthe original 880 design. To keep upward compatibility, the SORS and some other microprocessors use the same scheme: lower byte into lower memory, upper byte into upper memory. ‘The last instruction HLT hasan op code of 76H, stored in memory location 2000H, In surumary, the MVI instructions are 2-byt instructions, the STA is a Mbyte instruction, andthe HLT is a L-byte insietion, 11-4 REGISTER INSTRUCTIONS. ‘Memory-eference instructions are relatively slow because they requite more than one memory access during the inscwction cycle. Furthermore, we often want o move data Aretly fro oe reser to another without having wo go through the memory. What follows ae some of the SAP. 2 register instructions, designed to move data from one register to another inthe shortest possible time MOV is the mnemonic for move. It tls the compute to move data from ove register to anotber. For instance, MOV A.B tells the computer to move the data inthe B register to the accumulator. The operation is nondestructive, meaning tat the data in B is copied but not erased For example, if A= MH and B= 9DH then the execution of MOV A,B results in Chapter 11 Sapa 177‘You can move dis between the A,B, and C registers. ‘The formats for all MOV insrtion ae MOV AB MOVAC MOV B.A MOVB.C MOVCA MOVCB ‘These instructions are the fastest inthe SAP-2 instruction set, requiring only one machine cycle ‘ADD and SUB [ADD stands for athe data inthe designed register to the accumulator. Fe instance, ADD 8 means to the contents of the Brepster 1 the accu ‘uate. IF A= Ou and B= 02H then the execution of ADD B resus in A= 06H Simialy, SUB means subtract the data inthe designate register from the accumulate. SUB C will sabeact the contents of the C regis from the accumulate, The formats for the ADD and SUB instrctons are ADDB. ADOC SUBB suBC INR and DCR “May ines we wart increment or decrement the contents cof on of the regis. INR isthe mnemonic fr increment: it tells the compuser to incremet the designated register. DDR is the mnemonic for decrement, and it iasracs the ‘ompaterto decrement the designated register. The formats for these instructions ace INRA INRB. INRC DRA DERE ERC Asan example, if B= sett and C= AN 178 digital computer Blctronis then the execution of INR B results in 7H and the exccuion of a DCR C produces c= 9H EXAMPLE 11-3 Show the mnemenics for adding decimal 23 and 45. The answer isto be stored at memory location S6OOH. Aso, the answer incremented by | iste sted inthe C reise. SOLUTION As show in Appendix 2, decimal 23 and 45 are equivalent to 17H and 2DH. Here is program tat wil do the job Mnemonics MVIA,ITH. MVIB.20H. ADDB. STA SacOH, INRA, MOVCA ALT EXAMPLE 11-4 To hand-esemble a program means to tanshte a source program ito machine language program by hand rather than machine Haed-asemble the program ofthe preceding example trig a adeess 20008 ‘SOLUTION Adress Contents Symbolic 20008 3H MVLA,ITH 20018 mH 2002H att MVIB,2D11 2003H 2H 20041 sont ADD B 200H 3H ‘STA SdH 26H oH 2007H Slt 20a 3cH INRA 2911 aru MOV CA 200A 76H HLT Novis thatthe ADD, INR, MOV, and HLT instructions see I-byte instructions: the MVI insttions ate 2yte insrctons, and the STA i a Mbyte insrction,11-5 JUMP AND CALL INSTRUCTIONS ‘SAP-2 has four jump instructions; these can change the rogram sequence: In other words, instead of fetching the ‘ext instruction inthe usual way, the computer may jump ‘oF branch o another pat of the program. To begin with, JMP isthe mnemonic for jump; it wells the ‘computer to get the next instruction ftom the designated ‘memory locaton. Every JMP instruction includes an aress that is loaded imo the program counter. For instance, IMP 30008 tells the computer to got the next instruction from memory Jocaton 30001 on 00H 20s ne 00H 210-304 2081 —— Sop ae xo —— = mor —— +] Fig 13 (a) Uncocitionl jump: () conditional jamp, Here is what happens. Suppose JMP 3000H is stored a 200SH, as shown in Fig. I-3a. At the end of the fetch exee, the program counter contains PC ~ 200611 Daring the execution eycle, the IMP 3000H loads the program counter withthe designated address: PC = 3000H When the next fetch cycle begins, the next instruction comes from 3000H rather than 2006H (see Fig. 11-30). mM ‘SAP-2 has two flags called the sign flag and the zero flag. Daring the execution of some instructions, these lags will be set or reset. depending on what happens to the accu- rmulator contems. If the accumulator contents. become negative the sign flag willbe set; otherwise, the sign fag is cleared. Symbotcally, 0 s-{° whee stds fo sg ap. The sign fg wl emi et Cx ear nil anther operon hat os the ag JM isa monic for jump ms he cmp il jump a eign a ny te ign i Set As an example, supose a 1M MOOK i sted t 200SH, Afr arto as be eed ifa>o ifa ‘ments follow.) Labels are anotber programming aid used wih jumps and calls. When we write an assembly-anguage program, we often have no idea what address to use in a jump ot call instruction, By using a label instead of a numerical ‘address we can write programs that make sease tous. The ‘assembler will Keep track of our labels and automatically ‘assign the correct addresses to them. This is a great Iaborsaving feature ofan assemble. For instance, when the assembler convers the foregoing ‘program to machine language, it will replace JZ. by CA (op ‘code of Table 11-1) and END by the address ofthe HLT inruction. Likewise, twill epace IMP by C3 (op cose) and REPEAT by the address of the DCR C instruction ‘The assembler determines the addresses ofthe HLT and IMP by counting the mmber of bytes needed by all instructions and figuring out where the HLT and DCR C ‘nsructons willbe inthe final assembled program. All you bave to remember i that you can make up any label you want for jump and eal instructions. The same label fellowed by acolo is placed in foot of the instruction you are trying to jump to. When the assembler conver ‘Your program into machine language, the clon tells ita label is involved. ‘One more point about labels. With SAP-2, the labels can be from one to six characters, the fist of which must be a Fete. Labels are usually words or abbevitions, but rmumbers can be included. The following are examples of acceptable labels: REPEAT DELAY RDKBD AM BI2C3 ‘The fist two ae words; the thd isan abbreviation for read the Keyboard. The lst two are labels that include numbers. The restitions on length (90 more than six 182 Digtat Computer Electronics characters) and stating character (must ele) are typical of commercially available assemblers, EXAMPLE 11-8 ‘Show a program that multiplies decimal 12 and & SOLUTION ‘The hexadecimal equivalents of 12 and 8 are OCH and (GH, Let us set up a Toop that adds 12 to the accumulator during each pass. If the computer loops 8 times, the accumulator contens will equal 96 (decimal) atthe end of ‘the looping, Here's one assembly-language program that will do the Mnemonic Comment MVLA,0OH Clear accumulator MVLB.OCH Load docimal 12 into B MVICOSH ‘Preset counter with 8 REPEAT: ADD B {Ad decimal 12 DCR C :Decrement te counter TZDONE Test for ero IMP REPEAT Do it again DONE: HLT ‘Stop it The comment el| most ofthe sry. Fin, we lar the actuals, Net, we load dina 2 ino he B reir Then he coun pee decimal 8 Tes rt he insraons we pan of he nialzion before eneig a top. ‘The ADD B begins the loop by adding decimal 12 to accumu, The DOR € reds the out 7 Since the ‘zero flag is clear, JZ DONE is ignored the first time through tod the rogram forest the ADD B instruction. "You shold te abl ee wha wl happen. ADD B is ine the lop and wl be excited 8 times, Aer ight pares trough the lop the zo agi ct ten the 1 DONE wil ake he progam out of te lop the HLT inaction ‘ne 12 sade ines, N+ N+ D+ R+R+R+2+2=% (Because decimal 96 is equivalent to hexadecimal 60, the accumulator contains 0110 0000.) Repeated addition like this is equivalent to makiplicaton, In other words, adding 12 eight times is identical to 12 X 8, Most microprocessors 60 not have mukiplication hardware; they only have an ader-subtracter like the SAP computer. Therefore, with the typical microprocessor, you have to use some form of programmed multiplication such a repeated additionEXAMPLE 11-9 Modify the foregoing, multiply program by using a INZ instead of a JZ. SOLUTION Look at this: Label Mnemonic Comment MVIA,OOH Clear acumelator MYIBOCH Load decimal 12 ito B MVI-COSH Preset counter with 8 REPEAT: ADD B Add decimal 12 DeRC ‘Decrement the counter INZ REPEAT Test for 2e0 MLT ‘Stop it ‘This is simpler. I eliminates one JMP instruction and one label. As long a the counter is greater than zero, the JNZ. ‘will force the computer to loop back to REPEAT. When the counter drops to zero, the program wil fll through the INZ.to the HLT. ing program stating at address SOLUTION Address Contents Symbolic 20008 3EH MV A.00H 2001 ‘08 20028 6H MVI BOCH 20038 ocH 20041 OBH MVI, C08H 20038 os 20068 80H ADD B 20071 oDH DcR 2008, OH NZ. 2006H 20098 OH 200AH 20H 2008H 76H HLT The first thre instructions initialize the registers before the ‘multiplication begins. If we change the inital values, we can multiply other numbers EXAMPLE 11-11 ‘Change the multiplication part of the foregoing program ino a subroutine located at starting address POOSH. SOLUTION Address Contents ‘Symbolic Fon6tl 80H ADD B OOH oDH Der OSH OH INZ FOOGH. FoO9H oH FooAH Fou. FooH OH RET Here's what happened. The initlizng instructions depend ‘onthe numbers we are multiplying, so they don't belong ‘he subroutine, The subroutine should contain only the In relocating the program we mapped (converted) a- sdeesses 2006H-200BH to FOO6H-FOOBH. Also, the HLT ‘was changed to 1 RET to get ws back to the original program. EXAMPLE 11-12 The multiply subroutine of the preceding example i used in the following program. What does the program do? MVLAOOH MVIB,108 MVICOEH CALL RIGHT HLT SOLUTION Hexadecimal 10H is equivalent to decimal 16, and hexa- decimal OEH is equivalent to decimal 14. The fst three instructions clear the accumulator, Joad the B register with decimal 16, and preset the counter to decimal 14. The ‘CALL sends the computer to the multiply subroutine ofthe ‘preceding example. When the RET is executed, the acu- imulator contents are EOH, which is equivalent to 224 Incidentally, a parameter is a piece of data that the subroutine needs to work properly. The mukiply subroutine located at POOGH needs thee parameters to work properly (A, B, and ©). We pass these parameters tothe multiply subroutine by clearing the accumulator, leading the B register with the mulkiplicand, and preseting the Crepister with the multiplier. In other words, we st A = OOH, B= 10H, and C = OEH, Passing data to subroutine in this way is called repiter parameter passin. Chapter 11 sap2 18311-6 LOGIC INSTRUCTIONS [A microprocessor can do logic aswell a arithmetic, What follows are the SAP-2 logic instructions. Again they ae 2 subse ofthe 8080/8085 instructions. cMA CMA stands for “complement the sccumltor.”* The ‘execution of a CMA inverts each bit in the accumulator, producing the 1's complement ANA ANA. means 10 AND the accumulator contents with the designated register. The results toed in the accumulator. For instance, ANAB ‘means to AND the contents of the accumulator with the contents of the B register. The aNDing is done on a bit-b- bit basis. For example, suppose the two registers contain ‘A = 1100 1100 ay B= 1111 0001 aa) ‘The execution of an ANA B results in ‘A = 1100 0000 [Notice thatthe ANDing is bitwise, a illustrated in Fig. 11-6. The Anping is done on pairs of bits; A, is xNDed with By, Ag with By, Ay with Bs, and so on, with the result stored inthe accumulator. ‘Two ANA instructions are availabe in SAF and ANA C. Table 11-1 shows the op codes ANAB ORA ORA is the mnemonic for OR the accumulator with the designated register. The two ORA intrctions in SAP-2 are ORA B and ORA C. Asan example, ifthe accumulator and B register contents are given by Eqs. U-1 and 11 then executing ORA B gives A 11 1101 XRA XRA means xow the accumulator with the designated register. The SAP.2 instruction set contains XRA B and 184 digat computer Electronics (Gram) Geeta)» Fig, 1.6 Logic instructions ae bitwise XRA C. Ifthe accumulator and B contents are given by gs. 11-1 and 11-2, the exceuton of XRA B produces ‘A= 0011 1101 ANI ‘SAP-2 also has immediate logic instructions. ANI means AD immediate tells the computer to AND the accumulator ‘conten withthe bye that immediately follows the opcode For instance, if A= 0101 110 the excution of ANI CTH will x 101 110 with 11000111 to produce new accumu conten of A = 01000110 ont ORI isthe mnemonic for ok immediate. The accumulator conten are Oked with the byte that follows the op code. 7 A= 0011 1000 the execution of ORI SAH will 8 0011 1000 with 0101 1010 to produce new accumulator contents of 111 1010 xa XR meats xom immediate. I ‘A=0001 1100 the execution of XRI Dsl wil xo oor 1100 with 1101 e100 to produce 100 100011-7 OTHER INSTRUCTIONS ‘This section looks at the last of the SAP-2 instructions. Since thse instructions don't fit any pancular category, they are being collected here in a miscellaneous group, NOP stands for no operation. Duting the execution of a NOP, all T states are do nothings. Therefore, no register ‘changes occur during 2 NOP. The NOP instruction is used to waste time. It takes four T states to fetch and execute the NOP instruction. By repeating « NOP 2 number of times, we can delay the data Processing, which is useful in timing operations. For instance, if we put « NOP inside a loop and execute it 100 times, we create atime delay of 400 T states, HLT We have already used this. HLT stands for halt. It ends the data processing N IN is the mnemonic for input. It tells the computer to teansfer data from the designated port to the accumulator, Since there are two inpot ports, you have to designate which is being used. The format for an input operation is IN byte For instance, IN OH ‘means to wansfer the data in port 2 tothe accumulator. our ‘OUT stands for opi. When this instruction is executed, the accumulator wor is loaded nto the designated output ot, The format for this instruction is OUT byte Since the ouput ports are numbered 3 and 4 (Fig. 11-2), YOU have to specify which port i to be used. Fo instance, our os will ransferthe contents ofthe accumulator to port 3. RAL RAL is the mnemonic fo rotate the accumulator left. This ‘nructon will shift all bits the left and move the MSB. =o) Oss w w lg. 1-7 Rote isictons: (a) RAL; (b) RAR, ito the LSB postion, as illustrated in Fig. 11-7a, As an ‘example, suppose the contents ofthe accumulator are ‘A= 1011 0100 Executing the RAL will produce ‘A= 0110 1001 ‘As you see, LSB position. bis moved left, and the MSB. went to the RAR RAR stands for rotate the accumulator right, This time, the bits shift to the right, the LSB going to the MSB position, as shown in Fig, 11-75. If A= 1011 0100 the execution of a RAR will resul in A= 0101 1010 EXAMPLE 11-13 ‘The bits in a byte are mumbered 7 to 0 (MSB t0 LSB). ‘Show a program that can input a byte from port 2 and determine if bit 0 isa 1 or 20. I the bit sa 1, the program {sto load the accumulator with an ASCII Y (yes). Ifthe bit is 0, the program should load the accumulator with an ASCII N (no). The yes or no answer is 1 be sent 10 ‘output port 3. SOLUTION Label Mnemonic Comment IN 02H Get byte from port 2 ANIOIH Isolate bit 0 INZ YES Jump if bt 0 isa 1 MVLAEH Load N into accumulator JMP DONE Skip next instruction MVLA.S9H Load Y into accumulator DONE: — OUTO3H Send answer to por 3 HLT Cchapuer 11 SAP.2‘The IN O2H transfers the contents of input port 2 to the accumulator to get A= AAMAS ‘The immediate byte in ANI OIH is (000 0001, ‘This byt is called a mask because its Os will mask or blank ‘out te coresponding high bits nthe accumulator, In other ‘words, after the execution of ANT OI the accumulator conten are ‘A = 0000 000A, If Asis 1, the JNZ. YES will produce a jmp to the BVI |AS9H; this loads « SOH (the ASCIL for ¥) info the accumulator. If Ay is 0, the program falls through tothe MVI ASEH. This loads the accumulator withthe ASCIL foe N. ‘The OUT 03H loads the answer, either ASCII ¥ or N, ‘mo por 3. The hexadecimal display therefore shows either 58H or EH, EXAMPLE 11-14 Instead of a parallel ouput at port 3, we want a serial ‘utp st port 4. Modify the foregoing program so that it converts the answer (S9H or 4EH) into serial outpat at bi 0, port 4 SOLUTION Label Mnemonic Comment Ion ANLOIH, INZ YES MVI AEH IMP DONE, YES: MVIA,SIH DONE: © MVICOSH Lond counter with 8 AGAIN: OUTOMH Sead LSB to port 4 RAR ‘Position next bit Der c :Decrement count INZAGAIN “Test count HLT In converting frm parle to serial data, the Ay biti sent frst, them the A bit, then the Abit, and so 186 Digtat computer Electronics EXAMPLE 11-15 Handshaking is an iateracton between a CPU and a peripheral device that aks place during an UO data transfer. In SAP-2 the handshaking takes place as follows. After you enter two digits (1 byte) imo the hexadecimal encoder ‘of Fig. 11-2, the data is loaded into port 1; at the same time, «high READY bits sen o pot 2. ‘Before accepting input data, the CPU checks the READY bitin port 2, Ifthe READY bit is low, the CPU waits. If the READY bit is high, the CPU loads the data in pot 1 ‘Afr the data transfer is finished, the CPU sends high ‘ACKNOWLEDGE signal to the hexadecimal Keyboard en- ‘oder this eset the READY bitto0. The ACKNOWLEDGE bit then is eset to low. ‘Afer you key in anew byte, the cycle stars over with new data going to the pot I anda high READY bit vo port ‘The sequence of SAP-2 handshaking is 1 READY bit (bit 0, por 2) goes high 2 put the data in port 1 to the CPU: 3. ACKNOWLEDGE bit (bit 7, por 4) goes high wo reset READY bit. 4 Reset the ACKNOWLEDGE bit. Write a program that inputs a byte of data from port 1 using handshaking. Store the byte inthe B register. Label Mnemonic Comment STATUS: IN O2H Input byte fom port 2 ANLOIH Isolate READY bit JZSTATUS. Jump back if not ready INOIH Transfer data in port 1 MOV B.A Transfer from A to MVIA.S0H ;Set ACKNOWLEDGE bit OUT 04H Output high ACKNOWLEDGE MVLA,OOH Reset ACKNOWLEDGE bit OUT 04H Output low ACKNOWLEDGE HLT Ifthe READY bit is low, the ANE OH will force the accumulator contents to go to 220. The JZ STATUS therefore wil oop back to IN 02H. This looping. will contin until the READY biti high, indicating vali data in por 1 ‘When the READY biti high, the program falls trough the IZ STATUS to the IN OIHL. This transfers a byte from port 1 to the accumulator. The MOV sends the byte othe B register. The MVI A,$OH sets the ACKNOWLEDGE bit(bit 7). The OUT OSH sends this high ACKNOWLEDGE: to the hexadecimal encoder where the intemal hardware resets the READY it. Then the ACKNOWLEDGE tit is ‘eset in preparation for the next input cycle, 11-8 SAP-2 SUMMARY ‘This section summarizes the SAP-2 T states, fags, and addressing modes. T States ‘The SAP-2 contoler-sequencer is microprogrammed with ‘variable machine cycle. This means that some instructions take longer than others to execute. As you real, the idea ‘behind microprogramming is 1 store the control routines ina ROM and access them as needed, ‘Table 11-3 shows each instruction and the number of T States needed to execute it. For instance, it takes four T states to execute the ADD B instruction, seven to execute the ANI byte, eighteen to exocute the CALL, and so on Knowing the number of T states is imporant in timing applications Notice thatthe JM instraction has 7’ states of 107, This ‘means it takes 10 7 states when a jump occurs bt only 7 Without the jump. The sume idea applies to the other conditional jamps; 10 T states fora jump, 7 with n jump. Flags ‘As you know, the accumulator goes negative or ero during the execution of some instructions, This affects the sign and zero fags. Figure 11-8 shows the circuits used in ‘SAP. to set the Ags ‘When the accumulator contents are negative, the leading bit Ay isa 1. This sign bit drives the lower AND gate, When the accumulator contents are zero, all bits are zero and the ‘uiput of the Now gate isa 1. This NOR output drives the ‘pper AND gate. If gating signal Lis high, the fags will be updated to reflect the sign and zero condition ofthe accumulator, This means the Zjz4o ill be high when the sceumulator contents are 2270; the Siac wil be high when the accumulator contents are negative Not all instructions affect the fags. As shown in Table 11-3, the instructions that update the flags are ADD, ANA, ANI, DCR, INR, ORA, ORI, SUB, XRA, and XRI. Why: ‘only these instructions? Because the L, signal of Fig. 1-8 {is high only when these instructions are executed. This is accomplished by microprogramming an Ly bit for each insructon. In other words, in the control ROM we store a high L bit for the foregoing insiructions, and a low L bit forall ober, Fre O}~ Sane Pr Le on Fp Fig 18 Soing the Mas. Conditional Jumps As merioed carer, the condtons jumps tke tea T sites when the jmp occurs ba only sven sates hon jump ake place. Bre, hiss accomplsed flows Daring the exceation cycle the aes ROM sends the computer 10 the string ales of + condition jmp tictoouine. Te inal microinstruction lok tthe age and judges mtbr or nt to jump. Ia amp is inde, ‘he microti continues; otherwise is aborted and the computer begins new fetch eee ‘Addressing Modes The SAP-2 instructions acess data in diferent ways. It is the operand that tells us how the data is wo be accessed, For instance, the first instructions discussed were LDA adress STA address ‘These ae examples of direct addressing because we specify the address where the data is 1 be found. ‘Immediate adacessing is differet. Instead of giving an ‘Mares fr the data, we give the daa itself, Fr instance, MVIA.byte accesses the data o be loaded into the accumulator by using the byte in memory that immediatly follows the op coe. Table 11-3 shows the other immediate instructions ‘An instruction like MOV A,B Chapter 11 sara 187‘TABLE 11-3. SAP-2 INSTRUCTION SET Liciiae renee Tnsrocion Op Code 7 Stats Flags Addressing Hyts ADD B 80 4 SZ Regis ADD 8 4 SZ Regier ANAB M4 SZ Register ANAC al 4 SZ Register ANT byte Be 7 S,Z_ Immediate 2 CALL addess, = CD18 None Immesite 3 CMA, 2F 4 Nome Ini 1 DCR A sD 4 SZ Register DCR B = 4 SZ Repiner, ERC om 4 SZ Reiter HLT 6 S Nowe I IN bye DB 10 None Direct 2 INRA x $ SZ Reginer IRB OF 4 SZ Regier INRC oc 4 SZ Reiner IM address FA 107 None Immediate 3 IMP aldress C3 10 None Immediate 3 IZ address C217 None Immedite 3 WE abies CA 107 None Immediate 3 LDA adress 38 13 None Direct 3 MOV A.B ® 4 Now Register MOV AC ” 4 None Register a 4 None Register =I MOV B.C 4 4 None Repier 1 MOV CA AF None Repiter 1 MOV C.B 8 4 None Regiser MVIAbye © 3E 7 None Immedite 2 MVIBbyte 06-7 (None mediate 2 MviCbyte OE 7 Nome immediate 2 Nop m 4 Noe 1 ORAB Bo 4 SZ Regier RAC Bl 4 SZ Regier OR byte Po 7 S.Z Immediate 2 OUT byte bs 10 None Direct, a RAL "7 4 None Implied 1 RAR 4 None Implied 1 RET o 1 None Implied 1 STAadiess 13 None Direct 3 SUBB 0 4 SZ Regier SUBC 31 4 SZ Regier XRAB. AB 4 SZ Register XRAC AQ 4 SZ Regier XU byte EE 7.2 Immediae 2 isan example of register addressing. The data tobe loaded Implied acressing means that he location ofthe data is js sored in a CPU regiser rather than in the memory. contained within the opcode isi, For instance, Register addressing has the advantage of speed because fewer T stats are needed fo this typeof instuction. RAL 188 Diguat Computer Electronicstells us to rotate the accumulator bits left. The data isin the accumulator; ths is why no operand is needed with implied addressing Bytes Each instruction occupies a number of bytes inthe memory SAP-2 instructions are either 1, 2, or 3 bytes long, Table 1-3 shows the length of each instruction. As you see, ADD instructions are I-byte instructions, ANI instructions ae 2-byle instructions, CALLS are 3-byte instructions, and ‘0 forth EXAMPLE 11-16 SAP-2 has a clock frequency of 1 MHz. This means that cach T state basa duration of 1s. How long does it take {to execute the following SAP-2 subroutine? Label Mnemonic Comment MVICS6H —;Preset count to decimal 70 AGAIN: DCRC ‘Count down INZ AGAIN Test count Nop ‘Delay RED SOLUTION ‘The MVLis executed once to initialize the count. The DCR is exccuted 70 times. The INZ jumps back 69 times and falls through once. With the number of T states given in ‘Table 11-3, we can calculate the total execution time of the subroutine as follows: MVE 1x7 xIps= Ths DCR 10x 4x Ips = 280 INE: X 10 1s = 690 Gump) INZ = 1X 7X Ips= 7 (rojump) NOP 1x4xipse 4 RET. 1x 10x 1us = _10 908 ps = Ls [AS you se, the total time needed to execute the subroutine is approximately 1 ms. A subroutine like this can produce atime delay of 1 ms whenever itis called. There are many applications where you need a delay. According to Table 1-3, the instructions i the foregoing subroutine have the following byte lengths: Instruction | MVI | DCR Bytes snz_| Nop | RET 3 The total byte length of the subroutine is 8. As part ofthe SAP-2 software, the foregoing subroutine can be assembled and relocated at addresses FOLOH to FOITH. Hereafter, the execution of a CALL FOIOH will produce atime delay of Ios. EXAMPLE 11-17 How much time delay does this SAP-2 subroutine produce? Label Mnemonic ‘Comment MVIBOAH Preset B counter with decimal 10 LOOP: MVICSTH Preset C counter with ecimal 71 Loop: ERC {Count down on C JNZ LOOP? {Test for C count of zero DcR B ‘Count down on B 4INZLOOPI Test for B count of zer0 RET SOLUTION This subroutine has two loops, one inside the other, The inner loop consists of DCR C and INZ LOOP2. This inner loop produces atime delay of DRC: 7x4 tus = 284 ps INZ LOOP2: 70x 10x 1s = 700 (jump) INZ LOOP2; 1x 7X 1ys=_7 — (nojump) 991 ws ‘When the C count drops to zero, the program falls through the JNZ LOOP2. The B counter is decremented, and the JNZ.LOOPI sends the program back to the MVI-C,47H. ‘Then we enter LOOP? for a second time. Because LOOP2 is inside LOOPI, LOOP? will be executed 10 times and ‘he overall ime delay will be approximately 10 ms. Here are the calculations forthe overall subroutine: MV BOAH: 17x 1us= —7ps MVI CATH: 107% 1ys= 70 10x 991 ps = 9,910 Wx4xIps= 40 9x 10x ips= 90 — Gump) 1X7X1ps= 7 (aojump) 110% 1ps = 10 10,134 ps ~ 10m ‘This SAP-2 subroutine has a byte length of DHMH 4Te I Sas IAD chapter 1 sara 1891 can be asembled and located at addresses FO20H 10 FOXCH. From now on, a CALL FO20H will rdoce atime delay of approximately 10s. By changing the fst instruction to MMVI BOA the B counter i preset with decimal 100 I this case, the inner loop is ected 100 times and the overaltime delay is approximately 100 ms. This 100-ns subroutine can be Tocated at addresses FU30H to FUBCH, EXAMPLE 11-18 Here is subroutine with thre loops nested one ini te cer. How much dine dlay does it produce? Label Mnemonic ‘Comment MVLAQOAH Preset A counter with decimal 10 LOOPI: —-MVIB,64H Preset B counter with decimal 100 LooP?; — MVICATH Preset C counter with ecimal 71 Loors: DCR Count dove C SNZLOOPS Test C for zero DCR B ;Count down B INZLOOP? Test B for zero DCR A ‘Count down A JNZLOOP! Test A for zero RET SOLUTION {LOOPS still takes approximately 1 ms to get through. LOOP? makes 100 pases through LOOPS, s0ittakes bout 100 ms to compete LOOP2. LOOPI makes 10 pases through LOOP2; therefore, it takes around | sto compete the oer sbeoutie ‘What do we have? A 1-ssubrotine. It will be located in FOMDH to FOS2H. To produce @ 1 time delsy, we would we a CALL FO4OH ‘By changing te intial instruction to MVL AGA LOOP! will make 100 passes through LOOP2, which ‘makes 100 passes through LOOP3. The resting subroutine ‘an be located at FOH to FO72H ad wil produce a time ely of 10, ‘Table I1-4 summaries the SAP-2 sme delays. With these subroutines, we can produce delay from 1 ms to 10s. 190 digit computer Btetroies ‘TABLE 11-4, SAP-2 SUBROUTINES abel Starting Address Delay Registers Used DiMs FoIH = ims DIOMS PMH Wms BC DIOS = ROH 10ms BC isec MoH Is AB, piosec —FAOH 1s AB, EXAMPLE 11-19 ‘The tfc lights on a main road show green for $0 s, yellow for 6 8, and red for 30 s. Bits 1, 2, and 3 of ort 4 are the conto inputs to peripheral equipment that ns thse trafic igs. Write a program tat produces ime delays of 50,6, and 305 for the wali igh ee Label Mnemonic Comment AGAIN: MVLAS2H Preset counter with ecimal 50 STASAVE Save accumaltor ‘contents MVIAGIH —Setbit OUT OM Turon green light LOOPGR: CALL DISEC Call sebrouine LDA SAVE Load curent A count DCR A {Decrement A count STASAVE Save reduced A count INZLOOPGR Test for z10 MVIAOSH ‘Preset counir with decimal 6 STA SAVE MVIAOMH —Setit? OUT OSH Turn yellow ight LOOPYE: CALL DISEC LDA SAVE DCR A STA SAVE NZ. LOOPYE MVLAIEH Preset counter with decimal 30 STA SAVE MVLAGSH —Setbit3 OUT ON Turn on sed ight LOOPRE: CALL DISEC LDA SAVE DORA STA SAVE INZ LOOPRE IMP AGAIN SAVE: DataLet's go through the green par of the program; the yellow and red are similar. The green stars with MVI A,32H, which loads decimal $0 into the accumulator. The STA SAVE will store this iil value in & memory location called SAVE. The MVIA,02H ses bit | inthe accumulator, then the OUT O4H transfers this high bit to port 4. Since this port controls the traffic lights, the gen light comes ‘The CALL DISEC produces time delay of 1s. The LDA SAVE loads the accumulator with decimal $0. The DER A decrements the count to decimal 49. The STA SAVE stores this decimal 49. Then the INZ LOOPGR takes the program back to the CALL DISEC for another Is delay. ‘The CALL DISEC is executed $0 times; therefore, the cen light is on for 0 s. Thea the program falls through the INZ LOOPGR to the MVI A,OGH. The yellow put of the program then begins and results in the yellow light being on for 6 5, Finally, the re part ofthe program is ‘ected and the ed light ison fe 30. The IMP AGAIN, repeats the whole process. In this way, the program is controling the timing of the green, yellow, and ved light, ‘EXAMPLE 11-20 Middle C ona piano has 2 frequency of 261.63 He. Bit S ‘of por 4 is connected to an amplifier which drives a loudspeaker. Write a program that sends mide C to the loudspeaker. SOLUTION To begin with, the period of middle Cis al 77 ream 3808 ‘What we are gong to doi send to port signal like Fig 1-9. This square wave is high for 1,911 js and low for 1,911 ws. The overall petod is 3,822 us, andthe frequency is 261.63 Hz. Because the signal is square eather than ‘sinusoidal, it will sound distorted but it willbe recognizable as mide C. ‘Heres a program that sends middle C othe loudspeaker. Label Mnemonic Comment LOOP: OUT OHH Send bit to speaker MVIC.S6H Preset counter with decimal 14 LOOP2: DCR {Count down INZ LOOP? Test count CMA ‘Reset bits Nor -Fine tuning Nop Fine tuning IMP LOOPI Go back fr next half cycle JUL aes Fig. 19 Genering middle C nt ‘The OUT O41 sends a bit (citer low oF high) 0 the loudspeaker. The MVI presets the counter to desimal 134, ‘Then comes LOOP2, the DCR and JNZ, which produces time delay of 1,866 us. The program then falls though tothe CMA, which complement all bits in th accumulator. ‘The two NOPs ada time delay of 8 ys. The IMP LOOPL then takes the program back. When the OUT O4H is executed, bit 5 (complemented) goes to the loudspeaker In this way the loudspeaker is driven into the opposite tate. ‘The execution time for both half eycles is 3,824 us, close enough to middle C. Here ae the calculation forthe time delay OUT OM: 1x 10x tus= 10ps MVIC86H: 1x7xIps= 7 Der C Mx 4x tase $36 INZ LOOP2 133 x 10x Lys = 1,330 INZ LOOP: 1X7XIps= | 7 CMa: Ix4xtnse 4 2 NoPs: 2x4x1us= 8 IMP LOOP: 1 10x I ys=_10 1912as This isthe half-eyle time. The period is 3,824 us. EXAMPLE 11-21 Serial data is sometimes cae a serial data stream because bits flow one after another. In Fig. 1-10 a serial data stream drives bit 7 of port 2 at arate of approximately 600 bits per second, Write a program hat inputs an S-bit ‘character in serial dat seam and stores it in memory Iocation 210041 SOLUTION Since approximately 600 bits are received each second, the petiod of each bit is 1 com 657 as ‘The idea will be t0 input 2 bit from port 2, rotate the sccumulator righ, wait approximately 1,600 us, then inpot another bit, rotate the accumulator righ, and so on, wnt al bits have been received Chapter 11 sara 191E LE cg ~ pa = |)" , Ka sp Y etn He ita progam et wl wt Land Menon Cormen MBO oa moo Be Micon ‘ex sma tel? om NUH pwr Avant tol? Gea Uptechncer at Mtn HovEA Saebaie® MIA‘ Bein ly of 140 9s DeLay, Both Ga ten A INZDELAY et Ara DRC Cau swe € ‘Neamt TeCeru fro Tot gular mat Ieee? ona STA ZION ne hance 192. digtat Computer Hiectronics The fiat instrtion clears the B register. The second instruction lads decimal 7 nto the C counter. The IN (2H brings in the data from port 2. The ANI mask isolates bit “Tbecause this isthe SERIAL 1N bit rom port 2. The ORA B does nothing the first time through because B is fll of (0s. The RAR moves the accumulator bts othe right. The (MOV B.A stores the accumulator conten in the B register [MV A.T3H presets the accumulator with decimal 115. ‘Then comes a delay lop, DCR A and INZ DELAY, thi takes approximacly 1,600 as to complet ‘The DCR C reduces the C count by 1, and the JNZ. BIT tests the C count for 2eo, The program jumps back tothe 1N 02H to get the nex bit rom the serial data steam. The ANIL mask isolates bit 7, which is then oned with the contents of the B register this combines the previous bit with the newly received bit. After another RAR, the 180 recived bits are stored in the B register. Then comes ‘another delay of approximately 1,600 ps The program contines to loop and each time a new bit {is input from the serial data team. After 7 bits have beenreceived, the program will fall through the NZ. BIT instruction, ‘The last four instructions do the following. The IN O2H ‘borings inthe eighth bit. The ANI isolates bit 7. The ORA B combines this new bit with the otber seven bits in the B register. At this point, all received bits are in the sceu- mulator. The STA 2100H then stores the byte in the ‘accumulstor at 21008. ‘A concrete example will help. Suppose the 8 bis being received are STH, the ASCII code for W. The LSB is received first, the MSB las. Here is how the contents of the B register appear after the execution of the ORA B: ‘A= 10000000 (First passthrough loop) ‘A= 11000000 (Second pass) A= 11100000 (Third pass) A= 01110000 (Fourth pass) A-= 1011 1000 Fifth pass) A= 0101 1100 (Sixthpass) A= 1010 1110 (Seventh pass) A=O10L0111 (Final contents) Incidentally, the ASCII code only requtes 7 bit; for this Teason, the eighth bit (A,) may be set to ze0 of used as a parity bi GLOSSARY ‘assembler A program that conversa source program into ‘8 machine-language program. comment Pervonalnotesinan assembly language program that are not assembled. They refresh the programmer's memory a a later date. conditional jump A jump that occurs only if certain conditions are satisfied direct addressing Addessing. in which the instrction contains the address ofthe data to be operated on, Flog A flip-flop that keeps track of a changing condition ‘during a computer run ‘hand assembling Translating. a source program into a ‘machine-Language program by hand rather than computer ‘handsheking Ineraction between a CPU anda peripheral ‘device that takes place during an VO operation. In SAP-2 it involves READY and ACKNOWLEDGE signals Jimmediate addressing Adkressng in which the data to be operated on isthe byte immediately following the op code ofthe instruction, implied addressing Addressing in which the location of the data is contained within the mnemonic. label A name given to an instruction in an ascembly- language program, To jump to this instruction, you can wse the label rather than the address. The assembler will work ‘ut the corect adress of the abel and will use this address {nthe machine-language program. ‘mask A byte used with an ANI instruction to blank out cena bits. register addressing Addressing in which the data is sored ina CPU register. relocate To move a program or subroutine to another part ‘of the memory. In doing this, the addresses of jump imaructions must be converted to new addresses subroutine A program stored in higher memory that can tbe used repeatedly as part of a main program, SELF-TESTING REVIEW Read each ofthe following and provide the missing words ‘Answers appear at the beginning ofthe next question, 4. The controler sequencer produces words of microinstruction, 2 (control) A fag is a____ that keeps track of changing condition during @ computer run. The sign flag is set when the accumolatar contents go negative. The flag is set when the accu- ‘mulator contents goto zero. 3. p-fop, zero) In coding the LDA adress and STA address instructions, the byte of the address is stored in lower memory, the byte in upper memory. 4. (lower, upper) The IMP instuction changes the Program sequence by jumping to snother part of the rogram. With the JM instruction, the jump is exe- cuted only ifthe sign fag is. With the NZ instruction, the jump is executed ony if the zero fag is 8. (cer, clear) Every subroutine must terminate with « instruction. This returns the program to ‘the instraction following the CALL. The CALL. instruction is unconditional; it sends the computer to the starting address of a 6. (RET, subrowtine) An assembler allows you to write Programs in mnemonic form. Then the assembler Chapter 11 sara 193.