High Performance Standard Cell Layout Synthesis for

Advanced Nanometer Technology Nodes

Design Challenges and Futures

Presenter: Hong-Yan Su (lionking)

Institute of Computer Science and Engineering

National Chiao Tung University

Electrical Design Automation Lab 2016/5/16

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 Outline

 Introduction to standard cell basics

 Cell layout synthesis flow
 Transistor placement
 Cell routing
 Transistor folding
 Experimental results
 Future works

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 Introduction of Standard Cells

 Standard cells (logic gate) : basic components of digital IC

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 Cell Layout Synthesis

NAND2 schematic NAND2 layout

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 Common Metrics for Standard Cells

Transition
Timing Area
Delay

Standard Cell

Power

Dynamic Leakage

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 Transistor Structure

VDD A1 ZN VDD A2 ZN

VDD

A1 A2
ZN
VDD A1 ZN A2 VDD
A1

A2
VSS

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 Cell Layout Structure

 Regular layout structure

Power rail
ps ps ps ps
P-MOS region
Poly
Poly/Pin Region

Routing
grid line N-MOS region

Ground rail
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 Design Challenges on Standard Cell Library

 A cell library contains several hundreds of standard cells

 One technology node will have several libraries for various purposes
 Determination on cell layout structure
 Complex and explosive number of design rules on advanced
technology nodes

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 Problem Formulation

A Practical Standard Cell

Synthesis Method
Transistor Cell routing Placement
placement • Metal 1 routing with folded
• Cell area resource transistors
• Routability • Metal 2 routing
• Other design resource
rules (diffusion,
poly, …)

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 Transistor Placement (1/3)

 Seek an ordering for transistors

VDD A1 ZN VDD A1 ZN A2 VDD

VDD OR

VDD A2 ZN ZN A1 VDD A2 ZN
A1 A2
ZN
A1
N1 ZN A1 N1
A2
ZN A1 N1 A2 VSS
VSS
N1 A2 VSS

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 Transistor Placement (2/3)

 Seek an ordering for transistors

VDD ZN VDD

VDD A1 ZN A2 VDD A1 A2
VDD
ZN N1 VSS
OR
A1 A2
ZN Minimum required
ZN A1 VDD A2 ZN wirelength: 3 units
A1
N1 +
A2 ZN VDD ZN

VSS ZN A1 N1 A2 VSS A1 A2

ZN N1 VSS

Minimum required
wirelength: 4 units

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 Transistor Placement (3/3)

 Consider a cell with n P-MOS (N-MOS)

 Each MOS has two choices: normal and flip

VDD A1 ZN OR ZN A1 VDD

 Possible ordering for P-MOS/N-MOS: (2n)!

 Ex 1: (XOR) 6 transistors  12! Possibilities ≈ 49 seconds (107 possibilities / sec)
 Ex 2: (Half adder) 8 transistors  16! Possibilities ≈ 24 years
 Need to consider the ordering of P-MOS and N-MOS
simultaneously
 A cell library will contain several hundreds cells

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 Cell Routing

 Complete routing with the considerations of

 DFM issues and complex design rules
 Including at least one routing grid of IO pin metal
 Cell performance

Situation 1 Situation 4

s d d
rl
w s
Situation 3
Situation 2
s
rl s
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w
 Cell Layout Synthesis on Transistor Folding (1/3)

 Break a large transistor into multiple parallel-connected

transistors
 Better performance  increase diffusion width
 Cell height is fixed  transistor folding

AND2X1 AND2X2
VDD VDD

I1 I2 I1 I2 I1 I2 O_neg
O_neg O O_neg O
I1 I1 I1 O_neg
N1 N1 N2
I2 I2 I2

VSS VSS

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 Cell Layout Synthesis on Transistor Folding (2/3)

 Different folding techniques

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Cell Layout Synthesis on Transistor Folding (3/3)

NAND2X2 NAND2X4

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 Experimental Results (1/3)
 Environments
 Implemented with C++ on a Linux platform
 Intel-i7 3.4GHz CPU and 8 GB RAM
 Testcases: 28nm commercial technology node
 INV, BUF
 X1, X2, X3, X4, X6, X8, X12, X16, X20, X24, X32
 AND2, NAND2, OR2, NOR2, AOI12, XOR2
 X1, X2, X3, X4, X6, X8, X12, X16
 Comparison: with commercial standard cell library
 All the cases can be synthesized within 1 second with identical area
 Compute average/minimum/maximum improvement ratio of all driving
strengths

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 Experimental Results (2/3)

 Routing resource improvement ratio

 AM1/AM2: area usage of metal 1/ metal 2

Average (%) Maximum (%) Minimum (%)

AM1 AM2 AM1 AM2 AM1 AM2
AND -2.15 5.28 1.77 11.81 -5.02 -1.93
NAND 0.67 4.89 5.33 15.11 -2.90 -2.02
OR 3.32 5.80 9.07 10.75 -0.84 -0.59
NOR 2.08 6.85 5.39 15.44 -5.61 -3.90
AOI -1.16 5.08 0.61 12.42 -6.84 -1.86
XOR 2.79 -5.23 4.24 -4.92 1.73 -5.70
BUF -2.35 9.23 2.08 15.87 -8.39 0.74
INV -10.04 10.79 -3.23 21.28 -15.81 -2.80

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 Experimental Results (3/3)

 Performance improvement ratio

 Similar performance: -1% ~ 1%

Leakage (%) Cap (%) Delay (%) Transition (%) Power (%)
Avg. Min Max Avg. Min Max Avg. Min Max Avg. Min Max Avg. Min Max
AND 0.00 0.0 0.0 -0.07 -1.0 1.5 0.06 -0.3 0.3 0.39 -0.5 1.4 -0.41 -0.9 0.9
NAND 0.04 0.0 0.2 0.28 -0.1 1.2 -0.44 -1.6 0.1 -0.66 -2.1 0.1 -0.05 -0.9 1.1
OR 0.00 0.0 0.0 0.62 -0.2 2.1 -0.38 -0.9 0.1 -1.02 -2.0 0.1 1.44 0.1 1.1
NOR 0.00 0.0 0.0 0.24 -0.1 0.7 -0.16 -0.7 0.5 -0.32 -1.3 0.8 -0.09 -0.8 0.6
AOI -0.03 -0.1 0.0 -0.43 -0.9 0.2 0.82 -0.2 2.8 1.09 -0.5 3.9 1.79 -0.4 6.6
XOR 0.00 0.0 0.0 1.32 1.0 1.7 0.51 0.0 0.8 -0.15 -1.3 0.6 1.35 1.1 1.8
BUF -0.12 -1.0 0.0 0.11 -0.9 1.1 0.02 -0.9 1.0 0.14 -2.0 1.7 -0.46 -1.2 0.7
INV 0.00 0.0 0.0 -1.77 -3.0 0.2 0.83 -0.8 1.7 0.85 -2.2 2.4 -1.70 -2.9 0.7

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 Future Works

 Routability estimation on transistor placement

 Smaller the better? No!
 DFM-related issues
 Multiple patterning
 Direct-self Assembly (DSA)
 New MOS structure
 FinFET / Gate all around / …
 Cell layout design aspect considering whole chip APR
 Smaller the better? No!

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