Harsh Khandelwal 17BIT0191 6th April 2019

Additional Learning

Name: Harsh Khandelwal

Reg_No:17BIT0191
Faculty: Prof Priya M

ICICICT2019 submission
 A Survey on Hamming Codes for Error Detection
Vraj Kishan Dugar, Manan Godha, Vishal Thakur, Harsh Khandelwal
School of Information Technology
VIT University,
Vellore, India
manangodha@gmail.com

Abstract—Information sent gets damaged many-a-times II. LITERATURE SURVEY during signal transmission. Therefore,
the signals received by the
receiver are erroneous and different to what the sender had 1. Error detection and correction by hamming code, Anil
 originally sent. This paper provides a comparison between 3 different types of error correcting codes, all based on
the basic Hamming code principle. Each code has its own efficiency in the way it functions, its power/area
consumption etc. In this paper we focus on the working of these 3 error correcting codes and try and find out the
more effective one.

Keywords— Hamming Code, error correction, error detection, bit error, parity check, 3D parity, Diagonal
hamming code, error control, comparison of error correction codes.

I. INTRODUCTION
The main purpose of achieving error detection is to add some extra overhead with the signal,
which helps the receiver to check whether the received data has been damaged during
transmission or not. There are various error detecting codes which are capable of detecting errors
of different sizes and have their own advantages and disadvantages based on their efficiency, bit
overhead and code rate they give. In this paper we look at three such codes based on the basic,
original Hamming code and compare their working and characteristics.
Hamming code is well known for its ability to correct singlebit errors. Hamming code is derived
from the principle of including ‘r’ redundancy bits into ‘n’ data bits such that 2r n + r +1.For 5
redundancy bits for a 11-bit data item and 6 redundancy bits for a 56-bit data stream. These
redundancy bits are to be added into the data bits at bit positions 2n (n = 0, 1, 2, 3…) with the
original data bits to provide a redundancy measure.
Error correction codes take data bits at the source and create redundant bits based on the
data bits which is then included in the data that is to be sent. Redundant bits are forwarded to the
receiver with the actual group of data bits at fixed positions and with fixed values. The receiver of
the data utilizes the redundant bits to check for errors that may have been generated during
sending or storing of the data. When the data is going to be stored, redundant bits are evaluated
and stored alongside the original bits and later, when the data is read from the memory it is
checked to check whether any errors in the transmission of the data have taken place between
the timespan of storage and retrieval.

Kumar Singh [1] Error detection:

Suppose the signal received has even parity bits. To decode he codeword, first check the parity
bits. Identify the parity bits as those bits present in the sequence at powers of 2. Find the value of
each parity bit in the following way :
• To find value of parity bit 1 : Check each digit one by one. If total no. of ones in these bits
is even, parity value is 0, else 1.
• To find value of parity bit 2 :Check 2 digits, skip 2 digits, check 2 digits and repeat. If total
no. of ones in the bits you check bits is even, parity value is 0, else 1.
• To find value of parity bit 4 : Check 4 digits, skip 4 digits, check 4 digits and repeat. If total
no. of ones in these bits is even, parity value is 1, else 0.
Match the values of the parity bits you get with the bits received in the signal. If they match, no
error exists, otherwise you have an error.

To find which bit has the error, add the location values of all those parity bits which did not match
with those calculated. Suppose if parity bits 2 and 8 were found to be incorrect, error exists at bit
2 + 8 = 10th bit.

Error Correction:
Now that we now which bit in the incoming message has an error, we correct it by changing its
value.

If the value is 0, change it to 1. If the value is 1, change it to 0.

Here, we get the corrected signal. So, we find that if the calculated values of parity bits in the
received signal don’t match with the values in the signal itself, an error exists at bit position equal
to the sum of positions of incorrect parity bits.

Example :

Figure 1.0 shows the received 14 bit value.

Figure 2.1 Grouping to obtain Hamming parities

Figure 1.1 shows the Parity bit calculation.

Here Incorrect Parity bits are 2,4 and 8. Therefore

error
th
position = 2 + 4 + 8 = 14 bit.

Figure 2.2 Hamming parity locations w.r.t grouped dat

Figure 1.2 shows the corrected signal.

2. Horizontal – Vertical Parity and Diagonal Hamming,[2] Raha, P., Vinodhini, M. and Murty, N
The HVPDH method requires an encoder along with a decoder. An encoder to produce the
parity bits and encode the signal with them. And a decoder to verify or change the received
 signal according to the parity bits. Three different parity bit sets need to be computed, vertical
parity, compare diagonal parity and horizontal parity bit sets.
Encoding:

Consider a 32-bit dataword. Arrange It into a N x M matrix. For 32-bits, let N=4 and M=8.

Figure 2.0 : The encoding matrix

Even parity is used. A bitwise XOR applied on each row gives that particular row’s horizontal
parity bit, and an XOR on the column gives that particular column’s parity bit. This way, two
parity bit sets of the 3 are produced.
To find the diagonal hamming code, the encoding/data matrix is grouped in a special way.

The number of groups that are so formed according to Figure 2.1, should be the same as the
number of rows in the encoding matrix. As you can see, there is a specific diagonal pattern in the
way data bits are grouped. First group : ( D16, D9, D2, D6, D13, D20, D27, D31). Second group : (
D8, D1, D5, D12, D19, D26, D30, D23). And so on.
The Hamming bit calculation is as shown in the figure below:

Figure 2.3 : Hamming parity bits calculation

For evaluating 32 bit data, we will get 8 vertical, 16 diagonal parity bits and 4 horizontal Hamming
parity bits, i.e. the three parity it sets have been calculated.

Decoding (at receiver end):

When the receiver receives the codeword, the decoder again calculates the parity bit sets for
error detection. Then the bit sets are merged again with the precious matrix, to again
compute both H and V parity sets.

Error Detection:
Observe the recalculated grouped diagonal Hamming parity bits. These bits help locate
errors in the dataword received.

Figure 2.4 : The received, decoded dataword

If single bit error exists in every diagonal parity bit group, that bit can be easily located
using the diagonal Hamming parity bits recalculated by the decoder. If the number of
error bits in every diagonal parity set is > 1, the error position then is found out with the
help of the vertical and horizontal parity bit sets, which are also calculated again by the
decoder when the new dataword is merged into the matrix representation again.

Syndrome bits are calculated in a simple manner: just apply bitwise XOR on the vertical and
horizontal parity bit sets received, with the vertical and horizontal parity bits calculated again.
If any syndrome bit is not 0, the bits of that row or column are considered to proceed with
error correction. Location of the error bits is found by comparing the above bits with the
Hamming parity results. Correction is performed by flipping the value of the error bit.

Cycle :

• Correct the error bit detected at the beginning.

• Data bit is again sent to decoder to recalculate parity bits
• Repeat process until all parities received are zero.

3. 3D Parity Check Code with Hamming Code, Tambatkar,

S., Menon, S., Sudarshan, V., Vinodhini, M. and Murty, N
[3]

This method is a unique hybrid of the error – correcting aptitudes of Hamming & 3D parity
check code, in a way so as to increase/better the reliability by compensating in the number
of parity bits.

The encoder converts data into a binary data stream and arranges it in a matrix to reduce
overhead, the size being m x n. These bits are encoded in 3D parity check code, calculating
three different sets of parity bits – Forward diagonal, vertical and horizontal. These parity bits
are once again ordered in vectors and these vectors are encoded in Hamming code by
 utilizing the HVHC encoder. Hamming parity bits are then calculated and parity bits are
stored along with data bits as vectors in memory.

Encoding:

3D parity bits are used as error correction codes for data bits stored in a matrix using the 3D
Parity Check encoder. 3D parity bits are evaluated using even parity technique, by using bitwise
XOR on corresponding bits. Again, if we take an example of a 32-bit data word, an effective way to
order them as a matrix getting a low number of parity check bits will be either a 4 x 8 or a 8 x 4
matrix. Going with the 4 x 8 again (Figure 3.0), we will get 4 horizontal parity bits ht[0] to ht[3]
(one for each row), 8 vertical parity bits vt[0] to vt[7] (one for each column) and 11 diagonal
forward parity bits as shown in Figure 3.1.

Figure 3.0: Input data bits arranged as a matrix

F gure 3.1: Input matrix with parity bits placed

To generate the code word systematically, these parity check bits are appended to the data bit
vector at the last index. The data bits and 3D parity check bits are then sent as input to the HVHC
encoder. The matrix is optimized if there are 8 parity bits in every vector

Figure 3.2: The systematic code-word

So, we get 3 vectors incorporating the 23 parity bits. Each of these vectors is encoded by the
HVHC encoder. Finally, data bits with Hamming code and this 3D parity check code are stored
in memory.
 Figure 3.3: The encoded vector

Decoding:

Encoded data bits are passed to HVHC decoder and the 3DPC decoder. HVHC decoder splits
out 3DPC bits and Hamming bits. These are arranged in vectors and syndrome vectors are
calculated for each of these vectors. These syndrome vectors are used to decode Hamming
code used for the 3DPC bits and likewise and error bit in each Hamming code row vector can
be rectified. This can be done by finding decimal equivalent of location of error bit.

If the error is a single bit, the bit that is inverted is shown by the syndrome. Therefore, error
detection goes up to 6 bits while 3 error bits in the 3DPC bits can be corrected. The HVHC
decoder can detect only two error bits in each row.

After detection, data bits and 3DPC bits are directed to the 3PC decoder. It splits the data bits
from the 3DPC bits that are used as guidelines. For data bits that are more likely to contain
errors, 3DPC bits are re-evaluated. These reference parity check bits are matched with these
bits to look for any similarities or dissimilarities either in the row-wise, column-wise or
diagonal parity bits. If a dissimilarity exists, the data bit referring to that diagonal/row/column
is flipped and hence corrected.

Figure 3.4: Detection of one-bit error in data bits

Figure 3.5: Detection of two-bit error in data bits

 Figure 3.6: Detection of three-bit error in data bits

III. EXPERIMENTAL RESULTS

From the graphs shown next, we can deduce that both the HVPDH method and the 3DPC
Hamming Code method are almost equally efficient. Both have similar overheads too. The HVPDH
method comes out to be the better one as far as the bit overhead is concerned and as that is a
major factor to look upon, the graphs clearly depict that among these 3 error-correction codes,
the HVPDH method is most efficient, especially when used in semiconductor memories.

Figure 4.1: Bit overhead and Code Rate for 3DPC Hamming

Code procedure

Figure 4.2: Bit overhead and Code Rate for HVPDH method
 Figure 4.3: Parity Bit Comparison

Figure 4.4: Code Rate % Comparison

Figure 4.5: Bit overhead % Comparison

IV. CONCLUSION
The first error correction code which we studied is the original Hamming Code. The next two
are more complex ones, but codes which have their roots sill based on Hamming codes. The
normal Hamming code can only correct single bit errors.

Compared to the previous method, The HVPDH Method is successful is detecting errors of up
to 8-bits and succeeds in correction of 1-bit, 2-bit and some 3,4,5 – bit errors.

The Hamming Code with 3D Parity Check Code method is capable of correcting any error
combination up to 3 bits. Thus, this method is one of the few ones capable of detecting errors
in both parity and data bits. It attains greater reliability but compensate in power/area
consumption.

REFERENCES

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correction for memories. 2017 International Conference on Computer Communication and Informatics (ICCCI).
[3] Tambatkar, S., Menon, S., Sudarshan, V., Vinodhini, M. and Murty, N. (2017). Error detection and correction in semiconductor
memories using 3D parity check code with hamming code. 2017 International Conference on Communication and Signal
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