F2 : Modeling Styles

1
 Modeling Styles

There are three modeling styles:

• Behavioral (slightly incorrect, Sequential is better)

• Data flow

• Structural

2
 One System –
Many VHDL Descriptions
Idea...

Behavioral Dataflow Structural

Description Description Description

Circuit 1 Circuit 2 Circuit 3

3
 Sequential (Behavioural) vs
Concurrent (Dataflow) Statements
• VHDL provides two different types of execution:
 sequential
 concurrent

• Different types of execution are useful for modeling of real

hardware
– Supports various levels of abstraction

• Sequential statements view hardware from a “programmer” approach

• Concurrent statements are order-independent and asynchronous.
They view hardware from a “hardware designers” point-of-view.

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 Sequential Style
XOR-gate
a Typically used to describe state machines
q
b and other complicated behaviour.

process(a,b)
begin
if (a/=b) then
q <= ‘1’;
else
q <= ‘0’;
end if;
end process;

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 Data flow Style
XOR-gate
a Typically used to describe atomic functions
q
b and other simple behaviour.

q <= a xor b;

Or in behavioral data flow style:

q <= '1' when a/=b else '0';

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 Structural Style
XOR-gate
a Typically used to describe hierarchy and
q
b connect smaller, more managable,
units together.

u1: inverter port map (a,ai);

ai t3 u2: inverter port map (b,bi);

a
q u3: and_gate port map (ai,b,t3);
b
bi t4 u4: and_gate port map (bi,a,t4);

u5: or_gate port map (t3,t4,q);

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Sequential & Dataflow style

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 Sequential Style
XOR-gate
a Typically used to describe state machines
q
b and other complicated behaviour.
Sensitivity list – when a signal
in the list changes value, the
Everything inside a process(a,b) process is executed
process is executed
begin
sequentially
if (a/=b) then
q <= ‘1’;
else
q <= ‘0’;
end if;
end process;

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 Sequential Style Syntax

[ process_label : ] PROCESS NO SIGNAL

DECLARATIONS!
[( sensitivity_list )]
CONSTANT
process_declarations DECLARATIONS

VARIABLE
BEGIN DECLARATIONS

LOCAL TYPE
process_statements DECLARATIONS

LOCAL FUNCTION
END PROCESS [ process_label ] ; DECLARATIONS

• Assignments are executed sequentially inside processes

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 Constant declaration

• Constants are used for storing data that doesn’t change

• Constants are available for the local region where it was specified
• The constant assignment takes place upon simulation initialization

CONSTANT constant_name : type_name :=value;

CONSTANT ADD : BIT_VECTOR(3 DOWNTO 0) := "0000";

CONSTANT freq : INTEGER := 100000000;

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 Variable declaration

• Variables are used for local storage of data

• Variables are generally not available to multiple components and
processes
• All variable assignments take place immediately

VARIABLE variable_name : type_name [:=value];

VARIABLE opcode : BIT_VECTOR(3 DOWNTO 0) := "0000";

VARIABLE freq : INTEGER;

 Variables are more convenient than signals for the

storage of (temporary) data inside processes
 Variables may be made global in VHDL’93 on (by
declaring them in the architecture
12 header)
 Signal Assignment

• A key difference between variables and signals is the assignment

delay

ARCHITECTURE signals OF test IS

SIGNAL a, b, c, out_1, out_2: BIT;
BEGIN
out_1 <= a NAND b;
out_2 <= out_1 XOR c;
END signals;

Time a b c out_1 out_2

Signals are parallel
0 0 1 1 1 0 constructs, that are
1 1 1 1 1 0 executed in delta
time if no delay is
1+d 1 1 1 0 0 specified.
1+2d 1 1 1 0 1
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 Variable Assignment
ARCHITECTURE variables OF test IS
VARIABLE a,b,c,out_3,out_4: BIT;
BEGIN
PROCESS (a, b, c)
BEGIN
out_3 := a NAND b;
out_4 := out_3 XOR c;
END PROCESS;
END example;

Time a b c out_3 out_4

Variables are
0 0 1 1 1 0 sequential
1 1 1 1 0 1 constructs, that are
executed
immediately within
the same delta.
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 Potential problem
• Avoid using shared variables
– Debugging potential asynchronous errors very difficult
– Concept likely to change in future VHDL standards

• Use it only when modelling two/multi-port memories.

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 Sequential Statements
– {Signal,variable} assignments
– Flow control
• if <condition> then <statements> [elsif <statements>]
else <statements>
end if;
• for <range> loop <statements> end loop;
• while <condition> loop <statements> end loop;
• case <condition> is
when <value> => <statements>
when <value> => <statements>
when others => <statements>
end case;
Implies State Machine.
– Wait on <signal> until <expression> for <time> ; Good for Testbenches.

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 IF- vs CASE-statement Syntax
Concatenation operator

if (a='1') then case (a&b) is

q <= '1'; when "00" =>
elsif (b='1') then q <= '0';
q <= '1'; when others =>
else q <= '1';
q <='0'; end case;
end if;

Case statements must be complete – all cases

must be covered.
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 Synthesis of an IF-statement
signal A, B, C, P1, P2, Z: BIT;
…
Process(P1,P2,A,B,C)
begin
if (P1 = '1') then
Z <= A;
elsif (P2 = '0') then
Z <= B;
else
Z <= C;
end if; The IF-statement implies a priority!
End process;

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 Synthesis of a case statement
type ENUM is (PICK_A, PICK_B, PICK_C, PICK_D);
signal VALUE: ENUM;
signal A, B, C, D, Z: BIT;
...
case VALUE is
when PICK_A => Z <= A;
when PICK_B => Z <= B;
when PICK_C => Z <= C;
when PICK_D => Z <= D;
end case;

The CASE statement implies no priority!

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 FOR- vs WHILE-statement Syntax

for i in 0 to 9 loop A for-loop is considered to be a

combinational circuit by some
q(i) <= a(i) and b(i);
synthesis-tools. Thus, it cannot have
end loop; a wait statement to be synthesised.

i:=0;
while (i<9) loop A While-loop is considered to be an
FSM by some synthesis-tools. Thus,
q <= a(i) and b(i); it needs a wait statement to be
WAIT ON clk UNTIL clk=‘1’; synthesised

end loop;
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 WAIT-statement Syntax
• The wait statement causes the suspension of a process statement or a procedure

• wait [sensitivity_clause] [condition_clause] [timeout_clause ] ;

– sensitivity_clause ::= on signal_name { , signal_name }

wait on CLOCK; -- Wait on a clock event

– condition_clause ::= until boolean_expression

wait until Clock = '1'; -- Wait until Clock becomes '1'

– timeout_clause ::= for time_expression

wait for 150 ns; -- Wait for a specific amount of

time (not synthesizable)

• Synthesizable combination:

wait on CLOCK until Clock='1'; -- Wait on the positive edge of clock

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 Sensitivity-lists vs Wait-on-statement

Summation: Summation: PROCESS

PROCESS( A, B, Cin) BEGIN
BEGIN
Sum <= A xor B xor Cin;
= Sum <= A xor B xor Cin;
WAIT ON A, B, Cin;
END PROCESS Summation; END PROCESS Summation;

if you put a sensitivity list in a process,

you can’t have a wait statement!

if you put a wait statement in a process,

you can’t have a sensitivity list!

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 Data flow Style
XOR-gate
a Typically used to describe atomic functions
q
b and other simple behaviour.

q <= a xor b;

Or in behavioral data flow style:

q <= '1' when a/=b else '0';

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 Concurrent Process Equivalents

•All concurrent statements correspond to a process equivalent

U0:q <= a xor b after 5 ns;
is a short hand notation for
U0:process
begin
q <= a xor b after 5 ns;
wait on a,b;
end process;
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 Concurrent (dataflow) versions of
if and case-statements

q<= b when sel='0' else a;

With sel select q <=

b when '0',
a when others;

CANNOT BE USED INSIDE A PROCESS!!!

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Structural Style

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 VHDL Hierarchy

Package

Generics Entity Ports

Architecture Architecture Architecture

(structural)

Concurrent Process
Concurrent
Statements
Statements 27 Sequential Statements
 VHDL Hierarchy

Universe (working directory)

Libraries
(sub-directories)

Packages, Entities, Architectures, and Configurations (compiled files) are

stored in a library called WORK.
To reuse these objects, refer to them via the library and the use command:
use work.all; use work.my_package.all;
library ieee; use ieee.std_logic_1164.all;
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etc.
 Structural Style
• Circuits can be described like a netlist
• Components can be customized
• Large, regular circuits can be created

x
y carry
enable
x
result

y
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 Structural Statements

• Structural VHDL describes the arrangement and interconnection of

components
– Behavioral descriptions, on the other hand, define responses to
signals

• Structural descriptions can show a more concrete relation between

code and physical hardware

• Structural descriptions show interconnects at any level of abstraction

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 Structural Statements

• The component instantiation is one of the building blocks of structural

descriptions

• The component instantiation process

requires component declarations and
component instantiation statements U0
• Component instantiation declares the
AND
interface of the components used in the
architecture

• At instantiation, only the interface is visible

– The internals of the component are hidden

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 Component Instantiation Syntax
• The instantiation statement maps the interface of the component to other
objects in the architecture
• The instantiation has 3 key parts
– Name
– Component type
– Port map
Component
Name Type

U0 : and_gate PORT MAP

(in1 => S1, in2 => S2, out1 => S3);

Port Map

S1 in1
out1 S3
S2 in2
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Named vs Positional port association

U0 : and_gate
U0 : and_gate
PORT MAP
PORT MAP
(in1 => S1,
(S1,S2,S3);
in2 => S2,
out1 => S3);

In named association the name

of the port points to the
signal that it is connected
to.
In positional association the
Signals are connected to ports
in the order the ports are
listed in the component
declaration.

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 Component Declaration

• The component declaration declares the interface of the component

to the architecture

ARCHITECTURE test OF test_entity

COMPONENT and_gate
PORT ( in1, in2 : IN BIT;
out1 : OUT BIT);
END COMPONENT;
... more statements ...

 Necessary if the component interface is not declared

elsewhere (in a package stored in a library)

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 Component Instantiation in VHDL’93

• In VHDL’93, entity-architecture pairs can be directly instantiated. This

is more compact, but does not allow the flexibility of configuration

ARCHITECTURE test_and_gate OF test IS

SIGNAL S1, S2, S3 : BIT;
BEGIN
U0 : entity work.and_gate(behave)
PORT MAP (in1 => S1,
in2 => S2,
out1 => S3);
END test_and_gate;

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 Legal signal-to-port connections

constant literals allowed in VHDL’93 :

U0:full_adder port map(a,b, '0',cout,sum);
VHDL’87:
zero<='0';
U0:full_adder port map(a,b,zero,cout,sum);

Outputs of a component can be left open:

U1:full_adder port map(a,b,cin,OPEN,sum);
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 Component libraries
• Component declarations may
be made inside packages and
stored in libraries
– Components do not have to
be declared in the
architecture body
PACKAGE my_components IS
COMPONENT and_gate
PORT ( in1, in2 : IN BIT;
out1 : OUT BIT);
END COMPONENT;
END my_components;
USE Work.my_components.ALL;
ARCHITECTURE test OF test_entity
SIGNAL S1, S2, S3 : BIT;
BEGIN
Gate1 : and_gate
PORT MAP (S1, S2, S3);
END test;
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 Generics

• Generics allow the component to be customized upon

instantiation

• Generic parameters pass information from the entity to the

architecture

• Common uses of generics

1) Alter range of subtypes (Common)
2) Change size of arrays (Common)
3) Customize timing – Technology modelling (Uncommon)

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 Alter range of subtypes
Entity adder is
Generic(N:integer);
…
End adder;
Architecture behave of adder is
signal sum:integer range 0 to 2**N-1;
…
Begin
…
End behave;

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 Change size of arrays/vectors
Entity adder is
Generic(N:integer);
Port(A,B:IN bit_vector(N-1 downto 0);
Q:OUT bit_vector(N-1 downto 0));
End adder;
Architecture behave of adder is
…
Begin
…
End behave;

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 Technology Modeling

• Another use of generics is to alter the timing of a certain component

• It is possible to indicate a generic timing delay and then specify the
exact delay at instantiation

COMPONENT inv IS
GENERIC (tplh, tphl : TIME);
PORT ( in1 : IN BIT;
out1 : OUT BIT);
END COMPONENT;

 The example above declares the interface to a

component named inv
 The propagation time for high-to-low and low-to- high
transitions can be specified
41 later
 Gate Level Modeling
Entity inv is
Generic (tplh, tphl : time);
Port ( in1 : IN BIT;
out1 : OUT BIT);
End inv;
Architecture behave of inv is
Begin
process(in1) -- this process is only executed if in1 changes value
begin
if (in1=’0’) then
out1<=’1’ after tplh;
else
out1<=’0’ after tphl;
end if;
end process;
End behave;
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 Structural Statements
• The GENERIC MAP is similar to the PORT MAP in that it maps specific
values to generic parameters declared in the component.
• You can use named or positional association, but you cannot mix them.

PACKAGE my_components IS
COMPONENT inv
GENERIC ( tplh, tphl : time);
PORT ( in1 : IN BIT; out1 : OUT BIT);
END COMPONENT;
END my_components;

USE Work.my_components.ALL;
ARCHITECTURE test OF test_inv
SIGNAL S1, S3 : BIT;
BEGIN
Gate1 : my_components.inv
GENERIC MAP (2 ns, 3 ns)
PORT MAP (S1, S3);
END test;
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 Configuration Specification

• The configuration specification allows the designer to choose the

entity for each component

• What is the need for configuration?

– VHDL supports design partitioning
– Various pieces of the design work may be parceled out
– When the architecture is developed, only the component interface
may be available
– There is a need to pull the pieces of the design back together

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 Configuration Specification (ctd.)

• Configuration must account for

– Entity name can be different than the component name
– Entity declaration may have more ports than the component
declaration
– Ports on the entity declaration may have different names than the
component declaration
• Configuration is clearly necessary in these cases to map the correct
entity to the component

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 Configuration Syntax (ctd.)

• The configuration specification must indicate two pieces of

information
– Selected components
– Entity to bind with

• The basic syntax of the configuration specification is

FOR component_specification USE binding_indication;

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 Component Specification Syntax
• The component specification can be of several forms
– Single component
FOR A1 : and_gate USE binding_indication;

– Multiple components
FOR A1, A2 : and_gate USE binding_indication;

– All components
FOR ALL : and_gate USE binding_indication;
All components of this type are effected
– Other components
FOR OTHERS : and_gate USE binding_indication;
Components that have not yet been specified are effected

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 Binding Indication Syntax

• The binding indication identifies the entity to be used for the

component
• The name of the architecture can also be identified
• Configuration may also be made in a separate configuration
declaration

Entity name

FOR A1 : and_gate USE ENTITY Work.and_2_input (behavioral);

Architecture name
 Binding indication may also include a PORT
MAP and GENERIC MAP to adapt the entity to
the component 48
 Example: BAD Configuration
Specification
• This example shows the use of the configuration specification to
allow an entity fit a component with a different interface
• NB! This is considered BAD CODING STYLE!!!

ENTITY JKFF IS
PORT (clk, preset, clear, J, K : IN BIT;
Q, Q_bar : OUT BIT);
END JKFF;

PACKAGE Global_signals IS
SIGNAL clk, preset, clear : BIT;
END Global_signals;

USE Work.Global_signals;

ENTITY config_test IS
END config_test;
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 Example: BAD Configuration
Specification
• The configuration statement maps the JKFF entity to the global signals and
the ports of the component

ARCHITECTURE structural OF config_test IS

SIGNAL S1, S2, S3, S4: BIT;
COMPONENT FF
PORT(J, K: IN BIT; Q, Q_bar: OUT BIT);
END COMPONENT FF;

FOR U0 : FF USE ENTITY Work.JKFF

PORT MAP (clk => Global_signals.CLK,
preset => Global_signals.preset,
clear => Global_signals.clear,
J => J, K => K,
Q => Q, Q_bar => Q_bar);

BEGIN
U0 : FF PORT MAP (S1, S2, S3, S4);
END structural; 50
 Configuration Specification
• If the binding is not specified in the architecture, it can be done from the
outside, in a configuration specification.
• This is useful to use in testbenches, replacing test vector generators,
components and monitors without touching the architecture.
ARCHITECTURE structural OF config_test IS
SIGNAL S1, S2, S3, S4: BIT;
COMPONENT FF
PORT(J, K: IN BIT; Q, Q_bar: OUT BIT);
END COMPONENT FF;

BEGIN
U0 : FF PORT MAP (S1, S2, S3, S4); Name of entity
END structural;
Configuration config_FF of config_test is
for structural Name of architecture
FOR U0 : FF USE ENTITY Work.JKFF(structural)
PORT MAP (clk => Global_signals.CLK,
preset => Global_signals.preset,
clear => Global_signals.clear,
J => J, K => K,
Q => Q, Q_bar => Q_bar);
end for;
end for;
End config; 51
 Generate Statement

Structural for-loops: The GENERATE statement

• Some structures in digital hardware are repetitive in nature (RAM,

ROM, registers, adders, multipliers,…)

• VHDL provides the GENERATE statement to automatically create

regular hardware

• Any VHDL concurrent statement may be included in a GENERATE

statement, including another GENERATE statement

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 Generate Statement Syntax

• All objects created are similar

• The GENERATE parameter must be discrete and is undefined

outside the GENERATE statement

• Loop can not be terminated early

name : FOR N IN 1 TO 8 GENERATE

concurrent-statements
END GENERATE name;

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 IF-Generate statement

• Allows for conditional creation of components

• Can not use ELSE or ELSIF branches with the

IF-scheme

name : IF (boolean expression) GENERATE

concurrent-statements
END GENERATE name;

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 Example: Array of AND-gates
USE work.my_gates.all;
ARCHITECTURE structural OF and_bit_vector IS
BEGIN
G1 : FOR i IN N-1 DOWNTO 0 GENERATE
and_array : and_gate
GENERIC MAP (2 ns, 3 ns)
PORT MAP (i1=>a(i),i2=>b(i),q=>q(i));
END GENERATE G1;
END structural;

a(N-1:0)
b(N-1:0)

q(N-1:0) 55
Example: Array of several gate-types

ARCHITECTURE structural OF mixed_vector IS

BEGIN
G1 : FOR i IN N-1 DOWNTO 0 GENERATE

G2 : IF (i > N-4) GENERATE

or1 : or_gate
GENERIC MAP (3 ns, 3 ns)
PORT MAP (a(i), b(i), c(i));
END GENERATE G2;

G3 : IF (i <= N-4) GENERATE

and_array : and_gate
GENERIC MAP (2 ns, 3 ns)
PORT MAP (a(i),b(i),c(i));
END GENERATE G3;

END GENERATE G1;

END structural;

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 Example: Array with indexing
ARCHITECTURE structural OF parity_calculator IS
BEGIN
G1 : FOR i IN N-1 DOWNTO 0 GENERATE

G2 : IF (i > 0) AND (i < N-1) GENERATE

xor_1 : xor_gate GENERIC MAP (3 ns, 3 ns)
PORT MAP (c(i-1), b(i), c(i));
END GENERATE G2;

G3 : IF (i = 0) GENERATE
xor_1 : xor_gate GENERIC MAP (3 ns, 3 ns)
PORT MAP (even_odd,b(i),c(i));
END GENERATE G3;

G4 : IF (i = N-1) GENERATE
xor_1 : xor_gate GENERIC MAP (3 ns, 3 ns)
PORT MAP (c(i-1),b(i),qout);
END GENERATE G4;

END GENERATE G1;

END structural;
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 Constructing Adders: Two’s
Complement Algebra
A + {B,B}

Cout Cin
FA FA FA

Two’s complement: -B=B+1 => B= -B -1

A+B A+B
Cin=0 A+B+0 A+B+0=A-B-1
Cin=1 A+B+1 A+B+1=A-B-1+1
A+B+Cin A-B-Cin
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Testing structural components

59
 Testing a Circuit

Test Pattern Circuit Response

Generator Under Test Analyzer

Test Equipment
• Pulse and Function generators
• Oscilloscope
• Logic Analyzers
• Computers
• Specialized Zigs +
Test Engineer

60
 Testing a structural component
• When you test a structural component, it is
important that you jog every wire at least once
• For a structural adder, the outputs and the carry
must switch/change value.
– If we add -1 with 0, and then add +1 using cin, then the
value will ripple through the carry chain and turn sum to
0. All wires in the architecture changes value.

61
 Assert Statement

• The ASSERT statement is used for displaying text when certain

conditions are NOT met
• ASSERT statement classifies the text message in four
categories
– Note -- relays information about conditions to the user
– Warning -- alerts the user to conditions that are not expected, but
not fatal
– Error -- relays conditions that will cause the model to work
incorrectly
– Failure -- alerts the user to conditions that are catastrophic

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 Assert Syntax

• Syntax of the ASSERT statement

ASSERT condition
REPORT "violation statement"
SEVERITY level;

 The ASSERT statement will trigger when the

condition is false
 The violation statement must be enclosed in quotes

ASSERT (NOT((j='1') AND (k='1')))

REPORT "Set and Reset are both 1"
SEVERITY ERROR;

63
 Assert Example
• Assume type state is (good, reset);
• We specify the Normal operating conditions – assert triggers on
abnormal operating conditions

PROCEDURE display_state (current_state : IN state) IS

BEGIN
ASSERT (current_state = reset)
REPORT "Status of State: good"
SEVERITY NOTE;
ASSERT (current_state /= reset)
REPORT "Status of State: reset"
SEVERITY WARNING;
END display_state;

 ASSERT statements may have some

implementation defined action associated with
the various SEVERITY levels
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 Testing the adder
library ieee;
use ieee.std_logic_1164.all;
Use ieee.std_logic_signed.all;
ARCHITECTURE test_adder OF test IS
constant N:integer:=8;
signal A,B,Sum:std_logic_vector(N-1 downto 0);
signal cin,cout:std_logic;
BEGIN
U0 : entity work.adder(structure)
generic map(width=>N)
port map(A,B,cin,SUM,cout);
A<="11111111";
B<="00000000";
A list of values can be
cin<='0', '1' after 20 ns;
given to an input
assert (Sum=A+B+cin)
report "outputs do not match the given input"
severity note;
END test_adder;

65