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TXW102 R29 PC Architecture PDF
TXW102 R29 PC Architecture PDF
PC Architecture (TXW102)
Topic 1:
Introduction to Computer Hardware Architecture
© 2008 Lenovo
Objectives:
Computer Hardware Architecture
© 2008 Lenovo
© 2008 Lenovo
Notebooks
Notebooks are optimized for traveling and for mobile users who need easy access to data.
Notebooks can be categorized as ultraportable (around three pounds), full function (up to seven
pounds), or a desktop alternative (desktop features in a larger notebook design). Lenovo uses the
brand names IdeaPad or ThinkPad for its notebook systems.
The tablet PC is another kind of PC. Tablet PCs are based on a Microsoft specification for ink-
enabled touch screen computers (using Windows XP Tablet PC Edition or Windows Vista). The
tablet PC comes in two form factors: slate (which has no keyboard attached because the tablet can
be connected to a docking station) and convertible (includes integrated keyboard). Lenovo markets
the ThinkPad X61 and X200 Tablet, which are convertibles.
Desktops
Desktops are for users who work in one place and need access to data on the desktop or through a
network. Lenovo uses the brand names IdeaCentre or ThinkCentre for its desktop systems.
Common desktop mechanical designs include the following:
• Ultra Small (0 slot x 2 bay or 1 slot x 2 bay)
• Small (2 slot x 3 bay or 4 slot x 3 bay)
• Desktop (4 slot x 4 bay or 3 slot x 3 bay)
• Tower (4 slot x 5 bay)
Workstations
A workstation, such as a Unix workstation, RISC workstation, or engineering workstation, is a high-
end desktop or deskside microcomputer designed for technical applications. Workstations are intended
primarily to be used by one person at a time, although they can usually also be accessed remotely by
other users when necessary.
Workstations usually offer higher performance than is normally seen on a personal computer,
especially with respect to graphics, processing power, memory capacity, and multitasking ability.
Workstations are often optimized for displaying and manipulating complex data such as 3D
mechanical design, engineering simulation results, and mathematical plots. Consoles usually consist of
a high resolution display, a keyboard, and a mouse at minimum, but often support multiple displays
and may often utilize a server level processor. For design and advanced visualization tasks,
specialized input hardware such as graphics tablets or a SpaceBall may be used.
Lenovo markets the ThinkStation family of workstations.
Servers
Servers are computers that provide services to other computers, called clients. Servers are in secure
areas because so many users are dependent on their function. They include file servers, print servers,
terminal servers, Web servers, e-mail servers, database servers, and computation servers.
Server designs include
• Tower, which rests on the floor
• Rack-based, which must be installed in a rack
• Server blades, which have server circuitry on a single board which slides into an enclosure with
other blades.
Note: Servers for racks vary in height by a U measurement (a U is 1.75-inch height). 1U servers are
popular for Web sites because for Web pages it is better to spread the load across multiple servers
(horizontal scalability) rather than to increase the processing power of a centralized server (vertical
scalability).
Lenovo markets the ThinkServer family of servers.
Netbook Notebook
Device for Internet Multi-purpose PC
Purpose built for Internet use Performance for multi-tasking,
Web usage: learn, play, content creation, intense workloads,
Usage
communicate, and view and Internet
No optical drive Entertainment, productivity, and
rich Web
Compact form factor Range of form factors
Size
(7-10" screen) (> 10" screen)
Price ~$250 to $450 $450 and above
Intel
Brands
© 2008 Lenovo
Manageability
Compatibility
Performance
Total Cost of
Capital Cost
Application
Application
Ownership
Vendors
Security
Network
Ease of
Impact
Offline
Traditional PC 3 3 3 3 Several
Server-based
Computing 3 3 z z 3 3 Citrix, MS
HP,
Blade PC 3 3 3 z 3 3 ClearCube
Virtual Desktops
From Servers 3 3 z z 3 3 z VMWare
Application Softricity,
Streaming z z z 3 z 3 z AppStream
Ardence,
OS Streaming z z z 3 3 3 Wyse
Source: Gartner (March 2007)
3 - Decided advantage
z - Neutral
- Major weakness
© 2008 Lenovo
Architectural Choices
There are many choices of computing because different requirements drive different architectures.
PC OS RDP PC OS OS OS
Architecture Spectrums
The PC provides the greatest degree of flexibility for diversity of applications, types of
management, and configuration options. As other architectures such as hosted virtual machines,
blade PCs, streaming, server-based computing, and Web-based computing are considered, security
and lower total cost of ownership are increased at the expense of a more rigid design with little
flexibility.
Ethernet
• PC Blade is in a
rack in secure,
Direct Connection
centralized location User Port PC Blade
(C/Port) The PC Blade is each user's actual
• Lenovo resells computer: a configurable, Intel-based PC
Blade that delivers full functionality to the
ClearCube-branded desktop.
PC Blades and
management Cage
The ClearCube Cage is
software a centralized chassis that
houses up to eight PC Blades.
© 2008 Lenovo
PC Blades
PC Blades separate the guts of the PC from the physical desktop, putting processing power in data
centers and computer rooms. Employees then have only a monitor, keyboard and mouse on their
desks, along with a client appliance that is linked back to a blade server. PC blades offer a range of
benefits, including streamlined management and tighter security since all the hardware is
centralized. PC Blade configurations provide a dedicated blade to each user or a pool of blades that
can be dynamically allocated. In addition, spare blades can be used to provide hot backup to avoid
system outages.
PC Blade Advantages
• Centralized asset management – PC Blade hardware is centralized for easy access and asset
management.
• Mission critical applications – Blade infrastructure has high levels of redundancy; users can be
swapped to a functioning blade very quickly in case of hardware or software failure
• Reduced support costs – Hardware or software upgrades can be managed centrally in a fraction
of the time it would take to upgrade large numbers of dispersed PCs.
• Multiple locations – There is potential to support multiple locations with PC Blades by remotely
switching a user to a spare standby blade in the event of hardware failure (saving the cost of an
urgent engineer visit or keeping support staff on-site).
• Reduced costs for new users – It is lower cost to install and configure a new user with a PC
Blade than a desktop.
• Easy relocation – There are no significant costs when users move work location within a building.
• Improved security – The physical asset and intellectual property on the disk are centralized, e.g., it
is easier to steal a hard disk from a desktop than a PC Blade.
• Reduced user down time – Spare PC Blades can be configured to provide hot backup in case of
hardware failure.
• Improved appearance – In front office environments, the client’s user port has no moving parts,
generates no noise, produces little heat, and requires less space.
• Remote access – Users can access their own PC environment from multiple desks in the building
or from other remote locations with blade infrastructure installed
PC Blade Disadvantages
• Higher acquisition cost – Purchase price of PC Blade and its infrastructure is higher than a stand
alone PC.
• No wireless mobility – Mobile users or users who need to work away from their desks are not
supported.
• Lagging technology – PC Blade processors and technology may be six to 12 months behind
desktop technology.
• Unsuitable for power graphics users.
• New infrastructure – Significant change to current PC deployment, maintenance, and support
(skills, tools and processes).
• More difficult to plan and manage upgrades when customer has a mix of PC Blades and traditional
desktops.
• Lack of local CD and DVD drives except USB devices which open security risks and asset control
issues.
• User resistance for advanced/experienced PC users to losing access to 'their' PC.
• Extra cost for redundancy – Extra cost for closet spare (with cooling) to enable redundancy.
• Technology lock in – Little option to cascade or sell blades to other users or customers.
• PC Blade
- PC Blade is located with other
PC Blades in a rack in centralized
location
- Intel processor, memory, disk, and
graphics on PC Blade
© 2008 Lenovo
ClearCube
ClearCube is a company that has offered PC Blades since 1997 and dominates the PC Blade
market. Lenovo resells ClearCube-branded PC Blades and management software.
See www.clearcube.com for more information.
Think Idea
The Ultimate Business Tool Engineered for People
Visit lenovo.com for more information on the IdeaPad notebooks and IdeaCentre desktops.
ThinkVantage Technologies
ThinkVantage Technologies are a select group of offerings from
Lenovo designed to address emerging customer needs. Adding
value to open industry standards, ThinkVantage Technologies help
customers manage the cost of deploying end-user systems,
implement new technologies such as wireless computing, and help
ensure that these technologies can be implemented securely. While
many of these offerings currently exist, some are being significantly
enhanced and all of them have now been consolidated into a single
family of offerings.
Visit lenovo.com/thinkvantage for more information.
© 2008 Lenovo
- Dynamic Operating Environment Consolidates support for multiple operating systems and languages into
(DOE) one Super Image
- Hardware Independent Imaging Provides hardware-independent images that will support multiple system
Technology (HIIT) types via system-specific drivers and applications pulled from the PC’s
service partition (supported on ThinkPad and ThinkCentre systems only)
System Migration Assistant (SMA) An easy-to-use migration tool that automates the migration of both
settings and data through a menu system and advanced scripting
capability
Remote Deployment Manager Network-based imaging and system support tool that distributes images
(RDM)* and updates system settings (includes PowerQuest Drive Image Pro Lite)
Connect Access Connections Manages all wireless and wired connectivity settings and allows easy
switching between them
Protect Client Security Solution (CSS) Security software that provides authentication of end-user identity,
encryption of data, and simplified password management
Active Protection System (APS) Prevents some hard-drive crashes on most new ThinkPad models by
temporarily stopping the hard drive when a fall or similar event is
detected; provides up to four times greater impact protection than
systems without this feature
Support Productivity Center Provides one-button access to self-help support tools and information
about a user’s system
Rescue and Recovery A help desk behind the button that allows a system to recover itself from
OS corruption and even hard drive failures, fills the gap between
traditional backup and restore programs and re-imaging, allows remote
system recovery with or without user intervention, and automates the
deployment of critical patches, even if a system will not boot.
System Information Center (SIC) An electronic inventory management solution that tracks client PC
hardware and software assets, provides ThinkVantage Technology usage
information, and reports and measures security compliance
Software Delivery Center (SDC) Automates delivery of application software updates to PCs without end-
user intervention or disruption
Asset ID A unique asset-tagging technology that allows data, events, actions, and
responses to be read by or become interactive with other programs
System Update Accesses, downloads, and installs the latest updates for Think systems
IBM Director Agent An advanced CIM/WMI-based agent for systems and asset management
that allows extensive upward integration into other enterprise
management tools and databases
IBM Director A powerful systems management program with extensions targeted for
improved system setup, remote manageability, and event monitoring of
clients and servers
Dispose Secure Data Disposal An automated program that allows multiple levels of disk cleansing, which
ensures systems are properly safeguarded during disposal; meets the
DOD Level 5 and German standards for safe disposal
ImageUltra Builder $100 per unit • Deployed once per system versus typical cloned
image management and loading process
System Migration Assistant $70 per unit deployed • Deployed once per system versus manual
processes
Remote Deployment Manager $90 per system • Deployed once per system versus manual
processes
Access Connections $50 per wireless PC • Annual savings and only in notebook systems
• Assumes two help desk call per user per year
Rescue and Recovery $180 per occurrence • Used for one incident in 13% of installed systems
• Average support time savings of 183 minutes
Secure Data Disposal $45 per PC • Once per PC per life cycle
* Potential savings are based on typical customer environments. Some figures represent costs that customers may redirect from
labor-intensive areas to other areas of their business. Other figures are based on cost avoidance of competitive solutions
purchased separately. All figures are calculated using the TVT and Wireless Calculators and data from Gartner Research and
customers. Actual savings are not guaranteed and will vary by customer.
PC Architecture:
Computer Layers
• Layered structure
User
- This structure allows for
compatibility. Applications
EEPROM BIOS
© 2008 Lenovo
Computer Layers
A computer consists of several layers that each have interfaces to communicate to the layer next
to it. A layered structure allows for compatibility; for example, the same shrink wrapped
operating system can work on millions of PCs from different vendors because it interfaces with
industry standard BIOS calls. The disadvantage to the layers is that each layer can slow
performance. So to increase performance a layer could be bypassed; for example, an application
could be written directly to the BIOS and device driver of a specific computer which would gain
performance, but would only work on that unique computer.
Some of the different computer layers shown in the diagram above are explained below.
• Applications are the software programs with which a user typically interacts, such as those used
for word processing (Microsoft Word), Web browsing (Internet Explorer), sending e-mail
(Lotus Notes), and using spreadsheets (Microsoft Excel).
• Middleware is software that provides an additional level of abstraction to applications. The idea
behind the middleware is to hide the complexity of implementing code that is not strictly
related to the business objectives that the application is supposed to be written for. Writing
applications against the basic APIs that the OS is able to expose is sometimes very time
consuming and it might take a while before a programmer starts to get into the “business
modules” of the application being developed. Using middleware is like actually talking to a
cleverer interface compared to the interface provided by the OS. Middleware has to implement
all the “boring stuff,” so that developers can concentrate on the business logic. Examples
include IBM DB2, Oracle, Microsoft SQL Server, Lotus Domino, Microsoft Internet
Information Server, IBM WebSphere, and BEA WebLogic.
•The operating system is a set of programs that provides an environment in which applications
can run, allowing them easily to take advantage of the processor and I/O devices, such as disks
or adapters. Examples include Windows 2000, Windows XP, Vista, Red Hat Linux, and AIX
5L.
•The Basic Input/Output System (BIOS) is a set of program instructions that activates system
functions independently of hardware design (the layer between the physical hardware and the
operating system) and allows for software compatibility. BIOS is typically located in flash
memory (EEPROM) on the systemboard. When a PC is started, the BIOS runs a power-on self-
test (POST). It then tests the system and prepares the computer for operation by searching for
other BIOSes on the plug-in boards and setting up pointers (interrupt vectors) in memory to
access those routines. It then loads the operating system and passes control to it. The BIOS
accepts requests from the drivers as well as the application programs. The BIOS supports plug-
and-play and power management. Although there are several BIOS vendors, there are few
differences among their products.
Note: To preclude the problem of performing OS, BIOS, or driver updates before the OS or
network drivers are loaded, a Preboot Execution Environment (PXE) allows the system to boot
off the network. At boot, a PXE agent executes, and the PC gets an IP address from a DHCP
server and then uses the BOOTP protocol to look for a PXE server. The PXE client is firmware
implemented in BIOS (if LAN hardware is on the systemboard) or as a boot PROM (if LAN
adapter). Programs, including those in the PXE environment, require system configuration and
diagnostic information. A Systems Management BIOS (SMBIOS) is a chip that makes the
necessary information available via BIOS calls that are available through the OS and in the
preboot environment.
•Firmware is usually the layer of software that is between the device driver and adapter. It
typically is on a EEPROM of an adapter card and can be upgraded with new releases. Firmware
is similar to BIOS.
•Device Drivers are a type of software (which may be embedded in firmware) that controls or
emulates devices attached to the computer such as a printer, scanner, hard disk, monitor, or
mouse. Device drivers are typically loaded low into the memory of PCs at boot time. A device
driver expands an operating system's ability to work with peripherals and controls the software
routines that make peripherals work (a network card, a disk, printer). These routines may be part
of another program (many applications include device drivers for printers), or they may be
separate programs. Basic drivers come with the operating system, and drivers are normally
installed for each peripheral added.
Application Program
6.
Operating System
4.
5. BIOS 3.
7.
Video
Circuitry
Keyboard
Cable
Keyboard Port
Hardware
1. 2. Hardware
PC Architecture:
Subsystems
© 2008 Lenovo
Subsystems
Subsystems in a PC communicate to each other via buses. Buses adhere to a particular
architecture (set of rules) to allow compatibility with the numerous subsystems that adhere to
the same architecture.
Most PCs are associated with the term Wintel, which refers to Microsoft Windows and Intel
chip technologies. PCIe stands for PCI Express.
The processor is the central component of a PC. Intel and AMD are the main processor vendors
used in PCs.
Data in the processor, caches, memory, buses, disk controller, and graphics controller is stored
electrically; so when electrical power is shut down, this data is lost. Data on the disk is stored
magnetically, so the data is saved even when electrical power is removed.
PC Architecture:
Controllers
© 2008 Lenovo
Controllers
All major subsystems have controllers that define how data will be obtained and stored.
Sometimes a controller is a single chip with the data stored in separate physical circuitry. For
example, a memory controller controls memory, but the data is stored in different physical chips
called DIMMs.
Sometimes a single physical chip contains multiple controllers. For example, the I/O Controller
Hub (ICH) is a single physical chip which houses the PCI Express controller, PCI controller,
Serial ATA controller, EIDE controller, USB controller, and other controllers.
Controllers are normally included in the chipset of the computer.
PC Architecture:
Buses
Control I/O
Controller Data
Address
© 2008 Lenovo
Buses
If two subsystems are on a bus, such as in the diagram with processor and memory, a data
transfer first involves sending the address on the address bus. Next, data is sent on the data bus.
If multiple subsystems exist on a bus, a control bus is needed in addition to the address and data
bus. The control bus is used to signal which subsystem will control the bus for the next transfer.
Address Bus
An address bus determines how much memory the processor or any subsystem can directly
address. For example, a 32-bit address bus means 2 to the power of 32 or 4 billion unique
numbers to address 4 GB of memory.
0 0 0 0 . . . 0 0 0 0 0
0 0 0 0 . . . 0 0 0 0 1
0 0 0 0 . . . 0 0 0 1 0
0 0 0 0 . . . 0 0 1 0 0
0 0 0 0 . . . 0 0 1 0 1
Memory Addressing Similar to Car Odometer
Before data is read or written by a processor, the address of that data is sent first. This address is
sent on a separate set of physical wires called the address bus. The data is then sent on a
different set of physical wires called the data bus.
A processor is designed to use a certain maximum quantity of address lines. The amount of
physical memory that a processor can address is determined by this quantity. The number of
unique numbers that can be made by a base two number system (0s and 1s) with the quantity of
address digits determines the maximum addressable memory of a processor. Software can limit
this maximum addressability, for example, DOS sets the processor to use 20 address lines as
DOS only addresses 1 MB of memory.
Following are some processors and their addressability:
Address lines Addressable memory Examples
24 16 MB 486SLC
32 4 GB 486DX2
36 64 GB Pentium 4, Xeon
40 1 TB EM64T physical memory
44 18 TB Itanium
48 256 TB EM64T virtual memory
64 18 EX IA-64 64-bit flat addressing
Sometimes operating systems limit addressability, so that the operating system can not utilize
all the available physical memory.
PC Architecture:
Bus Speeds
Processor +
L1/L2 Cache
System bus
400 to 1066 MHz
PCI Express MCH or Memory
x16 slot GMCH
PCI Express slots Host Bridge Memory bus
PCIe 2.5 GHz
200 to 800 MHz
PCIe 2.5 GHz
PCI 2.0 33 MHz I/O
Controller Direct Media Interface (DMI)
Hub 100 MHz
PCI 2.0 slots (ICH)
4 SATA
disks
Firmware USB
Super I/O Hub
Low Pin Count (LPC) Interface 33 MHz
Bus Speeds
Each bus in a PC has a speed (measured in megahertz) and a data transfer rate.
The bus between the processor and the memory controller was originally called the frontside
bus; the processor had a separate bus to its integrated L2 cache called the backside bus and a
separate bus outside the processor to the memory controller called the frontside bus. The
frontside bus and the backside bus were two different buses. With the introduction of the
Pentium 4 and follow-on processors, the frontside bus was named system bus, although both
terms were still used interchangeably. The change of the name to system bus was due to the fact
that the L2 cache was not isolated off a separate, independent bus to the degree that it was for
earlier processors, such as the Pentium II and Pentium III.
The memory bus is clocked at 200 to 400 MHz, but most memory today is double data rate
(DDR); this means data is transferred on both the rising and falling edge which doubles the
throughput from the base clock speed.
The system bus and the memory bus can be either synchronous or asynchronous, depending on
the memory controller of the chipset. Some memory controllers only support synchronous
system and memory bus speeds; some support either synchronous or asynchronous speeds. An
example of a memory controller that supports synchronous system and memory bus speeds is a
400 MHz system bus with a 200 MHz memory bus with PC2-3200 DDR2 memory (there is an
even multiple of 200 among 200 MHz and 400 MHz). An asynchronous example is a 400 MHz
system bus with a 266 MHz memory bus with PC2-4200 533MHz DDR2 memory. DDR3 uses
a 400 to 800 MHz memory bus.
In 1996 and 1997, the PC industry standardized the 66 MHz system bus. Migration to a 100
MHz system bus occurred in 1998, then to a 133 MHz bus in 2000. The Pentium 4 introduced a
400 MHz system bus in late 2000, although it was really 100 MHz × 4 to yield 400 MHz. Later,
Pentium 4 processors utilized an 800 MHz system bus (200 MHz × 4) followed by a 1066 MHz
system bus (266 MHz × 4). The Core 2 Quad uses a 1066 MHz system bus (266 MHz × 4)
PC Architecture:
Cache
Processor +
1. L1 Cache
2. L2 Cache
PCI Express
x16 slot
MCH or 3. Memory
PCI Express slots
GMCH
Host Bridge
PCI
Express
I/O
Controller
4. Hub
SCSI (ICH)
EIDE Disks
5.
Firmware
Hub
© 2008 Lenovo
Cache
Cache is a storage place (buffer or bucket) that exists between two subsystems in order for data
to be accessed more quickly to increase performance. Performance is increased because the
cache subsystem usually has faster access technology and does not have to cross an additional
bus. Cache is typically used for reads, but it is increasingly being used for writes as well.
For example, getting information to the processor from the disk involves up to five cache
locations:
1. L1 cache in the processor (memory cache)
2. L2 cache (memory cache)
3. Software disk cache (in main memory)
4. Hardware disk cache (some disks may only use an FIFO buffer)
5. Disk buffer
For reads, one subsystem will usually request more data than what is immediately needed, and
that excess data is stored in the cache(s). During the next read, the cache(s) is searched for the
requested data, and if it is found, a read to the subsystem beyond the cache is not necessary.
Industry Standards:
Restriction of Hazardous Substances (RoHS) Directive
FIN FIN
IS
NO NO
RUS
ES ES
SE
LV LV
LT LT
BY BY
IE IE
GB GB
POL POL
NL GER
NL GER
UK
BE BE
LU LU CZ CZ
SK SK
AT AT
FR
FR CH CH HU HUROMROM
HR HR
BA BA
YU YU BUL BUL
IT
MK MK
PT
PT SP SP AL
TUR
GR GR
CY
MAL
© 2008 Lenovo
A similar directive from the European Union is the Waste Electrical and Electronic Equipment (WEEE)
Directive. WEEE encourages and sets criteria for the collection, treatment, recycling and recovery of
electrical and electronic waste. WEEE requires producers to ensure that equipment they put on the
market in the EU after August 13, 2005 is marked with the crossed-out wheeled bin symbol, the
producer’s name, and indication that the equipment was put on the market after August 13, 2005.
Lenovo PC products comply with the WEEE Directive requirements.
WEEE-Compliant Symbol
Industry Standards:
ENERGY STAR 4.0 and 80 PLUS
© 2008 Lenovo
The 80% efficient power supply is a principal requirement of ENERGY STAR 4.0 and a major new
innovation. When a power supply converts AC power from the wall to the various DC voltages that the
computer needs, there is always a loss of power. The power loss varies with how busy the computer is.
An 80% efficient power supply is guaranteed to lose less than 20% of the AC power at 20%, 50% and
100% loads. Currently, power supplies for desktop computers range from approximately 65% to 75%
efficiency. A system can have an 80 PLUS power supply but not be ENERGY STAR 4.0-compliant. 80
PLUS power supplies are always auto-sensing.
See www.energystar.gov/ and www.80plus.org for more information.
2007 Limits
If hardware configuration consists of… Category Idle Sleep Standby
(watt) (watt) (watt)
• Multi-core processor or Then C 95W
Multi-processor and
• Graphics controller with > 128 MB
discrete memory and 4W 2W
• Two of the following three:
• ≥ 2 GB system memory 4.7W with 2.7W with
• TV Tuner and/or video capture WOL WOL
• ≥ 2 disks Else
Industry Standards:
EPEAT
© 2008 Lenovo
Industry Standards:
Climate Savers
© 2008 Lenovo
Climate Savers
The goal of the environmental effort is to save energy and reduce greenhouse gas emissions by
setting new targets for energy-efficient computers and components, and promoting the adoption of
energy-efficient computers and power management tools globally.
The typical desktop PC wastes more than half of the power it draws from a power outlet. The
majority of this unused energy is wasted as heat and never reaches the processor, memory, disks, or
other components. As a result, offices, homes, and data centers have increased demands on air
conditioning which in turn increases energy requirements and associated costs.
The Challenge starts with the 2007 ENERGY STAR requirements for desktops, laptops and
workstations (including monitors), and gradually increases the efficiency requirements over the next
three years, as follows:
• From July 2007 through June 2008, PCs must meet the Energy Star requirements. This means 80
percent minimum efficiency for the power supply unit (PSU) at 20 percent, 50 percent, and 100
percent of rated output, a power factor of at least 0.9 at 100 percent of rated output, and meeting
the maximum power requirements in standby, sleep, and idle modes.
• From July 2008 through June 2009 the standard increases to 85 percent minimum efficiency for
the PSU at 50 percent of rated output (and 82 percent minimum efficiency at 20 percent and 100
percent of rated output).
• From July 2009 through June 2010, the standard increases to 88 percent minimum efficiency for
the PSU at 50 percent of rated output (and 85 percent minimum efficiency at 20 percent and 100
percent of rated output).
See www.climatesaverscomputing.org for more information.
Industry Standards:
GREENGUARD
© 2008 Lenovo
GREENGUARD
The GREENGUARD Environmental Institute is an industry-independent, non-profit organization
that oversees the GREENGUARD Certification Program. As an ANSI Accredited Standards
Developer, GEI establishes acceptable indoor air standards for indoor products, environments, and
buildings. GEI’s mission is to improve public health and quality of life through programs that
improve indoor air. A GEI Advisory Board consisting of independent volunteers, who are
renowned experts in the areas of indoor air quality, public and environmental health, building
design and construction, and public policy, provides guidance and leadership to GEI.
The GREENGUARD Certification Program is an industry independent, third-party testing program
for low-emitting products and materials.
Select Lenovo products are GREENGUARD certified.
See www.greenguard.org for more information.
Industry Standards:
Intel High Definition Audio (Intel HD Audio)
Dolby
Game audio Digital
Intel HD Audio
supports multiple
audio streams at
Chat audio the same time.
© 2008 Lenovo
Support for Intel HD Audio is found in the ICH6 and later I/O Controller Hubs. The ICH6 and
ICH7 integrate both AC ’97 and Intel HD Audio to facilitate transition from the older AC ’97;
however, only AC ’97 or Intel HD Audio can be used at one time. (Either requires an additional
external codec chip; when Intel HD Audio was announced, the older AC ’97 chips cost less
money.) The ICH6/ICH7 Intel HD Audio digital link shares pins with the AC ’97 link. For
input, the ICH6/ICH7 adds support from an array of microphones that can be used for enhanced
communication capabilities and improved speech recognition. The ICH8 only supports HD
Audio (not AC '97).
Intel HD Audio has support for a multi-channel audio stream, a 32-bit sample depth, and a
sample rate up to 192 kHz.
Intel HD Audio delivers significant improvements over previous-generation integrated audio
and sound cards. Intel HD Audio hardware is capable of delivering the support and sound
quality for up to eight channels at 192 kHz/32-bit quality, while the AC ‘97 specification can
only support six channels at 48 kHz/20-bit quality. In addition, by providing dedicated system
bandwidth for critical audio functions, Intel HD Audio is architected to prevent the occasional
glitches or pops that other audio solutions can have.
Dolby Laboratories selected Intel HD Audio to bring Dolby-quality surround sound
technologies to the PC, as part of the PC Logo Program that Dolby recently announced. The
combination of these technologies marks an important milestone in delivering quality digital
audio to consumers. Intel HD Audio will be able to support all the Dolby technologies,
including the latest Dolby Pro Logic IIx, which makes it possible to enjoy older stereo content
in 7.1-channel surround sound.
Standardized
Register Interface
(UAA)
Modem codec
OS Audio codec
ICH6
Audio Intel HD
Telephony codec
driver UAA Audio Intel HD
Intel HD
Modem bus driver registers Audio Link HDMI codec
Audio
driver
Controller
AC ’97
AC ’97 registers Audio Dock
AC ’97 AC Link Dock codec
drivers codec
Cntrl
Only Intel HD Audio or AC ’97 Modem
may be used at one time codec
Intel HD Audio also allows users to play back two different audio tracks, such as a CD and a
DVD simultaneously, which can not be done using current audio solutions. Intel HD Audio
features multi-streaming capabilities that give users the ability to send two or more different
audio streams to different places at the same time, from the same PC.
Microsoft has chosen Intel HD Audio as the main architecture for their new Unified Audio
Architecture (UAA), which provides one driver that will support all Intel HD Audio controllers
and codecs. While the Microsoft driver is expected to support basic Intel HD Audio functions,
codec vendors are expected to differentiate their solutions by offering enhanced Intel HD audio
solutions.
Intel HD Audio also enables enhanced voice capture through the use of array microphones,
giving users more accurate speech input. While other audio implementations have limited
support for simple array microphones, Intel HD Audio supports larger array microphones. By
increasing the size of the array microphone, users get incredibly clean input through better noise
cancellation and beam forming. This produces higher-quality input to voice recognition, Voice
over IP (VoIP), and other voice-driven activities.
Intel HD Audio also provides improvements that support better jack retasking. The computer
can sense when a device is plugged into an audio jack, determine what kind of device it is, and
change the port function if the device has been plugged into the wrong port. For example, if a
microphone is plugged into a speaker jack, the computer will recognize the error and can
change the jack to function as a microphone jack. This is an important step in getting audio to a
point where it “just works.” (Users won’t need to worry about getting the right device plugged
into the right audio jack.)
The Intel HD Audio controller supports up to three codecs (such as an audio codec or modem
codec). With three Serial Data In (SDI) and one Serial Data Out (SDO) signals, concurrent
codec transactions on multiple codecs are made possible.
The SDO connects to all codecs and provides a bandwidth of 48 Mb/s. Each of the three SDIs
are typically connected to a codec and have a bandwidth of 24 Mb/s. In addition, the controller
has eight non-dedicated, multipurpose DMA engines (4 input, and 4 output). This allows
potential for full utilization of DMA engines for better performance than the dedicated function
DMA engines found in AC ’97. In addition, dynamic allocation of the DMA engines allows
link bandwidth to be managed effectively and enables the support of simultaneous independent
streams. This capability enables new exciting usage models (e.g., listening to music while
playing a multi-player game on the Internet).
Surround Surround
Center
Left Right Dolby Digital
DTS
DVD Video
CD
Subwoofer
With Intel HD Audio, a DVD movie with 5.1 audio can be sent
to a surround sound system in the living room, while you
listen to digital music and surf the Web on the PC.
Industry Standards:
Intel Active Management Technology (Intel AMT)
© 2008 Lenovo
Intel AMT requires the computer system to have an Intel AMT-enabled chipset, network hardware and
software, as well as connection with a power source and a corporate network connection. With regard to
notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based
VPN or when connecting wirelessly, on battery power, sleeping, hibernating, or powered off. For more
information, see www.intel.com/technology/manage/iamt.
Dash 1.0 Dash 1.1 AMT 2.6/3.0 AMT 4.0 AMT 5.0
Boot Control X X X X X
Hardware Inventory X X X X X
Software Inventory X X X X X
Hardware Alerting X X X X X
IDE Redirect X X X X
Agent Presence X X X
Remote Configuration X X X
Audit Logs X X
Measured AMT X X
Enhanced System Defense X X
KVM X
Benchmarks
© 2008 Lenovo
Benchmarks
The following is a short list of benchmarks and the systems they measure.
• Overall performance:
– SYSmark 2004 SE - SYSmark includes office productivity and Internet content creation
benchmark tests. The two scores are combined and given a weighted average to produce an
overall performance rating. Both SYSmark tests derive scores by using real-world
applications to run a preset script of user-driven workloads and usage models developed by
application experts.
The SYSmark 2004 SE Internet Content Creation test is organized as scenarios that are
designed to simulate an Internet content creator’s day. This benchmark incorporates such
applications as Adobe Photoshop 7.01, Discreet 3ds max 5.0, and Macromedia
Dreamweaver MX.
The SYSmark 2004 SE Office Productivity test follows ICC’s blueprint by mimicking the
usage patterns of today’s desktop and mobile business users, including the concurrent
execution of multiple programs. Applications such as Adobe Acrobat 5.0.5, McAfee
VirusScan 7.0, and the Microsoft Office suite are used. Each SYSmark test measures the
response time of the application to user input. Both scores are combined using a geometric
mean to get an overall score.
Security Issues:
Trusted Platform Module (TPM)
© 2008 Lenovo
The logon user name and TPM When files and folders are encrypted, they can
password are stored in the chip be decrypted only by the person who has the
TPM chip. authentication data the TPM chip requires.
User ID abcdefg
Password Disk
*******
Encrypted Files
Smart-card
reader
TPM
chip
Multiple login IDs and passwords cause users to be On-chip, protected storage of secrets reduces user
careless; store secrets without protecting them; use burden; enables secure single sign-on; ensures strong
weak protections protections
Storage of IDs and passwords in easily copied files; Secure storage of IDs and passwords; multiple log-in
use of one set of secrets for access to all systems secrets secured by the TPM
Altered settings allow inappropriate access to valued Validated settings ensure system integrity and prevent
networks and sensitive data inappropriate access
Untrustworthy systems result in unreliable and Trustworthy systems result in reliable and trustworthy
untrustworthy practices practice; reduce support expenses
Security chip in Winbond WPCT200 SafeKeeper Trusted Platform Module (in select
ThinkCentre desktops)
Security chip integrated in some desktop-based Intel I/O Controller Hub 10 (ICH10D
and ICH10DO) in select ThinkCentre desktops
Security chip was soldered to systemboard and was a module from Atmel
mainly used in select ThinkPad notebooks
Summary:
Computer Hardware Architecture
Lenovo ThinkPad
© 2008 Lenovo
Computer Measurements
• Bit (b): on charge or off charge (0 or 1)
• Byte (B): eight bits (a character/number represented by a byte)
• Kilobyte (2^10): one thousand bytes (KB): 1,024
• Megabyte (2^20): one million bytes (MB): 1,048,576
• Gigabyte (2^30): one billion bytes (GB): 1,073,741,824
• Terabyte (2^40): one trillion bytes (TB): 1,099,511,627,776
• Petabyte (2^50): one quadrillion bytes (PB): 1,125,899,906,842,624
• Exabyte (2^60): 1,000 petabytes (EB): 1,152,921,504,606,846,976
• Zettabyte (2^70): 1,000 exabytes (ZB): 1,180,591,620,717,411,303,424
• Yottabyte (2^80): 1,000 zettabytes (YB): 1,208,925,819,614,629,174,706,176
• Millisecond: one thousandth of a second (ms): 1/1,000
• Microsecond: one millionth of a second (us): 1/1,000,000
• Nanosecond: one billionth of a second (ns): 1/1,000,000,000
• Picosecond: one trillionth of a second (ps): 1/1,000,000,000,000
• Megahertz: millions of cycles per second (MHz)
• Gigahertz: billions of cycles per second (GHz); 1GHz=1,000 MHz
Speeds
bps = bits per second
KB/s = kilobytes per second
Mb/s = megabits per second
MB/s = megabytes per second
Gb/s = gigabits per second
GB/s = gigabytes per second
• Some magazines (like PC Magazine) measure in megabytes (1,024 bytes squared, or 1,048,576).
For rough conversion, subtract five million from every hundred million bytes. For example, 720
million bytes is 687 megabytes.
• Speeds for connectivity are normally measured in bits (bits per second). Speeds for transfers
within a PC (like across PC buses) are normally measured in bytes (bytes per second).
• For each 20 degrees Celsius-increase in operating temperature, electronic component life drops in
half.
• A billion bits is equivalent to 62,500 double-spaced typewriter pages--enough paper to stack 21
feet high.
• 0.15 micron is 1/600 the width of one human hair.
• Logic circuits are used to process information; memory circuits store information.
Network Speeds
Average Required
Applications
Throughput
Video
Audio
Other
Broadband Types
Business
Business DSL Fractional T1 Wired MAN Wireless MAN
cable
Speed
2-5 Mb/s 144 Kb/s-6 Mb/s 384 Kb/s-1.5 Mb/s 10 Mb/s-1 Gb/s 256 Kb/s-100 Mb/s
(download/
384-768 Kb/s 144 Kb/s-1.5 Mb/s symmetrical symmetrical symmetrical
upload)
Review Quiz
Objective 1
1. What type of system would most likely market its systems management support, chipset, and
graphics performance?
a. Notebook
b. Desktop
c. PC Blade
d. Netbook
2. What type of system has the user's processor, memory, disk, and graphics removed from a
user's desk and stored in a rack in a secure, centralized location?
a. Notebook
b. Desktop
c. PC Blade
d. Server
3. The ThinkPad brand name is associated with what type of computer system?
a. PDA
b. Notebook
c. Desktop
d. Server
4. Rescue and Recovery, Access Connections, and Productivity Center are from what strategic
Lenovo offering?
a. ThinkVantage Technologies
b. ThinkVision monitors
c. ImageUltra Builder
d. System Migration Assistant
Objective 2
6. What circuitry controls the methods, manner, and speed in which a subsystem is accessed?
a. Controller
b. Keyboard
c. VLSI logic
d. Device driver
Objective 3
8. What is the name of the architecture for implementing audio, modem, and communications
functionality after AC ’97?
a. Intel High Definition Audio (Intel HD Audio)
b. I/O Controller Hub 6 (ICH6)
c. Unified Audio Architecture (UAA)
d. Dolby Digital
10. What industry standard addresses the restriction of hazardous substances in electrical and
electronic equipment?
a. EPEAT
b. ENERGY STAR
c. Restriction of Hazardous Substances (RoHS)
d. 80 PLUS
11. What industry standard promotes technologies that improve the efficiency of a computer's
power delivery and reduce the energy consumed in an inactive state?
a. Climate Savers
b. 80 PLUS
c. Intel HD Audio
d. RoHS
Objective 4
12. What security solution is supported on all Lenovo ThinkPad and ThinkCentre systems that
protects vital security information and guards against unauthorized user access to data?
Answer Key
1. B
2. C
3. B
4. A
5. B
6. A
7. C
8. A
9. A
10. C
11. A
12. A
PC Architecture (TXW102)
Topic 2:
Processor Architecture
© 2008 Lenovo
Objectives:
Processor Architecture
© 2008 Lenovo
Processor Features:
Introduction
© 2008 Lenovo
Processors
The following points outline fundamental information applicable to all processors.
• The processor (or microprocessor) is the central processing unit (CPU) of the computer. The
processor is the place where most of the control and computing functions occur. All operating
system and application program instructions are executed here. Most information passes through
the processor, whether a keyboard stroke, data from a disk, or information from a communication
network.
• The processor needs data and instructions for each processing operation that it performs. Data
and instructions are loaded from memory into data-storage locations, known as registers, in the
processor. Registers are also used to store the data that results from each processing operation
until the data is transferred to memory.
• The processor is packaged as an integrated circuit that contains the following:
– one or more arithmetic logic units (ALUs or execution units)
– a floating point unit (math coprocessor)
– Level 1 and Level 2 cache
– registers for holding instructions, data, and control circuitry
• Clock rate is a fundamental characteristic of all microprocessors. Clock rate is the rate at
which a processor perform operations, and this rate is measured in billions of cycles per
second or gigahertz (GHz). The maximum clock rate of a microprocessor is determined by
how fast the internal logic of the chip can be switched. As silicon fabrication processes are
improved, the integrated devices on chips become smaller and can be switched faster. Thus,
the clock speed can be increased.
• Processors support specific operating systems. For example, the Itanium family of processors
used in some high-end servers require an operating system that is specifically written for
them. Itanium processors will not run Windows XP which is for IA-32 (32-bit) processors.
Processors used in notebooks and desktops today are 32-bit/64-bit processors (also known as
IA-32 or Intel Architecture 32-bit) and typically run Windows-based operating systems such
as Windows XP. Linux also runs on 32-bit/64-bit processors. IA-32 processors with support
for Intel 64 Technology can run 64-bit software.
Processor Definitions
Backside bus – In the P6 micro-architecture, which had a dual independent bus, the backside bus
was the 64-bit or 256-bit bus to L2 cache. The backside bus was independent of the frontside bus to
the memory controller.
Branch – A point that represents a potential change in the flow of a program. A branch can either
be unconditional, meaning that it always changes program flow, or it can be conditional, meaning
that it may or may not change program flow depending on other factors.
Branch Prediction – The Branch Processing Unit improves processor performance by trying to
predict the address of branches and preload the address in a buffer (Branch Target Buffer) should
the branch occur. The Branch Target Buffer can be dynamic (based on previous history of
branches) or static (based on a hardwired set of rules). The Branch Processing Unit has an 80% hit
rate (predicts branch and address accurately). When an instruction leads to a branch, the Branch
Target Buffer remembers the instruction and the address of the branch taken. The branch
instruction is a program statement that has the potential of altering the execution flow of the
program such as a "Jump" or "Loop" instruction. Branch instructions change the sequence of
instruction execution, which causes pipelines and buffers to clear and reload with new instructions
(which slows performance). Programs normally have 20% of instructions as branch instructions.
Branch mispredictions happen more frequently with “branchy” productivity applications than with
streaming multimedia applications.
Branch Processing Unit – Dedicated circuitry is used to prevent delays caused by branching
instructions. The branch processing unit removes branch instructions from the queue, calculates the
target address, and sends the new target address to the cache for prefetching. It tries to keep
instructions flowing into the queue even when program logic dictates a change in the base address
used for prefetching instructions from cache.
Capacitor – An electric circuit element used to store charge temporarily, consisting in general of
two metallic plates separated and insulated from each other by a dielectric. Higher wattage
processors and chipsets require more capacitors on a systemboard.
Complex Instruction Set Computing (CISC) – Processors that are microcode based with
instructions that vary in length. Intel x86 processors are CISC processors.
Core micro-architecture – A micro-architecture introduced on the Core 2 Duo and Core 2 Extreme
processors in July 2006. Key features of Intel Core micro-architecture include Intel Wide Dynamic
Execution, Intel Intelligent Power Capability, Intel Advanced Smart Cache, Intel Smart Memory
Access, and Intel Advanced Digital Media Boost.
Decode – To examine the format of an instruction to determine what type of operation and which
operands it specifies.
Dependency – A condition that prevents one instruction from executing until another instruction
has been finished. A true dependency occurs when one instruction's output becomes another
instruction's input. False dependencies may be introduced by out-of-order execution but can be
worked around through register renaming.
Die area – A small die size means lower costs since more chips can be manufactured from a single
wafer.
Dual-core – A processor that combines two independent processors and their caches onto a single
silicon chip.
Dual Independent Bus (DIB) – Two independent buses make up the dual independent bus (DIB)
architecture: the “L2 cache bus” (backside bus) and the processor to main memory “system bus”
(frontside bus). Both buses can be used simultaneously and in parallel, rather than in a singular
sequential manner as in a single bus system.
Execution unit – A portion of the processor dedicated to performing a particular type of operation
such as arithmetic functions, memory loads and stores, or branch processing.
Fetch – To retrieve code from cache or memory in preparation for decoding.
Field Effect Transistor (FET) – A transistor in which the output current is controlled by a variable
electric field. Higher wattage processors and chipsets require more FETs on a systemboard.
Capacitor Toroid Field effect transistor
Floating point – A system for representing any number as a single digit with a decimal fraction
along with a multiplier (an exponent of two or some other base number); for example, 1.23 x 10 to
the 4th.
Frontside bus – In the P6 micro-architecture, which had a dual independent bus, the frontside bus
was the 64-bit data bus from the processor core to the memory controller. The frontside bus was
also called the system bus and was independent of the backside bus to L2 cache.
High-K – In 2007, Intel released processors with 45 nm technology which changed out critical
materials in a redesign. It moved from polysilicon dioxide gate to metal gate technology. The metal
gate sits on an insulator made of hafnium-based high-k. The high-k refers to a material with a high
dielectric constant (k) (as compared to polysilicon dioxide) used in the manufacturing process.
IA-32 Execution Layer – In January 2004, Intel launched its IA-32 Execution Layer software,
which will let companies run 32-bit applications on servers using 64-bit Itanium 2 processors. Intel
first built 32-bit compatibility into the Itanium 2 processor itself; switching it to the software layer
will let 32-bit applications run more efficiently on Itanium 2 and eliminate the need to further
develop 32-bit compatibility at the chip level. IA-32 Execution Layer runs with Windows
applications. Intel plans to work with Red Hat, Inc. to support 32-bit Linux applications.
Instruction – The fundamental unit of a program; one or more bytes of information that direct the
processor to perform a particular task.
Integer instruction versus floating point instruction – Text processing is considered an integer
instruction since text (and numbers) are both bit patterns (00110101).
Load/Store Unit – The Load/Store unit loads and stores instructions between registers and caches. It
accesses memory using dedicated instructions that load a value into a register from cache or store a
value from a register into cache. This eliminates the need for a separate address computation for
each memory access. The Load/Store unit originally started as a RISC feature.
Micro-architecture – Micro-architecture refers to the implementation of processor architecture in
silicon. Within a family of processors, the micro-architecture is often enhanced over time to deliver
improvements in performance and capability while maintaining compatibility to the architecture.
Micro-op – Micro-op is Intel's term for RISC-like internal operations into which x86 instructions
are translated to improve processing efficiency. Micro-ops are easier to dispatch and execute in
parallel than their complex x86 instruction counterparts, which maintains compatibility with the
existing x86 instruction set but overcomes their historical limitations.
Microcode – A series of micro-instructions (sets of control bits) used to coordinate the execution of
complex instructions by breaking them into smaller segments.
Micron – A measurement of width; one micron is one millionth of a meter; human hair is between
50 and 100 microns; 0.18 microns is about 600 times thinner than the width of a hair. Decreasing
the micron width produces the following benefits:
• Increase MHz/GHz because the chip is smaller
• Reduces production costs because each wafer hold more chips
• Cuts power consumption because the chips operate at lower voltage
• Allows more transistors
• Generates less heat
Nanometer (nm) – Processors and other semiconductors are manufactured on a circular silicon
wafer. Over time, the process technology for the wafer size is reduced. It is measured in
nanometers. In 2006, the common size was down to 65 nanometers. This width is the smallest
circuit wire diameter.
NetBurst micro-architecture – NetBurst micro-architecture is micro-architecture first introduced in
the Pentium 4 in 2000 and used in subsequent Intel processors (such as Intel Pentium D and Xeon).
NetBurst includes hyper-pipelined technology, rapid execution engine, and execution trace cache.
Nonblocking – Allowing subsequent operations to proceed even if the first cannot be satisfied
completely. The term describes caches that can continue processing even after a miss, which occurs
when requested data is not present in the cache.
Out-of-order execution (OoO) – Allows multiple objects in different execution units to be
processed out of sequence. The instructions can then be recombined into the proper program flow
before being written to off chip memory. The area on the chip and the power to run the control
logic for OoO increase both chip cost and power consumption.
P6 micro-architecture – A micro-architecture introduced on the Pentium Pro in 1995 and used in
the Pentium II, Pentium III, Pentium II Xeon, Pentium III Xeon, and some Celeron processors. This
architecture defined how instructions were executed. P6 micro-architecture consisted of three major
units (fetch/decode, dispatch/execute, and retire unit) and a dual independent bus (a backside bus to
L2 cache and a frontside bus to the memory controller).
Pipeline – An "assembly line" design where instruction processing is broken into many small steps
or stages that are handled by separate circuits. When an instruction completes one stage, it
progresses to the next, and the earlier stage begins work on the subsequent instruction. The
processor has the capability of processing multiple instructions simultaneously at varying stages of
execution to obtain an overall instruction execution rate of one instruction per clock cycle. A higher
number of stages in the pipeline allow it to reach a faster clock speed; the disadvantage is the entire
pipeline must be flushed and reloaded during a branch miss (common with business applications)
effectively wasting processor cycles.
Privilege levels – Intel x86 processors support four privilege levels that are referred to as rings 0
through 3. Kernal mode is synonymous with ring 0. Applications run in ring 3. The rings provide
hardware-based protection mechanisms as the hardware prevents programs that are running in less
privileged rings from overwriting the contents of memory controlled by more privileged programs.
Processor architecture – Processor architecture refers to the instruction set, registers, and memory
data-resident data structures that are public to a programmer. Processor architecture maintains
instruction set compatibility so processors will run code written for processor generations past,
present, and future.
Reduced Instruction Set Computing (RISC) – Processors without microcode but with hardwired
instructions. RISC processors have uniform instruction lengths.
Register – A small, high-speed, on-chip storage area in a processor. Registers are the fastest type of
storage used by a processor. The more registers and the more bits each register holds, the more
compilers can optimize application performance. Registers are usually designed for certain tasks
such as floating-point, address, general-purpose, special-purpose, etc.
Retire – To commit results to architectural registers and memory. Instructions that are executed
speculatively cannot be retired until it is certain that all dependencies have
been resolved.
Serialize – To force the processor to stall the issuing of instructions until a particular instruction has
been retired. Serialization is required by certain instructions that cannot be processed out of order.
Speculative execution – An enhancement of branch prediction that speculatively executes the
predicted branch. If the branch is wrong, the processing must be corrected, but if the branch is
correct, the processor is further ahead. This method keeps objects in the pipeline without stalling
and waiting for a branch to be resolved.
Stall – To halt a portion of a pipeline for one or more clock cycles.
Super-pipelined – Having a pipeline substantially deeper than the usual five or six stages. Super-
pipelined designs tend to allow higher clock speeds than other pipelined designs.
Superscalar – The ability to process multiple instructions in a clock cycle. The Pentium processor
and after are superscalar due to their dual-pipeline structure. Both the 386 and i486 are scalar since
they only have one pipeline. Pentium has two execute units (integer units). Other processors have
multiple execution units.
Toroid – An electrical component that regulates electrical power to a device; looks like a doughnut
with wires around it. Higher wattage processors and chipsets require more toroids on a
systemboard.
Transistor – A device to open and close a circuit in a processor. Like a light switch on the wall that
lets electricity go to a light bulb, a transistor performs like a simple switch, either allowing or
preventing current to flow through. In general, a processor with more transistors is more powerful.
More transistors also make a processor run hotter. The smaller the transistor, the quicker the chip
can move electrons between them and the faster it can perform each calculation resulting in better
performance.
Voltage Regulator Module (VRM) – Processors and/or L2 cache may utilize a voltage regulator
module, which allows different processor voltages to be supported by interchangeable VRMs.
VRMs are physical circuitry that plug in to a socket near the processor's socket/slot.
Processor Features:
Math Coprocessors
Math Coprocessors
The math coprocessor, also called the FPU (floating point unit) or coprocessor, has special circuits
that allow it to process numeric floating point calculations in fewer cycles than the main processor.
Floating point multiplies are several times faster than standard integer execution units for numeric
calculations. The math coprocessor is also used when the algorithm requires a large range or a lot
of precision in its results.
Applications must be specifically written to take advantage of the math coprocessor. Typically only
CAD, statistical analysis, vector graphics, and numeric applications utilize the math coprocessor.
Most operating systems, including Windows and Linux, do not utilize a math coprocessor (except
for minor use in the graphics engine).
Intel processors beyond the 486DX have integrated math coprocessors.
Examples of math coprocessors for earlier processors:
Processor Features:
Clock Multipliers
© 2008 Lenovo
Clock Multipliers
The clock multiplier is the ratio between the internal clock speed and the external bus speed (the
system bus or front side bus). A processor runs internally at a faster speed than externally.
Anything internal to the physical chip runs at this fastest speed (i.e., the math coprocessor, L1
cache, and L2 cache). The speed to the memory controller is reduced to 100, 133, or 200 MHz.
While running everything at the fastest speed is ideal, the dollar cost of doing this is prohibitive.
Having slower external speeds reduces engineering design costs, makes all the external peripherals
less costly, and reduces frequency emission.
The system bus has migrated from 100 MHz to 133 to 200 to 233 to 266 MHz. The Core 2 Duo
uses an 800 MHz or 1067 MHz system bus, yet this is really still a 200 or 233 MHz bus that is
quad-pumped (four transfers in one cycle).
Processor Features:
Burst Mode Transfer
Processor Features:
MMX, SSE, SSE2, SSE3, SSE4 [HD Boost]
© 2008 Lenovo
MMX
Intel's MMX technology is designed to accelerate key elements of demanding multimedia and
communications applications such as audio, video, 2D and 3D graphics, animation, and speech
recognition. Intel insists MMX does not stand for Multimedia Extensions, so MMX does not
officially stand for anything.
MMX technology was first implemented in second generation Pentium processors in 1997, and
MMX has been implemented in all subsequent Intel processors.
MMX highlights include the following:
• Fifty new instructions
• Eight 64-bit wide MMX registers and four new data types
• Single Instruction, Multiple Data (SIMD) technique
MMX technology includes 57 new instructions, which accelerate calculations common in audio,
2D and 3D graphics, video, speech synthesis and recognition, and data communications algorithms
by as much as 8x.
Intel processors with MMX technology can execute two MMX instructions simultaneously.
Most MMX instructions follow the pattern of performing a single operation on a series of integer
values. This technique is called Single Instruction, Multiple Data (SIMD). SIMD is ideal for the
algorithms and data types frequently found in multimedia software. Examples include wavelet
compression, MPEG, motion compensation, color space conversion, texture mapping, 2D filtering,
matrix multiplication, fast Fourier transforms, discrete cosine transforms, and phoneme matching.
In general, such routines consist of small, repetitive loops that operate on 8-bit or 16-bit integers. It
is these routines that yield the greatest overall performance increase when converted to MMX-
optimized code.
MMX has no impact on the operating system, so it is compatible with existing x86-based operating
systems. Applications can take advantage of MMX in two ways. Either it can use MMX-enabled
drivers (like a graphics driver), or it can add MMX instructions to critical routines. Most
applications utilize the MMX drivers.
Processor Features:
Hyper-Threading (HT) Technology
Hyper-Threading Dual-core
AS AS
One physical processor
One physical processor
with two logical cores
with two physical cores
(one physical core)
Processor
execution Parallel threads executed Parallel threads executed
resources on a single core with on separate cores with
shared resources dedicated resources
© 2008 Lenovo
Logical AS AS AS AS
Processor
IA-32 IA-32
The physical processor Processor Each processor is a
Processor
consists of two logical separate physical
processors that share a processor
single processor core
Hyper-Threading delta
Physical processor
1.0
One-way Two-way
Although existing operating system and application code will run correctly on a processor with
Hyper-Threading technology, developers must rewrite code for multithreading support to get the
optimum benefit from Hyper-Threading technology. Microsoft Windows XP, Windows Vista, and
Linux are already multithreading operating systems. Device drivers can also be written to utilize
multithreading. For full support, the BIOS, OS, and chipset must support Hyper-Threading.
If the user enables Hyper-Threading technology in BIOS, Windows Server will detect and use
logical processors, which are not counted against the Windows licensing limit. Windows will first
count physical processors, and, if the license permits more processors, then logical processors will
be counted.
Thread 1:
Process data Time
With
Hyper- saved
Thread 2:
Threading Get network data
Processor Features:
Intel 64 Technology
© 2008 Lenovo
Intel 64 Technology
Intel 64 Technology (Intel 64) is an enhancement to Intel’s IA-32 (Intel Architecture 32-bit or
x86) architecture that allows the processor to run 64-bit code that has been compiled for the
Intel 64 architecture. The enhancement allows the processor to run newly written 64-bit code
and access larger amounts of memory. Intel 64 used the code names Yamhill and Clackamas
Technology (CT). Intel 64 Technology is an extension of the 32-bit x86 or IA-32 instruction set.
Intel 64 Technology was originally named Extended Memory 64 Technology (EM64T), but
was renamed in July 2006 with the announcement of the Intel Core micro-architecture.
Systems utilizing the Intel 64 instruction set extensions allow applications to run the existing
base of 32-bit applications or new 64-bit applications which permits migration to 64-bit
applications to take place within any future timeframe.
These extensions do not run code written for the Intel Itanium processor family known as IA-
64. The Itanium processor family is based on the Explicitly Parallel Instruction Computing
(EPIC) architecture. Itanium processors can run 32-bit software in the IA-32 Execution Layer
(IA-32 EL), but Intel has not stated that this layer will support Intel 64 code; this IA-32 EL does
not run 32-bit x86 applications natively, but translates the 32-bit instructions into code the
Itanium can run. Operating systems required for IA-64 will not run on Intel 64 processors (and
vice versa).
64-Bit Computing
The terms 64-bit and 32-bit refer to the number of bits that each of a processor's general-purpose
registers (GPRs) can hold. The phrase 64-bit processor depicts a processor whose register width is
64 bits. A 64-bit instruction is an instruction that operates on 64-bit data. When applied to a
processor, the bits characterize the processor’s data stream; so, a 64-bit processor has 64-bit register
widths and can perform operations on 64 bits of data at a time.
AMD64 Comparison
Intel 64 Technology is compatible with and nearly identical to AMD64 found in the various AMD
processors (with the exception of a few instructions such as 3DNow!). Even though the hardware
microarchitecture in Intel and AMD processors is different, the operating system and applications
ported to one processor will likely run on the other processor. Both Intel 64 and AMD64 are based
on AMD’s x86-64 instruction set extensions.
More Registers
Intel's IA-32 processors with Intel 64 Technology have 16 General Purpose Registers (GPRs) with
64-bit width and 16 XMM registers with 128-bit width. The additional registers are only used by
applications running in 64-bit mode. IA-32 processors without Intel 64 have 8 GPRs with 32-bit
width and 8 XMM registers with 128-bit width. A processor with more registers does not have to
retrieve data from cache as often, so it has better performance.
Advantages
Intel 64 Technology allows Intel processors to directly access in excess of 4 GB of memory. With
64-bit memory address limits, the theoretical memory size limit is 16 billion gigabytes (16 exabytes
[EB]), but systems will not implement the full 64-bit addressability. IA-32 processors can only
address a maximum of 4 GB which is a major limitation for large databases and digital content
creation solutions. For example, the Xeon processor with Intel 64 supports 48 bits of virtual
memory and up to 40 bits of physical memory; this allows access to 256 TB of virtual memory and
1 TB of physical memory.
When a 32-bit application is run on an Intel 64 processor, software still limits memory access to 4
GB and performance might not improve. Recompilation will be required to take advantage of
memory in excess of 4 GB. An application recompiled to run in a 64-bit environment will be able
to access significantly more memory, and performance might improve if the application was
previously memory constrained.
Another advantage of 64-bit processors is the ability to handle larger floating-point numbers that
are used in scientific and engineering calculations. While 32-bit processors can only handle
floating-point calculations with values up to 232 (about 4 billion) unless they resort to software
emulation, 64-bit processors can directly use up to 264 (about 18 billion billion [exabytes]).
Processor Features:
Intel 64 Technology Support
© 2008 Lenovo
IA-32e Mode
Mode Legacy Mode
Compatibility 64-bit
Default Sizes Address 32/16 32/16 64
Operand 32/16 32/16 32
General-purpose register width 32 32 64
Operating system required 32/16 64 64
Application recompile required No No Yes
Hardware Support
To run 64-bit applications, the system will need a 64-bit OS, IA-32 processor with Intel 64
Technology, updated BIOS, and updated drivers that support Intel 64 Technology.
Processor Features:
Execute Disable Bit
Processor Features:
Dual-core
Dual-core
In 2005, Intel introduced processors utilizing dual-cores which is two independent cores within
a single physical processor die. The first dual-core processors were the Intel Pentium D
Processor 8xx and Intel Pentium Extreme Edition 8xx. With previous single-core processors,
the traditional way to increase performance was to increase the clock speed. However,
increasing clock speeds has its limits due to power consumption and thermal problems. Dual-
core technology allows a duplication of execution resources to provide increased system
responsiveness in multi-tasking environments and headroom for next-generation multi-threaded
applications and new usages.
The move to multiple processor cores is the logical solution to the speed barrier single-core
processor designs have encountered. Adding multiple cores can increase processor power
without increasing clock speeds. Having multiple processor cores has the added benefit of
improving PC performance in situations where users need to run multiple applications at the
same time, for example, when watching a DVD movie while encoding an MP3 file. Each
application can have its own dedicated processor core rather than sharing a single core, which
can hinder the performance of one or both applications.
A dual-core processor provides multi-tasking benefits because it is like having an extra engine
in your car. It also provides multi-user benefits because on a home network one person can use
the PC while another person accesses and interacts with stored content from the same PC even
from other rooms. For example, your son plays a game on a PC in his bedroom. Using a remote
control, your daughter accesses the same PC to listen to music, even though she is in the family
room. A digital media adapter enables her to send the music to a stereo so she can listen to it.
Software
Software (operating systems and applications) needs to be written to run multiple threads
simultaneously to take advantage of additional processor cores, i.e., they must be multi-threaded. Multi-
threaded means the application can run multiple bits of code simultaneously. An example of a multi-
threaded operation is when a Word document is opened, antivirus code can automatically scan the file
in a separate thread. Another example is having a thread record a TV show in the background. Modern
operating systems can handle multiple threads of program execution at the same time either from a
single multi-threaded application or from multiple, single-threaded applications. Microsoft Windows
XP and Vista, as well as over 200 applications such as Adobe Photoshop CS and Roxio VideoWave
7.0, are multi-threaded. Most of today's multi-threaded applications focus on content creation and
multimedia production, which tend to perform many operations in parallel. As dual-core technology
becomes more prevalent, you can expect to see more multi-threaded applications become commonplace
such as 3D-intensive games that can take advantage of dual-core technology by using more robust
physics and artificial intelligence engines for more realistic effects and gameplay.
The operating system sees each of the execution cores as a discrete logical processor that is
independently controllable.
If software is already written to take advantage of Hyper-Threading technology, only a few adjustments
are needed for the software to utilize dual cores.
Processor Features:
Dual-core and Hyper-Threading
• Earlier dual-core processors use Hyper-Threading Technology
- Pentium D Processor 9xx
- Pentium Processor Extreme Edition 8xx and 9xx
- Can process four threads
• The latest dual-core and quad-core processors do not use Hyper-Threading Technology
- Core 2 Duo
- Core 2 Quad
Type Logical View Processing Example
Each thread processed Celeron M 3xx
1
No Hyper-Threading (HT) serially through single Celeron D 3xx
execution core Pentium M 7xx
1 Two threads processed Mobile Pentium 4 5xx
Hyper-Threading (HT) through two logical cores in
2
increasingly parallel manner Pentium 4 5xx and 6xx
© 2008 Lenovo
Processor Features:
Dual-core Features
Earlier Intel dual-core processors The latest Intel processors use shared
use independent L1 and L2 caches L2 cache (Intel Smart Cache)
• Pentium D 8xx and 9xx • Core 2 Duo Processor
• Core 2 Quad Processor
© 2008 Lenovo
Dual-core Features
Dual-core processors differ from single-core processors by providing two independent
execution cores. While some execution resources are shared, each logical processor has its own
architecture state with its own set of general-purpose registers and control registers to provide
increased system responsiveness. Each core runs at the same clock speed.
Shared L2 Cache
The Intel Core Duo Processor features a shared 2 MB L2 cache with Advanced Transfer Cache
Architecture and system bus between the two execution cores called Intel Smart Cache. The Intel
Core 2 Duo Processor features a shared 2 MB or 4 MB L2 cache that uses the name Intel Advanced
Smart Cache. These shared L2 caches enable the active execution core to access the full 2 MB
cache when one other execution core is idle. Dynamic cache allocation across both cores enhances
performance and reduces cache under-utilization and misses. Shared L2 cache enables single copy
of data to be used by each execution core. Shared cache designs may directly transfer data between
L1 caches, or between L2 and L1 caches.
Dual-core Performance
Multi-threaded applications or running multiple applications simultaneously could provide up to
70% performance improvement on dual-core processors.
For single-threaded, single-focus tasks, using a faster clocked single-core processor provides better
performance than a slower clocked dual-core processor. But a user who runs multiple applications
at once with several simultaneous operations will immediately see benefits from any dual-core
processor.
Because Windows XP itself is multithreaded, multi-threaded applications do not have to be running
to achieve a performance gain. Windows is a multitasking environment, so there are usually
applications running in both the foreground (such as an Internet browser) and the background (such
as virus scanning). A dual-core processor should execute the multiple threads of these applications
more efficiently.
Dual-core processors perform better than single-core chips even at slower clock speeds because
they reduce power consumption and heat dissipation.
See www.intel.com/technology/computing/dual-core for more information.
Processor Features:
Quad-core Features
Execution
Execution
Execution
Execution
Core
Core
Core
Core
L1 L1 L1 L1
Cache Cache Cache Cache
L2 Cache L2 Cache
© 2008 Lenovo
Quad-core Features
Quad-core processors differ from single-core and dual-core processors by providing four
independent execution cores. While some execution resources are shared, each logical processor
has its own architecture state with its own set of general-purpose registers and control registers
to provide increased system responsiveness. Each core runs at the same clock speed.
The Intel Core 2 Quad Processor (codenamed Kentsfield announced January 2007) features a
total of 8MB of L2 cache. This processor is really a dual-core on a dual-die; each dual-core has
a shared 4 MB L2 cache. So with two 4 MB L2 caches, the processor has 8 MB L2 cache total.
Processor Features:
Virtualization Technology
© 2008 Lenovo
Virtualization Technology
Virtualization refers to a single system running multiple operating systems and applications in
independent partitions. With virtualization, one computer system can function as multiple "virtual"
systems.
Servers are the main systems using virtualization, so this implementation is called server
virtualization. Server virtualization allows a single physical server to support multiple operating
systems which support many applications and users. Desktops and notebooks are only now starting
to implement virtualization under the term desktop virtualization.
By building virtualization hooks into its processors, Intel (along with AMD with its virtualization
technology) gives third-party developers direct access to the primary operational layer of the
processor. Having support in a processor for virtualization is also called processor-assisted
virtualization, hardware-assisted virtualization, or embedded virtualization.
Intel Virtualization Technology (code-named Vanderpool) improves the robustness and
performance of software-only solutions (such as using VMware on processors without hardware-
assisted virtualization). The Intel Virtualization Technology Specification was released in late
2005.
AMD released a technical specification for virtualization in early 2006.
Virtualization abstracts software from the underlying hardware infrastructure. In effect, it cuts the
link that ties a specific software stack to a particular system. This enables more flexible control of
both hardware and software resources, which can deliver value across a wide range of IT
requirements. It provides a spare box on which you can quickly throw a test OS to check out an
application or problem without messing up your primary workstation.
Virtualization eliminates the need for performance-sapping workarounds that make software-only
solutions behave much like emulation; the technology eliminates the need to emulate an x86 to
virtualize it.
For more information about Intel Virtualization Technology, visit the Intel Web site at
intel.com/technology/virtualization.
The applications run The virtual machine runs With the hypervisor
directly on the OS, as an application on the layer between the
which runs directly on host OS. There is an hardware and OSs,
the hardware. intermediary layer of each OS thinks it
software between the is running in the
host OS and the guest standard configuration,
OS. but in fact it is sharing
Examples are Microsoft the resources of the
Virtual PC and VMware base hardware.
GSX Server. Examples are VMware
ESX Server and Xen 3.0
Companies/
Type Description Pros Cons
Products
Hosted Virtualization Machine Manager • VMware Server • Simple installation and • System overhead
(VMM) is installed on top of a (GSX) management • Limited flexibility
host OS • Microsoft Virtual • Failure in the host OS will
Server 2005 impact all virtual
machines running on that
server
Hypervisor A hypervisor is installed directly • VMWare ESX • Higher performance • Lower performance than
on the hardware (often referred Server compared to hosted paravirtualizaton as the
to as "bare metal" virtualization) virtualization as the guest OSs are not made
versus on top of the operating hypervisor interacts "virtualization aware"
system in the hosted architecture directly with the
hardware
• More scalable and
flexible than hosted
virtualization
Virtualization Configurations
Guest
Operating Operating Operating Operating OS
System System System System
Processor Features:
Virtualization Technology Processors and Software
© 2008 Lenovo
Other than vendors such as VMware and Microsoft, there is an open-source approach to
virtualization from the Xen project. Xen uses paravirtualization which means that the OSes running
on the hypervisor need to be modified to make them run simultaneously. The paravirtualization
method uses a thin layer between the hardware and the OS, with an I/O virtualization scheme that
employs a single set of drivers used by all guest OSes. Xen claims that paravirtualization improves
efficiency and speed. Its Xen 3.0 can create Windows, Linux, and Solaris virtualized servers. See
www.xensource.com for more information.
VMware uses transparent virtualization which means the OSes that run on the hypervisor are not
modified.
Over the next few years, Microsoft intends to phase out separate virtualization products and put
virtualization functionality in the Windows OS. In late 2006, Microsoft released Virtual PC 2007
(replacing Virtual PC 2004), adding support for Windows Vista as a host operating system.
Processor Features:
Intel Dynamic Acceleration
• Boosts performance of one core when the other core is inactive
• Used with single-threaded or multi-threaded applications when
extended serial code is executed
• Maintains reasonable thermal dissipation
• Introduced in notebook-based Intel Core 2 Duo processors with
Socket P
© 2008 Lenovo
Processor Features:
Intel Trusted Execution Technology (TXT)
• Enables more secure PC platform
• Hardware extensions to select Intel 3rd Party Software
processors and chipsets including Virtual Machine
Processor Monitor
• Protects against software-based requires
VT and TXT
attacks
Chipset has TXT
• Protects data in virtualized support, VT-d support,
and TPM 1.2 interface
environments Processor
• Requires many hardware,
software, and BIOS
Chipset
components Memory
Graphics
lash
• Introduced in 2007 in AC module and BIO
S/F
select Intel Core 2 platform 3rd Party
initialization Intel Hardware
Duo E6x50 processors Software (TPM v1.2)
Input Devices
Intel Trusted Execution Technology requires a computer system with Intel Virtualization
Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules, and an
Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual
machine monitor, an OS, or an application. In addition, Intel TXT requires the system to contain a
TPM v1.2, as defined by the Trusted Computing Group and specific software for some users. Local
laws and regulations may limit Intel TXT's available in certain countries. For more information, see
www.intel.com/technology/security.
Host Hardware
Memory Processor & CS I/O Devices TPM 1.2
Processor Features:
Intel Core Micro-architecture
NetBurst Core
micro-architecture micro-architecture
Pentium-based and Celeron-based Celeron (2007 and after)
processors (2000-2006) Pentium Dual-Core (2007 and after)
Core Solo processor (2006) Core 2 Duo (2006 and after)
Core Duo processor (2006) Core 2 Extreme (2006 and after)
Core 2 Quad (2007 and after)
© 2008 Lenovo
1 1 1 1
Fetch 2 Decode 2 Queue 2 Execute 2 Retire
3 3 3 3
1
With Intel Wide Dynamic Execution
1 1 1 1
2 2 2 2
Fetch Decode Queue Execute Retire
3 3 3 3
4 4 4 4
Further efficiencies include more accurate branch prediction, deeper instruction buffers for greater
execution flexibility, and other features that reduce the number of required execution cycles.
For example, Macro-Fusion is a new feature that reduces execution cycles within each execution
core. In previous generation processors, each incoming program instruction was individually
decoded and executed. Macro-Fusion enables common pairs of these instructions to be combined
into a single instruction during decoding, and then subsequently executed as a single instruction.
This reduces the total number of executed instructions, allowing the processor to process more
instructions in less time, all while using less power.
Without Macro-Fusion
With Macro-Fusion
Instruction Decoder Execution
Combine 11
Rename/Alloc Rename/Alloc
4 Wide-Micro-Op
to Execute
Schedulers Schedulers
Enhanced ALUs
Execute Execute
Advantage
Performance
Wider execution
Comprehensive advancements
Energy Enabled in each core
With the Intel Wide Dynamic Execution of the Intel Core micro-architecture, every execution core in a
multi-core processor is wider. This allows each core to fetch, dispatch, execute, and return up to
four full instructions simultaneously.
Without Intel Intelligent Power Capability With Intel Intelligent Power Capability
L2 Cache RAM
Core 2
RAM
Core 2
L2 Cache
Intel Advanced Smart Cache allows each core to dynamically utilize up to 100% of
available L2 cache, while obtaining data from the cache at higher throughput rates.
Shared L2
Decreased Traffic
L1 Cache L1 Cache
Core 1 Core 2
Independent L2
Increased Traffic
Not Shareable
L1 Cache L1 Cache
Core 1 Core 2
In a multi-core processor where two cores do not share L2 cache, an idle core also means
idle L2 cache space. This is a critical waste of resources, especially when another core
may be suffering a performance hit because its L2 cache is too full. Intel's shared L2
cache design enables the working core to dynamically take over the entire L2 cache and
maximize performance.
F
Without Memory Disambiguation
Execution Retire
4 3
Instruction Sequence
3
I H
5 4
Instruction Sequence
4
64 64
128 bits 128 bits
bits bits
128 bits 128 bits 128 bits 128 bits 128 bits
127 0
Source
X4 X3 X2 X1
SSE/2/3 OP With Intel Single Cycle
Y4 Y3 Y2 Y1 SSE, 128-bit instructions
Dest can be completely
executed at a throughput
Intel Core
rate of one per clock cycle,
Microarchitecture
effectively doubling the
Clock Cycle 1 X4opY4 X3opY3 X2opY2 X1opY1 speed of execution for
these instructions.
Not Intel Core
Clock Cycle 1 X2opY2 X2opY2
Microarchitecture
Clock Cycle 2 X4opY4 X3opY3
Advantage
Performance
Increased performance
128-bit single cycle in each core
Energy Improved energy efficiency
Processor Packaging
Desktop systems
• Flip-Chip Land Grid Array (FC-LGA)
- LGA775 socket for 775-land Flip-Chip LGA
package (FC-LGA4, FC-LGA6, FC-LGA8)
Notebook systems
• Micro Ball Grid Array (Micro BGA) Flip-Clip Land Grid
Array (FC-LGA)
• Micro Pin Grid Array (Micro PGA)
© 2008 Lenovo
Processor Packaging
Processors implement different types of packaging, depending on the requirements of the system.
Pin Grid Array (PGA) – Most early Celeron, Pentium III, and Pentium 4 processors in desktops use
PGA packaging. PGA is a type of chip in which the connecting pins are located on the bottom in
concentric squares. The early Pentium 4 used a 423-pin socket with PGA package technology,
which is called PGA423 or PGA423 socket.
Flip-Chip PGA4 (FC-PGA4) – The Flip-Chip Pin Grid Array 4 (FC-PGA4) package was
introduced in February 2004 with the Pentium 4 code-named Prescott. The package is also used
with the Intel Celeron D Processor 3xx. This processor uses a 90 nm process consisting of a
processor core mounted on a pinned substrate with an integrated heat spreader. This packaging
employs a 1.27 mm [0.05 in] pitch for the substrate pins.
Land Grid Array – The Pentium 4 Processor 5xx and 6xx and Pentium D Processor 8xx in the 775-
land package are packaged in a Flip-Chip Land Grid Array (FC-LGA4) package that interfaces
with the systemboard via an LGA775 socket. In January 2006, the FC-LGA6 was introduced as a
follow on to the FC-LGA4. The FC-LGA6 is used on the Pentium 4 Processor 6x1, Pentium D 9xx,
Core 2 Duo, and Core 2 Quad. The LGA775 is also called Socket T. In January 2008, the FC-
LGA8 was introduced as a follow on to the FC-LGA6; it was first used in the Core 2 Duo
Processor (Wolfdale). The package consists of a processor core mounted on a substrate land-
carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves
as the mating surface for processor component thermal solutions, such as a heatsink. The figure
below shows a sketch of the processor package components and how they are assembled.
FC-LGA4 Package
Core (die) Integrated Heat
Spreader
Substrate Thermal Interface
Material
Capacitors
Systemboard
LGA775 Socket
LGA775 socket
Micro Pin Grid Array (Micro PGA) or Micro Flip Chip PGA (Micro-FCPGA) – Introduced by
Intel in May 1999, this processor packaging uses pins that insert into a socket. It is used for
notebook-based processors. The Micro PGA processor packaging type is slightly larger than a
postage stamp and consists of the processor and a tiny socket, which combined measure only 32 by
37 millimeters in dimension and less than six millimeters in height. The pins on the package are
only 1.25 millimeters long (about the thickness of a dime), making it Intel's smallest "pinned"
processor package. With the introduction of the 0.13 micron Mobile Pentium III-M (Tualatin) in
July 2001, this packaging migrated to a new technology called Micro Flip Chip Pin Grid Array
(Micro-FCPGA), but still consisted of inserting pins into a socket. Flip chip describes the method
of electrically connecting the die to the package carrier. The Celeron M, Pentium M, Core, and
Core 2 Duo processors use the newer Micro-FCPGA.
Ball Grid Array (BGA) or Micro Flip Chip BGA (Micro-FCBGA) – Ball Grid Array is a packaging
type for extremely small devices that are soldered to a larger board. It is commonly used in
notebook-based systems. Ball Grid Array packaging replaces pins with solder balls on the
underside for mounting. It is less than a tenth of an inch high and weighs less than a nickel. BGAs
are available in a variety of types ranging from plastic over molded BGAs called PBGAs, to flex
tape BGAs (TBGAs), high thermal metal top BGAs with low profiles (HL-PBGAs), and high
thermal (H-PBGAs). With the introduction of the 0.13 micron Mobile Pentium III-M (Tualatin) in
July 2001, this packaging migrated to a new technology called Micro Flip Chip Ball Grid Array
(Micro-FCBGA). Flip chip describes the method of electrically connecting the die to the carrier
package, but still consists of solder balls on the underside for mounting. The Celeron M, Pentium
M, and Core processors use the newer Micro-FCPGA.
Microprocessor
controlled heat pipe
provides super
efficient heat transfer
from CPU and
minimizes fan use,
resulting in long
battery life. This
technology also keeps Processor die
noise levels low.
Underfill
Solder balls
Ball Grid Array with Die Up Cross-Section
Performance
High Performance
Intel Core 2 Extreme Processor
© 2008 Lenovo
Desktop Processors
This slide shows the Intel desktop processors and chipsets.
Industry Standards:
Intel Core 2 Processor with Viiv Technology
© 2008 Lenovo
© 2008 Lenovo
These features are also available in Intel Centrino 2 with vPro Technology for notebooks. But this
second generation Intel vPro technology also introduced the following:
• Improved system defense filters which can identify greater numbers and varieties of threats in the
network traffic flow.
• An embedded trust agent, the first certified by Cisco, providing the industry's only 802.1x
compatible manageability solution not dependent on OS-availability. This trust agent offers
Cisco's IT customers the ability to manage systems, even if powered off or the OS is down,
without lowering the security on 802.1x networks and Cisco Self-Defending Network products.
• An industry-leading foundation for Windows Vista
• Convenient remote configuration
– More convenient option for over-the-wire set-up
– Allows transfer of Intel AMT keys over the network during set-up
• Next-generation management standards (Web Services Management (WS-MAN and DASH)
– More capable, extensible and secure than Alert Standard Format (ASF)
– Standardizes management between console and PC and inside PC
– Built using draft-DASH standards. DASH (Desktop and Mobile Architecture for System
Hardware) is a web services-based management technology that enables IT professionals to
remotely manage desktop and mobile PCs from anywhere in the world, securely turn the power
on/off, query system inventory, and push firmware updates among other things, regardless of
the state of the remote PC.
• Intel Trusted Execution Technology (TXT) and Intel Virtual Technology for Directed I/O (VT-d)
– Hardware rooted security architecture and foundation for ISV solutions
– Initial enabling around trusted virtual appliances
– Significantly reduces risk of “hyper-jacking” or rootkit attacks
• Energy-efficient performance
– Performance leadership with quad-core processors and faster front side bus
– Lower CPU idle and chipset power
– Improved graphics performance
See developer.intel.com/products/vpro/index.htm for more information.
© 2008 Lenovo
Features
Key features of the Intel Celeron desktop processor includes the following:
• Core micro-architecture.
• 0.065 micron technology (or 65 nanometers).
• Single-core.
• 64 KB L1 cache (32 KB L1 instruction cache; 32 KB L1 write-back data cache).
• On-die 512 KB L2 cache. The L2 cache runs at the core processor speed. It is 8-way set
associative using a 64 byte cache line.
• No L3 cache.
• 800 MHz system bus which transfers data four times per bus clock (4X) with a double-clocked
address bus (2X). The system bus has a 64-bit data path.
• Intel Smart Memory Access optimizes the use of the data bandwidth from the memory subsystem
to accelerate out-of-order execution.
• Intel 64 Technology support providing 64-bit operating systems and application support.
• No support for Intel Virtualization Technology.
• Intel Advanced Digital Media Boost which accelerates execution of Steaming SIMD Extension
(SSE) instructions used in multimedia and graphics applications. The 128-bit SSE instructions are
issued at a throughput rate of one per clock cycle.
• Execute Disable Bit support.
• No Hyper-Threading Technology support.
• Four total execution units:
– 1 integer units [often called Arithmetic Logic Units (ALU)]
– 1 floating point unit
– 1 load unit
– 1 store unit
• Uses a 775-land Flip-Chip Land Grid Array (FC-LGA6) package requiring an LGA775 socket
(the mobile version uses different packaging).
Celeron
420, 430, 440, 450
(Conroe-L)
1.60, 1.80, 2.00, 2.20 GHz
Single-core
512 KB L2 cache
800 MHz system bus
No Virtualization Technology
Intel 64 and Execute Disable Bit
June 2007 and after
© 2008 Lenovo
Main memory
400, 533, or
800 MHz
64-bit
Pin Grid Array
System Bus
Frequently used paths
Less frequently used paths
Bus Unit
Front End
Fetch/ Execution
Trace Cache Execution Retirement
Decode
Microcode ROM
© 2008 Lenovo
Features
Key features of the Intel Celeron Dual-Core desktop processor includes the following:
• Core micro-architecture.
• 0.065 micron technology (or 65 nanometers).
• Dual-core processing using two independent cores in one physical package that run at the same
frequency.
• 64 KB L1 cache per core (32 KB L1 instruction cache per core; 32 KB L1 write-back data cache
per core).
• Shared on-die 512 KB L2 cache called Intel Advanced Smart Cache. The L2 cache runs at the
core processor speed. It is 8-way set associative using a 64 byte cache line. Intel Advanced Smart
Cache enables the active execution core to access the full L2 cache when the other execution core
is idle.
• No L3 cache.
• 800 MHz system bus which transfers data four times per bus clock (4X) with a double-clocked
address bus (2X). The system bus has a 64-bit data path.
• Intel Wide Dynamic Execution improves execution speed and efficiency with each core
completing up to four full instructions simultaneously with a 14-stage pipeline. The Core 2 Duo
supports micro-op fusion when an x86 instruction is decoded into micro-ops and two adjacent,
dependent micro-ops combine into a single micro-op and execute in a single cycle. A new feature
is "Macro-op fusion" which means certain x86 instructions may also be paired into a single
instruction, then executed in a single cycle. In certain cases, five instructions can be read from the
instruction queue, then executed as if only four instructions were issued.
• Intel Smart Memory Access optimizes the use of the data bandwidth from the memory subsystem
to accelerate out-of-order execution.
• Intel 64 Technology support providing 64-bit operating systems and application support.
Core1 Core
2
Bus
L2 Cache
System Bus
ROM
Decode Decode
Rename/Alloc Rename/Alloc
Schedulers Schedulers
FPU ALU ALU Load Store Store Load ALU ALU FPU
Celeron Dual-Core
E1200, E1400
(Conroe)
1.60, 2.00 GHz
Dual-core
512 KB Shared L2 cache
800 MHz system bus
No Virtualization Technology
Intel 64 and Execute Disable Bit
January 2008 and after
© 2008 Lenovo
Execution Execution
Core Core
L1 Cache L1 Cache
L2 Cache Control
L2 Cache
Processor Structure of
Intel Celeron Dual-Core Processor
Features
Key features of the Intel Pentium Dual-Core desktop processor includes the following:
• Core micro-architecture.
• 0.065 micron technology (or 65 nanometers).
• Dual-core processing using two independent cores in one physical package that run at the same
frequency.
• 64 KB L1 cache per core (32 KB L1 instruction cache per core; 32 KB L1 write-back data cache
per core).
• Shared on-die 1 MB or 2 MB L2 cache called Intel Advanced Smart Cache. The L2 cache runs at
the core processor speed. It is 8-way set associative using a 64 byte cache line. Intel Advanced
Smart Cache enables the active execution core to access the full L2 cache when the other
execution core is idle.
• No L3 cache.
• 800 MHz system bus which transfers data four times per bus clock (4X) with a double-clocked
address bus (2X). The system bus has a 64-bit data path.
• Intel Wide Dynamic Execution improves execution speed and efficiency with each core
completing up to four full instructions simultaneously with a 14-stage pipeline. The Core 2 Duo
supports micro-op fusion when an x86 instruction is decoded into micro-ops and two adjacent,
dependent micro-ops combine into a single micro-op and execute in a single cycle. A new feature
is "Macro-op fusion" which means certain x86 instructions may also be paired into a single
instruction, then executed in a single cycle. In certain cases, five instructions can be read from the
instruction queue, then executed as if only four instructions were issued.
• Intel Smart Memory Access optimizes the use of the data bandwidth from the memory subsystem
to accelerate out-of-order execution.
• Intel 64 Technology support providing 64-bit operating systems and application support.
Core1 Core
2
Bus
L2 Cache
System Bus
ROM
Decode Decode
Rename/Alloc Rename/Alloc
Schedulers Schedulers
FPU ALU ALU Load Store Store Load ALU ALU FPU
© 2008 Lenovo
Execution Execution
Core Core
L1 Cache L1 Cache
L2 Cache Control
L2 Cache
Processor Structure of
Intel Pentium Dual-Core Processor
Features
Key features of the Intel Core 2 Duo desktop processor includes the following:
• Core micro-architecture.
• 65 nanometers (Conroe) or 45 nanometers (Wolfdale) process technology
• Dual-core processing using two independent cores in one physical package that run at the same
frequency.
• 64 KB L1 cache per core (32 KB L1 instruction cache per core; 32 KB L1 write-back data cache
per core).
• Shared on-die 2 MB, 4 MB, or 6 MB L2 cache called Intel Advanced Smart Cache. The L2 cache
runs at the core processor speed. It is 8-way set associative using a 64 byte cache line. Intel
Advanced Smart Cache enables the active execution core to access the full L2 cache when the
other execution core is idle.
• No L3 cache.
• 800, 1067, or 1333 MHz system bus which transfers data four times per bus clock (4X) with a
double-clocked address bus (2X). The system bus has a 64-bit data path.
• Intel Wide Dynamic Execution improves execution speed and efficiency with each core
completing up to four full instructions simultaneously with a 14-stage pipeline. The Core 2 Duo
supports micro-op fusion when an x86 instruction is decoded into micro-ops and two adjacent,
dependent micro-ops combine into a single micro-op and execute in a single cycle. A new feature
is "Macro-op fusion" which means certain x86 instructions may also be paired into a single
instruction, then executed in a single cycle. In certain cases, five instructions can be read from the
instruction queue, then executed as if only four instructions were issued.
• Intel Smart Memory Access optimizes the use of the data bandwidth from the memory subsystem
to accelerate out-of-order execution.
• Intel 64 Technology support providing 64-bit operating systems and application support.
• Some support Intel Trusted Execution Technology.
Core1 Core 2
Bus
L2 Cache
System Bus
ROM
Decode Decode
Rename/Alloc Rename/Alloc
Schedulers Schedulers
FPU ALU ALU Load Store Store Load ALU ALU FPU
Thermal Control
Thermal Control
Arch State Arch State
L1 Caches L1 Caches
The following table shows some key differences between the Pentium D Processor 8xx/9xx and the
Core 2 Duo processor.
800 MHz system bus 800, 1067, or 1333 MHz system bus
FC-LGA4 packaging for LGA775 socket FC-LGA6/LGA8 packaging for LGA775 socket
Intel Core 2 Duo Processor (with heat sink) Intel Core 2 Duo Processor (without heat sink)
LGA775 socket for Intel Core 2 Duo Processor LGA775 socket on Lenovo ThinkCentre systemboard
Core 2 Duo
Core 2 Duo Core 2 Duo
E4300, E4400, E4500,
E6300, E6320, E6400, E6420, E6550, E6750, E6850
E4600, E4700
E6540, E6600, E6700 (Conroe) (Conroe)
(Conroe)
1.80, 2.0, 2.2, 2.4, 2.6 GHz 1.86, 2.13, 2.33, 2.40, 2.66 GHz 2.33, 2.66, 3.00 GHz
Dual-core Dual-core Dual-core
2 MB Shared L2 cache 2 MB or 4 MB Shared L2 cache 4 MB Shared L2 cache
800 MHz system bus 1066 or 1333 MHz system bus 1333 MHz system bus
No Virtualization Technology Virtualization Technology Virtualization Technology
Intel 64 and Execute Disable Bit Intel 64 and Execute Disable Bit Intel 64 and Execute Disable Bit
None None Trusted Execution Technology
January 2007 and after July 2006 and after July 2007
© 2008 Lenovo
Core 2 Duo
Core 2 Duo Core 2 Duo
E8200, E8300, E8400,
E7200, E7300 E8190
E8500, E8600
(Wolfdale) (Wolfdale)
(Wolfdale)
2.53, 2.66 GHz 2.66 GHz 2.66, 3.00, 3.16 GHz
Dual-core Dual-core Dual-core
3 MB Shared L2 cache 6 MB Shared L2 cache 6 MB Shared L2 cache
1066 MHz system bus 1333 MHz system bus 1333 MHz system bus
No Virtualization Technology No Virtualization Technology Virtualization Technology
Intel 64 and Execute Disable Bit Intel 64 and Execute Disable Bit Intel 64 and Execute Disable Bit
None None Trusted Execution Technology
April 2008 and after January 2008 January 2008 and after
© 2008 Lenovo
Execution
Execution
Execution
Execution
systems
Core
Core
Core
Core
• Core micro-architecture
• Key features L1 L1 L1 L1
Cache Cache Cache Cache
- Quad-core
L2 Cache L2 Cache
- Dual-die L2 cache (4, 6, 8, 12 MB total)
- Intel 64 Technology
- 1066 or 1333 MHz system bus
Memory Controller Hub
• Code-name Kentsfield (January 2007)
and Yorkfield (March 2008)
© 2008 Lenovo
Features
Key features of the Intel Core 2 Quad desktop processor include the following:
• Core micro-architecture
• Q6xxx: 65 nanometers; Q8xxx/Q9xxx: 45 nanometers processor technology
• Quad-core processing using four independent cores in one physical package that run at the same
frequency.
• 32 KB L1 cache per core (so 4 x 32 KB L1 cache)
• 4, 6, 8, 12 MB L2 cache via a 2 x 3/4/8 MB shared L2 cache. The processor is actually a dual-
core on dual-die so two cores share a single L2 cache. The L2 cache runs at the core processor
speed and is called Intel Advanced Smart Cache. It is 8-way set associative using a 64 byte cache
line.
• No L3 cache
• 1066 or 1333 MHz system bus which transfers data four times per bus clock (4X) with a double-
clocked address bus (2X). The system bus has a 64-bit data path.
• Intel Wide Dynamic Execution improves execution speed and efficiency with each core
completing up to four full instructions simultaneously with a 14-stage pipeline. The processor
supports micro-op fusion when an x86 instruction is decoded into micro-ops and two adjacent,
dependent micro-ops combine into a single micro-op and execute in a single cycle. It supports
"Macro-op fusion" which means certain x86 instructions may also be paired into a single
instruction, then executed in a single cycle. In certain cases, five instructions can be read from the
instruction queue, then execute as if only four instructions were issued.
• Intel Smart Memory Access optimizes the use of the data bandwidth from the memory subsystem
to accelerate out-of-order execution.
• Intel 64 Technology support providing 64-bit operating systems and application support.
• Q6xxx/Q9xxx: Supports Intel Virtualization Technology to allow hardware-assisted
virtualization (Intel Virtualization Technology requires a system with a processor, chipset, BIOS,
virtual machine monitor (VMM) and applications enabled for Virtualization Technology).
• Intel Advanced Digital Media Boost which accelerates execution of Steaming SIMD Extension
(SSE) instructions used in multimedia and graphics applications. The 128-bit SSE instructions are
issued at a throughput rate of one per clock cycle.
• Execute Disable Bit support.
• Q9xxx: Intel Trusted Execution Technology which enables more secure platforms from software-
based attacks with appropriate software.
Execution
Execution
Execution
Execution
Core
Core
Core
Core
L1 L1 L1 L1
Cache Cache Cache Cache
L2 Cache L2 Cache
Processor Structure of
Intel Core 2 Quad Processor
(Dual-die with two L2 caches)
© 2008 Lenovo
Notebook Processors
This slide shows positioning of the Intel mobile processors.
• Intel brand name for the best mobile technologies in notebook PCs
- Performance
- Battery life
- Wireless
- Form factor
- Manageability
© 2008 Lenovo
• Intel brand name for integrated wireless and manageability in notebook PCs
• Requires three chips to receive Centrino branding
- Intel processor, Intel chipset, Intel wireless chip
• Also requires additional features for vPro branding
© 2008 Lenovo
© 2008 Lenovo
Intel Centrino Processor Technology Family (January 2008 and August 2008)
© 2008 Lenovo
Processor
Description TDP Range
Class
SP Mobile Small package Power Optimized – Energy Efficient higher performance 20-29W
© 2008 Lenovo
Features
Key features of the Intel Celeron mobile processor includes the following:
• Core micro-architecture.
• 0.065 micron technology (or 65 nanometers).
• Single-core.
• 64 KB L1 cache (32 KB L1 instruction cache; 32 KB L1 write-back data cache).
• On-die 1 MB L2 cache. The L2 cache runs at the core processor speed. It is 8-way set associative
using a 64 byte cache line.
• No L3 cache.
• 533, 667, or 800 MHz system bus which transfers data four times per bus clock (4X) with a
double-clocked address bus (2X). The system bus has a 64-bit data path.
• Intel 64 Technology support providing 64-bit operating systems and application support.
• Execute Disable Bit support.
• No support for Intel Virtualization Technology.
• No Hyper-Threading Technology support.
• Four total execution units:
– 1 integer units [often called Arithmetic Logic Units (ALU)]
– 1 floating point unit
– 1 load unit
– 1 store unit
• 5xx: uses Socket P and a Micro Flip-Chip Pin Grid Array (Micro-FCPGA) package requiring an
mPGA779M socket
• 7xx: uses Socket P and a Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package
Main memory
533 MHz
64-bit
Micro Flip-Chip Pin
Grid Array or
1 MB L2 cache
Celeron
530, 540, 550, 560, 570, 575, 585
(Merom)
Standard Voltage
1.73, 1.86, 2.00, 2.13, 2.16, 2.26 GHz
Single-core
1MB L2 cache
533 or 667 MHz system bus
No Virtualization Technology
Intel 64 and Execute Disable Bit
Intel Celeron M Processors
June 2007 and after
are used in select Lenovo
ThinkPad notebooks.
Celeron
723
(Penryn)
Ultra Low Voltage
1.20 GHz
Single-core
1MB L2 cache
800 MHz system bus
No Virtualization Technology
Intel 64 and Execute Disable Bit
Intel Celeron M Processors
August 2008
are used in select Lenovo
ThinkPad notebooks.
Features
Key features of the Intel Pentium Dual-Core notebook processor includes the following:
• Core micro-architecture.
• 0.065 micron technology (or 65 nanometers).
• Dual-core processing using two independent cores in one physical package that run at the same
frequency.
• 64 KB L1 cache per core (32 KB L1 instruction cache per core; 32 KB L1 write-back data cache
per core).
• Shared on-die 1 MB L2 cache called Intel Advanced Smart Cache. The L2 cache runs at the core
processor speed. It is 8-way set associative using a 64 byte cache line. Intel Advanced Smart
Cache enables the active execution core to access the full L2 cache when the other execution core
is idle.
• No L3 cache.
• 533 MHz system bus which transfers data four times per bus clock (4X) with a double-clocked
address bus (2X). The system bus has a 64-bit data path.
• Intel Wide Dynamic Execution improves execution speed and efficiency with each core
completing up to four full instructions simultaneously with a 14-stage pipeline. The Core 2 Duo
supports micro-op fusion when an x86 instruction is decoded into micro-ops and two adjacent,
dependent micro-ops combine into a single micro-op and execute in a single cycle. A new feature
is "Macro-op fusion" which means certain x86 instructions may also be paired into a single
instruction, then executed in a single cycle. In certain cases, five instructions can be read from the
instruction queue, then executed as if only four instructions were issued.
• Intel Smart Memory Access optimizes the use of the data bandwidth from the memory subsystem
to accelerate out-of-order execution.
• Intel 64 Technology support providing 64-bit operating systems and application support.
Core1 Core
2
Bus
L2 Cache
System Bus
ROM
Decode Decode
Rename/Alloc Rename/Alloc
Schedulers Schedulers
FPU ALU ALU Load Store Store Load ALU ALU FPU
Pentium Dual-Core
T2310, T2330, T2370, T2390
(Merom)
1.46, 1.60, 1.73, 1.86 GHz
Dual-core
1 MB Shared L2 cache
533 MHz system bus
No Virtualization Technology
Intel 64 and Execute Disable Bit
July 2007 and after
© 2008 Lenovo
Execution Execution
Core Core
L1 Cache L1 Cache
L2 Cache Control
L2 Cache
Processor Structure of
Intel Pentium Dual-Core Processor
© 2008 Lenovo
© 2008 Lenovo
Features
Key features of the Intel Core 2 Duo mobile processor includes the following:
• Core micro-architecture.
• 65 nanometers (Merom) or 45 nanometers (Penryn) process technology
• Dual-core processing using two independent cores in one physical package that run at the same
frequency.
• 64 KB L1 cache per core (32 KB L1 instruction cache per core; 32 KB L1 write-back data cache
per core).
• Shared on-die 2 MB, 3 MB, 4 MB, or 6 MB L2 cache called Intel Advanced Smart Cache. The
L2 cache runs at the core processor speed. It is 8-way set associative using a 64 byte cache line.
Intel Advanced Smart Cache enables the active execution core to access the full L2 cache when
the other execution core is idle.
• No L3 cache.
• 533, 667, 800, or 1066 MHz system bus which transfers data four times per bus clock (4X) with a
double-clocked address bus (2X). The system bus has a 64-bit data path.
• Intel Wide Dynamic Execution improves execution speed and efficiency with each core
completing up to four full instructions simultaneously with a 14-stage pipeline. The Core 2 Duo
supports micro-op fusion when an x86 instruction is decoded into micro-ops and two adjacent,
dependent micro-ops combine into a single micro-op and execute in a single cycle. A new feature
is "Macro-op fusion“ which means certain x86 instructions may also be paired into a single
instruction, then executed in a single cycle. In certain cases, five instructions can be read from the
instruction queue, then execute as if only four instructions were issued.
• Intel Smart Memory Access optimizes the use of the data bandwidth from the memory subsystem
to accelerate out-of-order execution.
• Intel 64 Technology support providing 64-bit operating systems and application support.
Core1 Core
2
Bus
L2 Cache
System Bus
ROM
Decode Decode
Rename/Alloc Rename/Alloc
Schedulers Schedulers
FPU ALU ALU Load Store Store Load ALU ALU FPU
Intel Core 2 Duo mobile processors include these features that are not found in the desktop
processor:
• Intel Dynamic Power Coordination – Coordinates Enhanced Intel SpeedStep Technology and idle
power-management state (C-states) transitions independently per core to help save power.
• Intel Dynamic Bus Parking – Enables platform power savings and improved battery life by
allowing the chipset to power down with the processor in low-frequency mode.
• Enhanced Intel Deeper Sleep with Dynamic Cache Sizing – Saves power by flushing cache data
to system memory during periods of inactivity to lower CPU voltage.
• (Some) Intel Dynamic Acceleration which allows one core to deliver extra performance when
other core is idle.
Socket P versions have this feature:
• Dynamic Front Side Bus Frequency Switching – Changes the bus clock frequency, allowing a
reduction in core voltage enabling a lower power active state called super LFM. This allows the
bus to run at full 800 MHz or at 50% of its frequency of 400 MHz.
Penryn-based processors include these features:
• Intel HD Boost which is Streaming SIMD Extensions 4 (SSE4) and faster Super Shuffle Engine.
• Intel Deep Power Down Technology which is a low-power state that allows both cores and L2
cache to be powered down when the processor is idle.
Thermal Control
Thermal Control
Arch State Arch State
L1 Caches L1 Caches
The following table shows some key differences between the mobile-based Core Duo Processor
and the Core 2 Duo processor.
533 or 667 MHz system bus 533, 667, or 800 MHz system bus
Core 2 Duo
Core 2 Duo Core 2 Duo Core 2 Duo
T5200, T5300,
U7500, U7600, U7700 L7200, L7400 T7200, T7400, T7600
T5500, T5600
(Merom) (Merom) (Merom)
(Merom)
1.06, 1.20, 1.33 GHz 1.33, 1.5 GHz 1.60, 1.66, 1.73, 1.83 GHz 2.00, 2.16, 2.33 GHz
Ultra Low voltage 10W Low voltage 17W Standard voltage 35W Standard voltage 35W
Dual-core Dual-core Dual-core Dual-core
2 MB Shared L2 cache 4 MB Shared L2 cache 2 MB Shared L2 cache 4 MB Shared L2 cache
533 MHz bus 667 MHz bus 533 or 667 MHz bus 667 MHz bus
Virtualization Virtualization Virtualization
(Only T5600) VT
Technology Technology Technology
Intel 64 Technology Intel 64 Technology Intel 64 Technology Intel 64 Technology
April 2007 and after January 2007 July 2006 and after July 2006
© 2008 Lenovo
© 2008 Lenovo
• Mobile Intel 965 Express family (GM965, PM965) and Mobile Intel 4 Series
chipset support
• Socket P support
© 2008 Lenovo
© 2008 Lenovo
Core 2 Quad
Q9100
2.26 GHz
Standard Voltage
Quad-core
12 MB L2 cache
1066 MHz bus
HD Boost
August 2008
© 2008 Lenovo
© 2008 Lenovo
© 2008 Lenovo
Summary:
Processor Architecture
© 2008 Lenovo
Semiconductor Industry Association’s (SIA) road map projects that chips will continue increasing in speed,
density, and power dissipation along their historic paths, aided by shrinking features.
Review Quiz
Objective 1
2. Why does a processor have a slower system bus speed than internal core speed?
a. The slower system bus speed is utilized by the math coprocessor.
b. The L1 cache gets a higher hit ratio with the slower system bus speed.
c. The execution units vary between the two speeds to conserve power.
d. Engineering design costs are reduced with a slower external system bus speed.
4. What feature in Intel processors helps protect memory data areas from malicious software
execution?
a. Intel 64 Technology
b. Execute Disable Bit
c. Renaming registers
d. Dual core
5. What are instruction set extensions to IA-32 to allow Intel processors to run 64-bit operating
systems and applications?
a. XA-32
b. Intel 64 Technology
c. Execute Disable Bit
d. Land Grid Array
7. What technology allows a single system to run multiple operating systems in independent
partitions?
a. Execute Disable Bit
b. Intel 64 Technology
c. Dual-core processing
d. Virtualization
Objective 2
8. Desktop processors may implement all of the following packaging except which one?
a. Pin Grid Array (PGA)
b. Voltage Regulator Module (VRM)
c. Flip-Chip PGA
d. Land Grid Array
Objective 3
11. Which Intel processor with four cores supports Virtualization Technology, Intel 64 Technology,
and 8 MB L2 cache?
a. Core Processor
b. Core 2 Duo Processor
c. Core 2 Quad Processor
d. Core 4 Processor
Objective 4
12. How many cores are included in the Intel Core 2 Solo processor?
a. None
b. One
c. Two
d. Four
13. What is an important difference between earlier versions and later versions of the Intel Core 2
Duo Mobile Processor?
a. Earlier versions use Socket M while newer versions use Socket P for 800 MHz bus support
b. Later versions support Intel 64 Technology
c. Earlier versions support Intel Centrino Pro processor technology
d. There is no difference
Answer Key
1. A
2. D
3. B
4. B
5. B
6. C
7. D
8. B
9. D
10. B
11. C
12. B
13. A
PC Architecture (TXW102)
Topic 3:
Memory Architecture
© 2008 Lenovo
Objectives:
Memory Architecture
© 2008 Lenovo
Processor +
L1 cache
L2 cache
PCI Express Memory and optional
x16 slot graphics controller
MCH or
PCI Express slots GMCH
host bridge Memory
Direct
Media
Interface PCIe controller
I/O PCI controller
PCIe Controller SATA controller
Hub IDE controller
(ICH)
USB controller
4 SATA disks
Super I/O USB 2.0
Firmware AC '97 codecs
hub or
Low Pin
High Definition Audio
Count interface
© 2008 Lenovo
L1 and L2 Cache
Processors (such as the Intel Core 2 Duo Processor) have caches to hold recently used data and
instructions. The caches are within the processor and are at different levels. The processor will first
look at L1 (level 1); if the information is not found, the processor will look in L2 (level 2), and so
forth. Some processors also have a third level or L3 cache. L1 and L2 cache is often referred to as
memory cache.
Dual-core processors have two cores, while quad-core processors have four cores. Each core has its
own dedicated L1 cache (so the L1 cache is not shared). For the L2 cache of dual-core or quad-core
processors, earlier implementations had each core use dedicated L2 cache while current
implementations share a single L2 cache among the cores.
Benefits of Cache
Caches reduce the number of clock cycles required for a memory access, in that caches are
implemented with fast SRAMs. Whenever the processor performs external memory read accesses,
the cache controller always pre-fetches extra bytes and loads them into the L1, L2, and L3 cache.
When the processor needs the next piece of data, it is likely that the data is already in these caches.
If so, processor performance is enhanced; if not, the penalty is minimal.
SODIMM used in
Lenovo notebooks
© 2008 Lenovo
CMOS (complementary metal oxide semiconductor) is often used to store the configuration
parameters of a system or an adapter. It requires little power but loses its contents if power is
removed. A battery is often used with CMOS so that the contents will remain once power is
removed from the system.
Memory Packaging
The following computer chips are usually implemented in various subsystems such as adapter cards
or systemboard components. Packaging for main memory is discussed later. These kinds of chips
would not be used for main memory today.
• Dual in-line package (DIP) – DIPs are traditional
"buglike" computer chip with 8, 14, 24, 40,
or more metal legs evenly divided between
right and left sides. DIPs are installed in holes
extending into the surface of a printed circuit
board. DIPs can be installed in sockets or
soldered in place.
DIP
• Single in-line package (SIP) – SIPs are a type of housing for electronic components in which
single-package arrays of computer chip logic are arranged in such a way that all connecting legs
are in a straight line.
SIP
• Zig-zag in-line package (ZIP) – ZIPs are similar to SIPs; every other pin connection is slightly
offset in a zigzag pattern.
• Single in-line memory module (SIMM) and dual in-line memory module (DIMM) – SIMMs and
DIMMs are individual logic devices installed on small circuit boards. The physical arrangement
facilitates easy installation and replacement.
• Integrated circuit (IC) – ICs are memory in a PCMCIA-similar card that conforms to JEDEC
standards.
• Small outline J-lead (SOJ) – An SOJ is a common form of surface-mount DRAM packaging that
is a rectangular package with J-shaped leads on the two longest sides.
SOJ
• Thin small outline package (TSOP) – A TSOP or TSOP2 is a DRAM packaging with gull-shaped
leads on both sides. A TSOP package is one-third the thickness of an SOJ package. TSOPs are
mounted directly on the surface of a printed circuit board and are typically used in SODIMMs
and PC Cards.
TSOP
• Fine-pitch ball grid array (FBGA) – An FBGA is a chip scale package for flash memories. It
physically encapsulates the Flash die.
FBGA
Importance of Memory
Any subsystem that needs to hold data needs memory. This table shows types of memory and their
architectures.
© 2008 Lenovo
Flash Memory
Flash memory is a form of non-volatile memory that allows electronic reads and writes. Non-
volatile means it does not lose its contents when power is turned off. Flash memory uses no moving
parts, so it is very useful for data storage; however, it is very expensive compared to disk-based
storage. With no moving parts, flash memory can handle vibration and dropping with no damage.
Flash memory is also very small and thin compared to disk-based storage.
Flash memory often is used to store BIOS on systemboards and for firmware on adapters. It is also
used for removable or integrated storage in digital cameras and handheld devices. Flash memory
gets its name because the microchip is organized so that a section of memory cells are erased in a
single action or "flash."
NOR NAND
Capacity 1 MB-32 MB 16 MB-1 GB
XIP capabilities Yes None
(code execution)
SD Memory Card
• USB memory keys are flash memory that plug into a USB connector. They are an ideal
replacement for a diskette and are recognized as a removable drive under Windows.
Lenovo USB 2.0 Memory Key Memory Key in Lenovo ThinkPad notebook
© 2008 Lenovo
The 2 GB Intel Turbo Memory introduced in 2008 allocates space as follows. These splits are
defined in firmware and are not customer configurable.
• 1408 MB for ReadyBoost
• 640 MB for ReadyDrive
The 2GB Intel Turbo Memory supports user application pinning if the hardware vendor supports
this. This features allows a user to load a application into the Turbo Memory to speed its
performance. If user pinning is used, it uses the space normally allocated to ReadyBoost. It is also
RAID compatible.
Performance Improvements
The 1 GB Intel Turbo Memory provides significant performance benefits:
• Performance benefit of +45%
• Performance benefit of +40% with standard 7200 rpm HDD + 1 GB Turbo Memory
• Up to 23% faster boot up time
Memory Packaging:
DIMMs
• Main memory is implemented with DIMM packaging.
- Dual in-line memory module (DIMM)
• Independent signals used on each side
• 64-bit data path
• Lenovo desktops
- 240 pins (DDR2 or DDR3)
• Lenovo notebooks use smaller SODIMMs (Small Outline DIMMs)
- 200 pins (DDR2) or 204 pins (DDR3)
DIMM SODIMM
(for desktops) (for notebooks)
© 2008 Lenovo
A DIMM has buffers for critical signals in the module that provide faster memory access and better
signal quality. Buffers on the module reduce the need for buffers on the systemboard, so the cost of
buffers is incremental as memory is added. Maximum memory efficiency is obtained by adding
memory buffers on the systemboard. Most DIMMs (except the 168-pin DIMMs) have memory
buffers. The eight-byte DIMMs can be parity, nonparity, or ECC and can support 3.3-volt
technology and 64 Mb and 256 Mb DRAMs.
The 72-pin older SIMM (single in-line memory module) and the DIMM are incompatible; they will
not fit in each other's socket or connector.
The DIMMs that are used on Lenovo notebooks are known as JEDEC SODIMMs (“SO” stands for
small outline).
While a DIMM typically has 240 pins, 64 pins are used for data, 8 may be used for ECC
information, about 36 are used for addressing, and the remainder are used for groundings and other
signal functions.
DIMM ranking
The number of ranks on any DIMM is the number of independent sets of DRAMs that can be
accessed simultaneously for the full data bit-width of the DIMM to be driven on the bus. The
physical layout of the DRAM chips on the DIMM itself does not necessarily relate to the number of
ranks. Sometimes the layout of all DRAM on one side of the DIMM compared to both sides is
referred to as "single-sided" versus "double-sided“, but these terms are misleading because the
terms do not necessarily relate to how the DIMMs are logically organized or accessed.
On a 64-bit (non-ECC) DIMM made with two ranks, there would be two sets of DRAM that could
be accessed at different times. Only one of the ranks can be accessed at a time, since the DRAM
data bits are tied together for two loads on the DIMM. Ranks are accessed through chip selects
(CS). Thus for a two rank module, the two DRAMs with data bits tied together may be accessed by
a CS per DRAM (e.g., CS0 goes to one DRAM chip and CS1 goes to the other). DIMMs are
currently being commonly manufactured with up to four ranks per module.
A rank of memory is the collection of DRAMs connected to a chip select signal from the memory
controller, abbreviated CS. Older controllers only provided two CS signals for every memory slot
and a maximum of two memory slots, thereby limiting capacity per memory channel to 4 ranks.
Consumer DIMM vendors have recently begun to distinguish between single- and dual-ranked
DIMMs. JEDEC decided that the terms "dual-sided," "double-sided," or "dual-banked" were not
correct when applied to registered DIMMs.
The term "rank" evolved from the need to distinguish the number of memory banks on a module as
opposed to the number of memory banks on a component. So, "rank" is used when referring to
modules, and "bank" is used when referring to components. The most commonly used modules
have either a single-rank of memory or a double-rank of memory.
Many factors influence the use of single-rank or double-rank modules. These include available
component densities and pricing, system memory requirements, the number of slots on a board, and
memory controller specifications. In the case of a 1 GB DIMM, it can be built as single-rank or
double-rank depending on the components used.
2 GB/rank
Chip Selects
2 ranks/slot
Address x 4 slots
16 GB capacity
Data
2 GB/rank
Chip Selects
4 ranks/slot
Address x 4 slots
32 GB capacity
Data
Memory Terminology:
Dynamic Random Access Memory (DRAM)
© 2008 Lenovo
DRAM
DRAM is memory that must be refreshed constantly. This requirement imposes delays between
accesses so that the charges can build up and stabilize.
Refreshing is continuously charging a device that cannot hold its content without an electrical
charge. Memory is refreshed with an electrical current.
An important performance measurement for memory is access time, which is the amount of time
that passes between the instant the processor issues an instruction to the memory to read data from
an address and the moment it receives it.
The address is provided in two successive addresses – RAS and CAS – reducing pin count and
complexity of the memory packaging in exchange for a trivial increase in controller cost.
The CAS is a control pin on a DRAM used to latch and activate a column address. The column
selected on a DRAM is determined by the data present at the address pins when CAS becomes
active.
The RAS is a control pin on a DRAM used to latch and activate a row address. The row selected on
a DRAM is determined by the data present at the address pins when RAS becomes active.
The following memory chips are addressed as follows:
x1 x4 x8
Memory Chip
Rows/Columns Rows/Columns Rows/Columns
1 Mb 10/10 9/9 NA
4 Mb 11/11 10/10 10/9
16 Mb 12/12 12/10 or 11/11 12/9 or 11/10
64 Mb 13/13 13/11 or 12/12 13/10 or 12/11
256 Mb NA 14/12 or 13/13 14/11 or 13/12
x16 x32
Memory Chip
Rows/Columns Rows/Columns
1 Mb NA NA
4 Mb 9/9 NA
16 Mb 12/8 or 10/10 10/9
64 Mb 13/9 or 12/10 11/10
256 Mb 14/10 or 13/11 or 12/12 14/9
DRAM Chips
A DRAM chip contains a matrix of memory cells, each cell holding a single bit. A cell is made up
of a capacitor (a tiny device that can hold an electrical charge) and a transistor, which acts like a
switch. To read a cell, the transistor is activated, and triggers the capacitor. A discharge of current
signifies a 1, and the capacitor must be recharged, and no discharge represents a 0.
To select a bit to read, a computer uses a grid of wires connected to the memory cell matrix. First, a
small voltage is applied to the selected row, thus selecting all bits in that row. Next, the appropriate
column wire is triggered. The combination is enough to activate the transistor at that row and
column. This process takes time, however, and much of the latency involved in memory accesses
comes from the time it takes to select the desired bits.
Memory Timing
Memory is organized on a chip in rows and columns, and it is accessed by repeated pulses of
electricity (called strobing) to reach each location. When memory is accessed, each strobing
cycle takes a fixed amount of time consisting of these four elements:
• tCL – Column address strobe (CAS) latency; the number of clock cycles required to access
a specific column of data. (The initial t refers to time.)
• tRCD – Row address strobe (RAS)-to-CAS delay; the number of clock cycles needed
between a row address strobe and a column address strobe.
• tRP – RAS precharge; the number of clock cycles needed to close one row of memory and
open another.
• tRAS – The number of clock cycles needed to access a specific row of data in RAM.
If a DRAM label says DDR2-800 5-5-5-15, here is the breakdown:
• 800 is the effective clock speed in megahertz. It is the actual clock speed times data per
clock cycle (200 MHz [for DDR2-800] x 4 [4 samples per clock cycle for DDR2]).
• "5-5-5-15" refers to a tCL of 5, tRCD of 5, tRP of 5, and tRAS of 15.
Latency is the delay that occurs during memory access. Since latency is measured in clock
cycles, a small number is better because less time is required for memory accesses. The time is
measured in nanoseconds (ns) with a typical system doing millions of memory accesses each
second. Memory speed and latency move in opposite directions (as memory speed gets faster,
then latency gets slower). For example, the same DDR2-667 memory module can run at 333
MHz with a 5-5-5-13 latency or at DDR2-533 speed at 266 MHz with a 4-4-4-11 latency. Since
higher clock frequencies represent smaller time intervals, the total time is practically the same
for both these settings.
Some memory vendors offer premium memory which runs at high clock speeds and lower
latencies. Specialized applications are sensitive to memory performance, so premium memory
results in better performance for games, media transcoding, and 3D rendering because they are
all sensitive to memory latencies. Mainstream applications like Web browsing, office
applications, and streaming media are less sensitive.
Types of DRAM:
Used for Main Memory
• DDR2
- Second generation of DDR
- Higher bandwidth than DDR1
- Introduced in 2004 for desktops and in
2005 for notebooks
• DDR3
- Third generation of DDR
- Higher bandwidth than DDR2
- Lower power
- Introduced in 2007 for desktops and in
2008 for notebooks
© 2008 Lenovo
Types of DRAM
Main memory in computers was implemented with different types of memory as follows:
• Prior to 1995: conventional DRAM
• 1996: Fast Page Mode (FPM)
• 1997: Extended Data Out (EDO)
• 1998-1999: Synchronous DRAM (SDRAM)
• 2000-2001: Rambus RDRAM and SDRAM
• 2002: SDRAM, DDR1 (or DDR-SDRAM), and Rambus RDRAM
• 2003: DDR1
• 2004-2005: DDR1 and DDR2
• 2006-2008: DDR2
• 2007-present: DDR3
These memory types can also be implemented on any device or subsystem that has memory, such
as a graphics controller, disk cache, buffer, adapter memory, etc.
Odd Even
Clock
Data 0 1 2 3 4 5
Data packet
Double data rate (DDR) synchronous DRAM (SDRAM) (also called double-speed DRAM or
DDR-1) provides additional throughput and features over standard SDRAM. DDR1 was introduced
in systems after chipset support in various memory controllers became available in late 2001.
DDR1 allows data to latch on both the rising and falling edge of the clock. Thus, for the same
memory speed as SDRAM, and with no increase in clock frequency, throughput can be doubled.
With the original SDRAM, a 100 MHz SDRAM chip handles a single memory operation per clock
cycle; the original SDRAM’s data rate, then, is effectively 100 MHz x 1, or 100 MHz. A PC133
SDRAM chip has a data rate of 133 MHz. PC100 and PC133 are in effect single data rate (SDR)
SDRAM. DDR memory chips can perform two operations during a single clock cycle. A 100 MHz
DDR memory chip’s data rate is thus 100 MHz x 2 or 200 MHz, a 133 MHz DDR memory chip
has a data rate of 133 MHz x 2 or 266 MHz, and so forth.
The DDR1 memory bus runs at memory-bus clock rate of 100 MHz for PC1600, 133 MHz for
PC2100, 166 MHz for PC2700, and 200 MHz for PC3200. However each DDR1 memory module
and memory chip runs at an effective (data) rate of 200 MHz, 266 MHz, 333 MHz, or 400 MHz.
The computer industry has adopted a practical convention of referring to the data rate as the DDR1
DIMM speed. So, PC1600 DIMMs are said to run at 200 MHz, PC2100 at 266 MHz, PC2700
DIMMs at 333 MHz, and PC3200 DIMMs at 400 MHz.
DDR-SDRAM (DDR1) is architecturally similar to SDRAM but has two main differences:
• DDR1 has more advanced synchronization circuitry than SDRAM.
• DDR1 uses a delay-locked loop (DLL) to provide a DataStrobe signal as data becomes valid on
the SDRAM pins. The controller uses the DataStrobe signal (one for every 16 outputs) to locate
data more accurately and resynchronize incoming data from different DIMMs.
The specifications for DDR1 memory modules are developed and approved by JEDEC. JEDEC is
the semiconductor standardization body of the Electronic Industries Alliance (EIA). About 350
member companies representing every segment of the industry actively participate to develop
standards to meet the industry needs.
Types of DRAM:
DDR2
© 2008 Lenovo
DDR2
The second generation of double data rate memory for desktop and notebook systems is Double
Data Rate 2 (DDR2). DDR2 is a type of synchronous DRAM that provides higher performance and
lower power consumption compared to DDR-SDRAM or DDR1. The specification for DDR2 was
formally released by JEDEC in late 2003 at www.jedec.org.
DDR2 supports four speeds of 400, 533, 667, and 800 MHz (each of these speeds is twice the
external clock frequency). Data is latched on both the rising and falling edge of the clock so
throughput is effectively doubled at the base clock rate.
DDR2 requires a memory controller in a chipset for support. Various chipsets support DDR2 such
as the Intel Grantsdale 915 (for desktops) and Intel Alviso 915 (for notebooks). A system cannot
support a mixed DDR1 and the newer DDR2 simultaneously; so a system will support all DDR1 or
all DDR2.
Systems with DDR2 memory controllers usually support any speed of DDR2 memory. If you mix
different speed DDR2 DIMMs in a system, the system will operate at the slowest DIMM speed; if
the memory controller does not support faster DIMM speeds, the system will operate at the slower
memory controller speed. Whereas systems with DDR1 memory controllers did not support any
speed of DDR1 memory, systems with DDR2 memory controllers offer more flexibility and
compatibility.
Types of DRAM:
DDR2 Benefits
Bandwidth GB/s
Clock 6.4 DDR400
5.3 DDR333
Data 0 1 2 3 4 5
4.2 DDR266
Data packet
2002 2003 2004 2005
© 2008 Lenovo
DDR2 Benefits
DDR2 operates at 1.8 volts compared to 2.5 volts for DDR1. This lower power consumption at
comparable operation frequencies gives headroom for operation at higher frequencies, and extends
battery life in mobile applications.
DDR2 used as main memory for desktops is implemented with 240-pin DIMMs; a desktop with
DDR2 support will not support the older DDR1 184-pin DIMM. DDR2 used as main memory for
notebooks will use a 200-pin SODIMM; while older notebook DDR1 also uses a 200-pin
SODIMM, a DDR2-based notebook only supports DDR2 SODIMMs.
DDR2 is available in Ball Grid Array (BGA) packaging including Fine-pitch Ball Grid Array
(FBGA). BGA packaging allows DDR2 to support higher operation frequencies compared to the
Thin Small Outline Package (TSOP) packaging used with DDR1.
4-bit Prefetch
DDR2 increases the prefetch (from 2 bits with DDR1 to 4 bits with DDR2) to improve
performance. DDR2 SDRAM achieves high-speed operation by 4-bit prefetch architecture. This 4-
bit prefetch delivers twice the external bandwidth of DDR1 for the same internal core frequency. In
4-bit prefetch architecture, DDR2 can read/write four times the amount of data on the external bus
from/to the memory cell array for every clock; it can deliver four times faster than the internal core
frequency.
• External clock frequency = two times faster than internal core operating frequency
• Data bus speed throughput = two times faster than external clock frequency
A comparison between SDR SDRAM, DDR1 SDRAM, and DDR2 SDRAM with a DRAM core
operating frequency of 100 MHz is shown below.
Internal bus core frequency 100 MHz 100 MHz 100 MHz
Data bus speed throughput 100 Mb/s 200 Mb/s 400 Mb/s
DRAM External
core frequency clock frequency Data bus speed
100 MHz 100 MHz 100 Mb/s
Memory
SDR I/O
Cell
SDRAM Buffer
Array
DRAM External
core frequency clock frequency Data bus speed
100 MHz 100 MHz 200 Mb/s
Memory
DDR I/O
Cell
SDRAM Buffer
Array
(DDR1)
2-bit prefetch
DRAM External
core frequency clock frequency Data bus speed
100 MHz 200 MHz 400 Mb/s
Memory
DDR2 I/O
Cell
SDRAM Buffer
Array
4-bit prefetch
200 MHz x 4 = 800 MHz system bus 200 MHz x 4 = 800 MHz system bus
Half the
Memory core Memory core speed of the
200 MHz 100 MHz memory core
Types of DRAM:
DDR2 Speeds
Processor
© 2008 Lenovo
DDR2 Speeds
A DDR2 module is named after its peak bandwidth, which is the maximum amount of data that can
be delivered per second:
• A 400 MHz DDR2 DIMM is called a PC2-3200 DIMM, with 3.2 GB/s bandwidth
(8 bytes [64-bit data path] x 200 MHz x 2 [DDR] = 3200 MB/s or 3.2 GB/s).
• A 533 MHz DDR2 DIMM is called a PC2-4200 DIMM with 4.2 GB/s bandwidth
(8 bytes [64-bit data path] x 266 MHz x 2 [DDR] = 4200 MB/s or 4.2 GB/s).
• A 667 MHz DDR2 DIMM is called a PC2-5300 DIMM with 5.3 GB/s bandwidth
(8 bytes [64-bit data path] x 333 MHz x 2 [DDR] = 5300 MB/s or 5.3 GB/s).
• An 800 MHz DDR2 DIMM is called a PC2-6400 DIMM with 6.4 GB/s bandwidth
(8 bytes [64-bit data path] x 400 x 2 [DDR] = 6400 MB/s or 6.4 GB/s).
Types of DRAM:
DDR3
© 2008 Lenovo
DDR3
The third generation of double data rate memory for desktop and notebook systems is Double Data
Rate 3 (DDR3). DDR3 is a type of synchronous DRAM that provides higher performance and
lower power consumption compared to DDR1 or DDR2. The specification for DDR3 was formally
released by the JEDEC Solid State Technology Association in 2007 at www.jedec.org.
DDR3 supports clock frequencies of 400, 533, 667, and 800. Data is latched on both the rising and
falling edge of the clock so throughput is effectively doubled at the base clock rate.
DDR3 requires a memory controller in a chipset for support. Various chipsets support DDR3 such
as some Intel desktop chipsets (Intel 3 and 4 Series chipsets). Notebook chipset support is included
in the GM45, GM47, and PM45 with code-name Cantiga. A system cannot support a mixed DDR2
and DDR3 simultaneously; so a system will support all DDR2 or all DDR3. The memory DIMMs
have different keys to prevent inserting in the incorrect slot.
Systems with DDR3 memory controllers usually support any speed of DDR3 memory. If you mix
different speed DDR3 DIMMs in a system, the system will operate at the slowest DIMM speed; if
the memory controller does not support faster DIMM speeds, the system will operate at the slower
memory controller speed. Similar to DDR2 systems, systems with DDR3 memory controllers offer
excellent flexibility and compatibility.
Types of DRAM:
DDR3 Benefits
• Increased bandwidth
- Higher bandwidth due to
increased clock frequency
- Doubles the prefetch
(from 4 to 8 bits)
• Lower power consumption
- Operates at a lower - DDR3 DIMM (top)
voltage (1.5 volts) than - DDR2 DIMM (bottom)
DDR2 (1.8 volts) - Different key notch prevents
installing in wrong memory slot
• Application performance similar
to DDR2
- Higher DDR3 frequencies offset
by slower latencies
© 2008 Lenovo
DDR3 Benefits
DDR3 operates at 1.5 volts compared to 1.8 volts for DDR2. This lower power consumption at
comparable operation frequencies gives headroom for operation at higher frequencies, and extends
battery life in mobile applications.
DDR3 used as main memory for desktops is implemented with 240-pin DIMMs. A notch 48 pins
from the left of one side separates the DIMM so that DDR3 is not accidentally placed in DDR1 or
DDR2 memory slots.
The Ball Grid Array (BGA) chip packaging in DDR3 has more contact pins than DDR2. This
simplifies the chip mounting procedure and increases mechanical robustness of the ready solutions
as well as improves signal quality at high frequencies.
DDR3 SDRAM signal protocol is improved over DDR2 as the memory bus frequency increased
significantly. DDR3 uses fly-by topology with on-module signal termination to transfer addresses,
management, and stabilization commands. This means that the signals are sent to all chips of the
memory modules one by one (not altogether at the same time).
The data reading/writing algorithms from DDR2 have also changed. The DDR3 controller has to
successfully recognize and process time shifts on data receipt from the chips generated by fly-by
architecture used for commands transfer. This technique is known as read/write leveling.
Leveling No No Yes
5.25"
2.48" 2.17"
5.25"
1.85" 2.80"
Types of DRAM:
DDR3 Bandwidth
I/O buffers
Memory I/O buffers Memory
core 4x rate core 8x rate
4n bits 8n bits
Clock speed 400, 533, 667, 800 MHz Clock speed 800, 1066, 1333, 1600 MHz
3.2, 4.2, 5.3, 6.4 GB/s 6.4, 8.5, 10.7, 12.8 GB/s
5-5-5-15 ns latency 7-7-7-15 ns latency
© 2008 Lenovo
DDR3 Bandwidth
While DDR2 uses a 4-bit prefetch, DDR3 uses an 8-bit prefetch also known as 8n-prefetch. This
means DDR3 doubles the internal bus width between the actual DRAM core and the input/output
buffer. The increase in the data transfer rate provided by DDR3 does not require faster operation of
the memory core. Only external buffers work faster. The core frequency of the memory chips are 8
times lower than that of the external memory bus and DDR3 buffers.
Therefore DDR3 can almost immediately hit higher frequencies than DDR2 without big
improvements of the semiconductor manufacturing process. However, the disadvantage is it
increases not only memory bandwidth, but also memory latency. So DDR3 will not provide
significantly better application performance than DDR2 even if it operates at higher frequencies
than DDR2.
DRAM External
core frequency clock frequency Data bus speed
100 MHz 100 MHz 100 Mb/s
Memory
SDR I/O
Cell
SDRAM Buffer
Array
DRAM External
core frequency clock frequency Data bus speed
100 MHz 100 MHz 200 Mb/s
Memory
DDR I/O
Cell
SDRAM Buffer
Array
(DDR1)
2-bit prefetch
DRAM External
core frequency clock frequency Data bus speed
100 MHz 200 MHz 400 Mb/s
Memory
DDR2 I/O
Cell
SDRAM Buffer
Array
4-bit prefetch
DDR2 clocked the memory bus at twice the memory cell speed to trade off an increase in memory
cell latency against an overall increase in memory throughput.
DRAM External
core frequency clock frequency Data bus speed
100 MHz 400 MHz 800 Mb/s
Memory
DDR3 I/O
Cell
SDRAM Buffer
Array
8-bit prefetch
DDR3 clocked the memory bus at four times the memory cell speed to trade off an increase in
memory cell latency against an overall increase in memory throughput.
Types of DRAM:
DDR3 Speeds
Marketing Naming Single Channel
Data Rate
Name Convention Bandwidth
800 MT/s
DDR3-800 PC3-6400 6.4 GB/s
(400 MHz x 2)
1066 MT/s
DDR3-1066 PC3-8500 8.4 GB/s
(533 MHz x 2)
1333 MT/s
DDR3-1333 PC3-10600 10.6 GB/s
(667 MHz x 2)
1600 MT/s
DDR3-1600 PC3-12800 12.8 GB/s
(800 MHz x 2)
Core 2 Duo
DDR3 DIMM (for desktops)
DDR3
(G)MCH
G35 6.4 to 12.8 GB/s
400/533/667/800 MHz
DDR3 Speeds
A DDR3 module is named after its peak bandwidth, which is the maximum amount of data that can
be delivered per second:
• A 400 MHz DDR3 DIMM is called a PC3-6400 DIMM, with 6.4 GB/s bandwidth
(8 bytes [64-bit data path] x 400 MHz x 2 [DDR] = 6400 MB/s or 6.4 GB/s).
• A 533 MHz DDR3 DIMM is called a PC3-8500 DIMM with 8.4 GB/s bandwidth
(8 bytes [64-bit data path] x 533 MHz x 2 [DDR] = 8400 MB/s or 8.4 GB/s).
• A 667 MHz DDR3 DIMM is called a PC3-10600 DIMM with 10.6 GB/s bandwidth
(8 bytes [64-bit data path] x 667 MHz x 2 [DDR] = 10667 MB/s or 10.6 GB/s).
• An 800 MHz DDR3 DIMM is called a PC3-12800 DIMM with 12.8 GB/s bandwidth
(8 bytes [64-bit data path] x 800 x 2 [DDR] = 12800 MB/s or 12.8 GB/s).
DDR3 DIMMs
These types of DDR3 DIMMs are available:
• 240-pin unbuffered DIMMs for desktops
• 240-pin registered (fully buffered) DIMMs for desktops
• 204-pin SODIMMs for notebooks
• Fully Buffered DIMM for servers
• Very Low Profile DIMM for networking
Types of DRAM:
DDR Channels
• Single-channel
- One path to memory for 64-bit data transfer
• Dual-channel
- Two paths to memory operate in lock step for 128-bit data transfer
- Double the bandwidth of single channel
- Supported in most of the latest Intel desktop and mobile chipsets
- Called Intel Flex Memory Technology with Intel chipsets
6.4 GB/s
Memory PC3-6400
Controller 12.8 GB/s bandwidth
6.4 GB/s
Hub PC3-6400
© 2008 Lenovo
DDR Channels
DDR1, DDR2, and DDR3 memory are implemented with a single-channel or dual-channels.
The memory controller of the chipset determines the support for the number of channels.
A single channel means there is a single link to the memory DIMM(s). This provides a 64-bit
data path.
A system with dual-channels means there is two independent links to the memory DIMMs.
Both channels can operate in lock step to transfer data simultaneously, so with each bus at 64-
bits wide, this configuration can provide a 128-bit data transfer with twice the bandwidth of a
single channel.
Single-Channel
The system will enter single-channel mode when only one channel of memory is routed and
populated on the systemboard. It will also enter single-channel mode if two channels of memory
are routed, but only one channel is populated. In this configuration, all memory cycles are directed
to a single channel.
D D D D
I I Channel A I I Channel A
M M Total M M Total
M M 1 GB M M 0 GB
Dual-Channel Asymmetric
This mode is entered when both memory channels are routed and populated with different amounts
of total memory. This configuration allows addresses to be accessed in series across the channels
starting in channel A until the end of its highest rank, then continue from the bottom of channel B
to the top of the rank. Real-world applications are unlikely to make requests that alternate between
addresses that sit on opposite channels with this memory organization, so in most cases, bandwidth
will be limited to that of a single channel.
D D D D
I I Channel A I I Channel A
M M Total M M Total
M M 1 GB M M 2 GB
Intel 0 1 Intel 0 1
Express 1 GB 0 GB Express 1 GB 1 GB
Chipset Chipset
GMCH GMCH
D D D D
I I Channel B I I Channel B
M M Total M M Total
M M 512 MB M M 1 GB
0 1 0 1
0 GB 512 MB 0 GB 1 GB
Dual-Channel Symmetric
This mode allows the end user to achieve maximum performance on real applications by utilizing
the full 64-bit dual-channel memory interface in parallel across the channels with the aid of Intel
Flex Memory Technology. The key advantage this technology brings is that the end user is only
required to populate both channels with the same amount of total memory to achieve this mode.
The DRAM component technology, device width, device ranks, and page size may vary from one
channel to another.
Addresses are ping-ponged between the channels, and the switch happens after each cache line (64-
byte boundary). If two consecutive cache lines are requested, both may be retrieved simultaneously,
since they are guaranteed to be on opposite channels.
D D D D
I I Channel A I I Channel A
M M Total M M Total
M M 1 GB M M 1 GB
Intel 0 1 Intel 0 1
Express 1 GB 0 MB Express 512 MB 512 MB
Chipset Chipset
GMCH GMCH
D D D D
I I Channel B I I Channel B
M M Total M M Total
M M 1 GB M M 1 GB
0 1 0 1
0 GB 1 GB 0 GB 1 GB
Types of DRAM:
FB-DIMMs
• Fully Buffered DIMMs are a different
way to access DDR2 DRAM chips with
a new memory controller
• Serial connection to each DIMM on
the channel
• Interface at each DIMM called
Advanced Memory Buffer Fully Buffered DIMM
FB-DIMM
memory
controller
Fully Buffered Memory DIMMs
© 2008 Lenovo
DDR2 DIMM
This serial interface results in fewer active connections to the DIMMs (approximately 69 per
channel vs. 240 for DDR2 DIMMs) and less complex wiring. Each DIMM is 240 pins. This serial
signaling is relatively similar to PCI Express. The interface between the buffer and DRAM chips is
the same as DDR2 DIMMs. The DRAM chips are also the same as DDR2 DIMMs.
Differential
Pins
Signals
Data Path to DIMMs 10 20
Data Path from DIMMs 14 28
Total High-Speed Signals 48
Power 6
Ground 12
Shared Pins (clocks, calibration, PLL power, test) ~3
Total Pins ~ 69
With this serial point-to-point connectivity, a built-in latency is associated with any memory
request. In addition, the design of FB-DIMM is such that even if the request is fulfilled by the first
DIMM nearest to the memory controller, the address request must still travel the full length of the
serial bus. As a consequence, the more DIMMs per channel, the longer the latency.
FB-DIMMs are not the next generation of DRAM. FB-DIMMs use a new way of accessing the
same DDR2 DRAMs from a new memory controller.
An FB-DIMM memory controller can support up to 6 channels with up to 8 DIMMs per channel
and single or dual-rank DIMMs. Power consumption for a FB-DIMM is 1.2 volts versus 1.8 volts
for DDR2 DIMMs. FB-DIMMs allow greater memory capacity in a system.
Standard
DDR2 interface
DRAM DRAM DRAM
between buffer
and DRAMs
DRAM DRAM DRAM
DDR3
DDR2
DDR2 400/533
FB-DIMM Performance
With a less complicated circuit board design and lower power consumption, systems can utilize
memory controllers with more channels. The use of more memory channels results in better
throughput.
The use of a serial connection adds latency to memory access, but the greater throughput offered by
FB-DIMMs results in lower average latency when under load, thereby improving performance.
Higher throughput is reached with the use of more channels. At low throughput levels, the latency
of the serial link is significant. However, because that latency remains constant regardless of the
load, FB-DIMM performance is significantly better than DDR2 as throughput increases.
Memory read latency
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Theoretical peak memory throughput (GBps)
Memory Performance:
Memory Capacity Affects Performance
© 2008 Lenovo
Memory Performance:
Windows Vista Memory Requirement
• Windows Vista Home Basic
- Requires minimum of 512 MB memory; 1 GB recommended
• Windows Vista Home Premium, Business, Ultimate
- Requires minimum of 1 GB memory; 2 GB recommended
• Windows Vista 64-bit OSes
- Recommend minimum of 4 GB memory
• SuperFetch
- Learns what applications are used most and preloads these into
memory for faster performance
• ReadyBoost
- Vista can use a USB flash memory key
as a read cache to cache memory data
© 2008 Lenovo
When the installed memory is 4 GB, it is expected that all of the 4 GB memory can be used as the
system memory. However, the actual usable memory is less than 4 GB on 32-bit operating systems
that handle up to 4 GB of memory.
Due to an architecture limitation, a number of blocks of memory space need to be allocated under 4
GB memory space: BIOS ROM space, graphics memory space, PCI and PCI Express space,
chipset memory mapped registers, and system management memory. These memory spaces do not
actually use the memory (except BIOS ROM copied to memory and graphics memory for the
integrated memory), but use the address space.
Total usable memory is 3 GB in integrated graphics mode and 2.5 GB in the discrete graphics mode
when 512 MB graphics memory is used.
Intel chipsets have a remapping capability which can push out the system memory space to over 4
GB address space taken by these devices, and this capability is useful when the operating system
can handle over 4 GB memory.
Installed Memory
4GB
Non-usable Memory
3GB
2GB
Usable Memory
1GB
Memory Map
SuperFetch
Windows SuperFetch understands which applications you use most and preloads these applications
into memory, so your system is more responsive. SuperFetch uses an intelligent prioritization
scheme that understands which applications you use most often, and can even differentiate which
applications you are likely to use at different times (for example, on the weekend versus during the
week), so that your computer is ready to do what you want it to do. Windows Vista can also
prioritize your applications over background tasks, so that when you return to your machine after
leaving it idle, it is still responsive.
ReadyBoost
An optional Windows Vista feature, ReadyBoost, is a read cache that allows Vista to cache
memory data onto flash memory (USB drive, Secure Digital Card, Compact Flash, or other
memory form factor) that will not fit into main memory. Because the flash device could be
removed at any time, unique data cannot be stored on it, and data is encrypted for security reasons.
Microsoft recommends that the USB memory key be about the same size as system memory, but
not larger than 4 GB.
Memory Errors:
Parity, Nonparity, ECC
Methods of dealing with possible memory errors:
• Parity
- Common prior to 1995; detected single bit errors
• Nonparity
- Common with notebooks and desktops today
- Memory today rarely generates errors
• Error checking and correcting (ECC)
- Detects and corrects 1-bit to 4-bit errors on the fly
- Detects 2-bit to 8-bit errors
- Implemented in server and workstation systems
- Used in Lenovo ThinkStation workstations
© 2008 Lenovo
Implementing Parity
Parity is implemented by adding an additional bit of DRAM memory for every eight bits (one byte)
of DRAM memory. For the 64-bit processors of today, an additional eight bits of memory and a
72-bit data path, increasing cost and board space (DRAM costs increase by 10 percent to 15
percent alone), is required. When the processor writes a byte of information to DRAM, the parity
logic checks for an even number of one bits in the data byte. If even, the parity logic places a zero
on the parity line going to the extra parity bit. If odd, the parity logic places a one on the parity line
going to the extra parity bit.
When the data is later read back from memory, the parity checking logic checks the nine bits of
information (per byte of data) for an even number of one bits. If it does not contain an even number
of one bits, an error has occurred, and the parity check logic then generates a parity error. Upon
detecting a parity error, the system logic generates a non-maskable interrupt (NMI) request to the
microprocessor. The microprocessor is then forced to jump to the NMI interrupt service routine
(ISR). This ISR, however, is able to do little more than determine that a parity error has occurred.
The NMI ISR reports a DRAM parity error on the screen and locks up the system, causing all the
data in the volatile system memory to be lost.
Average undetected error probability for nonparity memory:
• 32 MB of memory at 100 hours per month, one undetected error every 39 years
• 128 MB of memory at 300 hours per month, one undetected error every eight years
• 512 MB of memory at 600 hours per month, one undetected error every three years
Soft errors are temporary; a bit of data is lost, but the memory cell functions, and rewriting the data
in the cell corrects the error. Soft errors are intermittent errors that occur as a result of the passage
of ionizing radiation through the memory cells of semiconductor devices. The most common source
of this radiation is alpha particles generated as a result of the decay of thorium and uranium, which
are found in trace amounts in the packaging materials of all plastic and ceramic encapsulated
devices. Another source is cosmic radiation such as that from space. A dying star can cause cosmic
radiation projecting a shower of protons and neutrons that can eventually penetrate the atmosphere
and into memory.
A hard error is usually caused by contaminants that lodge themselves in the gate oxide of a DRAM
cell during manufacturing. The higher the altitude, the more numerous the soft errors, because there
are fewer air molecules at higher altitudes to absorb cosmic rays.
The following shows the number of parity bits and ECC bits required for a particular word size (or
data bus transfer):
Of all memory errors, single-bit errors occur 98 percent of the time, as compared to 2, 3, or 4-bit
errors. ECC memory can detect all and correct some double-bit errors The most prevalent errors are
single bit soft errors, then single bit hard errors, then multibit hard errors (fixed by Chipkill), then
multibit soft errors.
The above example shows one possible transfer scheme for a single DIMM that is enabled for
ECC. For a 64-bit write, 4 bits are written to each of 16 DRAM chips and 4 checksum bits are
written to each of 2 checksum DRAM chips.
In a single DIMM implementation, every DRAM chip contains more than one bit of a 64-bit
segment.
If only one bit is lost, the memory controller can reconstruct the lost bit by operating a reverse
checksum algorithm on the checksum data, which are physically stored on working DRAM chips.
A hamming code is a numerical calculation which uses an algorithm to convert a very large number
into a very small number. It creates a unique result for a given number of bits, which always
contains the same number of result bits. Thus, a 64-bit data segment can be protected with ECC and
the results of the calculation can be stored in just 8 check bits. For a standard 72/64 hamming code
that provides SEC/DED, anything more than a single-bit error will result in a failure of the reverse
checksum algorithm, and therefore the entire DIMM, causing a catastrophic failure of the system.
The actual order in which the data are written is determined by the memory controller and board
wiring. There are many possible permutations for where each bit could be stored. The example
above is just one possibility. It is inconsequential to the fundamental requirement for ECC
protection where the data bits are actually stored. The requirement for ECC is that, for a 64-bit data
segment, 8 additional bits of check space are required to store the checksum.
On a store, when the values for the 64 bits are known, the memory controller calculates the
checksum for the 64 bits and writes the checksum to memory alongside the data. On a fetch, the
memory controller reads back the 64 data bits along with the 8 check bits. It then recalculates the 8
check bits and compares them to the fetched check bits. The resulting comparison is known as a
syndrome and is used to determine if there are any errors. A standard 72/64 hamming code can
correct any single-bit error and detect any double-bit errors. This is known as Single Error
Correct/Double Error Detect (SEC/DED).
As with the data, the checksum is stored in blocks of four bits on two DRAM chips. Thus, no more
than 4 bits of any 64-bit data segment are ever located together, including the checksum.
Memory Cache
Processor
© 2008 Lenovo
Memory Cache
Memory cache in the processor enables it to read instructions and data faster than if the processor
had to access system memory. When instructions are first used or data is first read or written, they
are transferred to the cache from main memory. This transfer enables future accessing of the
instructions or data to occur faster. All processors today have L1 and L2 caches, and some have L3
cache.
L2 cache affects system performance. The critical issue is to have some amount of L2 cache; for
example, 256 KB is a typical and reasonable amount for most processors. As L2 cache size
increases, performance will not increase linearly. As more L2 cache is added, performance
increases less. Eventually, the overhead of a large amount of L2 cache could actually slow system
performance.
When the processor performs a memory write, several different scenarios could happen, which are
covered under Student Notes: Cache Write Policy.
L1 and L2 caches run at internal clock speed (e.g., 1.0 ns for 1 GHz processor).
Cache hit ratio does not increase proportionally with cache size.
Doubling the cache size does not double the cache hit rate.
Cache
Hit
Ratio
Performance/Capacity Relationship
1. Write-through
– Processor writes data through the cache to memory
(also writes to cache if the cache line is already there). Main
memory
• Caching effect is restricted to memory reading only.
2. Write-back
– Processor writes to cache and proceeds to the next L2 cache
instruction. The cache holds the write-back data in the
cache and later copies it to main memory (processor
idle time).
L1 cache
– Higher performance than write-through but more costly.
– Write-back has 10% faster application performance than write-through. Processor
The cache line is typically 32 to 64 bytes and involves four transfers to write (or read) the cache
line. The cache controller must be engineered so that busmasters do not read data in memory if the
data is still in the cache.
For the L1 and L2 cache:
• Write-through and write-back cache for reads
– If read miss: it reloads the new data after it gets it from the next level.
– If read hits: it reads the information from cache.
• Write-through cache for writes
– If write hit: it updates cache line and writes to memory controller.
– If write miss: does not capture; it writes to memory controller.
• Write-back cache for writes
– If write hit: it updates the cache line and returns ready to the processor and will eventually
write to memory if required.
– If write miss: it does not capture; it writes to the memory controller.
Thus, for write misses, neither type of cache captures the data; it is written to the memory
controller.
Memory
0 xx MB
• Memory is logically divided into blocks that map directly with a line-in cache (it can be stored
only in that particular line).
• If the application asks for information from two areas in the same block that compete for the
same line, the processor must thrash the cache and replace it with a new line.
– For example, if 256 KB L2 cache is used with 16 MB of main memory, about 64 blocks
compete for the same line in L2 cache because 256 KB by 64 = 16 MB.
• Direct-mapped cache is easy to design at a low cost, and it provides satisfactory DOS
performance for notebook and desktop operations systems.
Memory
0 xx MB
Cache Organization
L2 Cache
Direct Mapped
Set Associative
xx KB
0
• Each block in memory can be stored in different locations in cache.
• There are several versions of set associative cache organization:
– Two-way set associative gives each block in memory two cache line locations.
– Four-way set associative gives each block in memory four cache line locations.
– Fully associative lets each block in memory be stored anywhere in cache.
• Advantage: the most recently accessed information is usually in cache.
• Disadvantage: search is slow since the processor must search all of cache.
• It is complex to design and is higher in cost, but normally offers better performance
• The processor must now look in two, four, or all lines in L2 cache versus one line in
direct mapped.
• Multitasking operating systems alternate between multiple tasks with each task calling for a
different line in the same block.
Memory Cache:
Cache Evolution
L3
L2
L2
L1
L1
L1 cache Memory speed
Time
© 2008 Lenovo
Cache Evolution
Processor speed is evolving faster than memory speed. To avoid slow access to memory, levels of
cache should be implemented.
L1 and L2 caches are now standard in processors. The wider the disparity between the processor
and memory speed, the more levels of cache that are needed.
L3 cache is used with server-based processors.
Memory Cache:
Static Random Access Memory (SRAM)
© 2008 Lenovo
SRAM
Static random access memory (SRAM) is a type of memory that can be accessed at all times,
because static RAM chips do not need refreshing (in contrast to dynamic random access memory
[DRAM]). SRAM memory provides faster access, and is more expensive than DRAM. It is used
primarily for processor caches.
There are manufacturing differences for L1 and L2 caches that are placed on the processor die, as
opposed to being placed on an external memory die as in some L3 designs. These differences relate
more to power and space concerns than any functional differences. The SRAM on the die of the
processor must provide data in zero wait state (i.e., it must function with a cycle time that is equal
to the frequency of the processor).
All processors today have caches that use SRAM. If the L1, L2, and L3 cache is on the die of the
processor (meaning the same physical chip), this cache must be fast enough to provide zero wait
states. For example, a processor at 1 GHz needs 1.0 ns to have zero wait states.
Summary:
Memory Architecture
© 2008 Lenovo
Magnetic RAM
A new kind of computer memory chip is being developed
by IBM’s Almalden Labs. The chip has the potential to
eventually replace all RAM technologies. Magnetic Random
Access Memory (MRAM) is a microscopic memory-cell
technology that consumes little power and is non-volatile
memory meaning it retains data when power is shut off.
Resolving the issue of volatility has been the single largest
issue facing the DRAM industry over the past ten years.
This positions MRAM as a potential replacement for
Ferro-Electric Random Access Memory (FeRAM),
Static RAM (SRAM), and potentially for high-performance,
low-power, embedded applications such as those addressed Magnetic RAM chip
by Electrically Erasable Read-Only Memory (EEPROM) today. MRAM is much faster than Flash
memory. The current speed projection for MRAM is about six times faster than today’s DRAM
memories with initial chip density projected to be one megabyte. MRAM is in early development
and is classified as an alternative technology. MRAM depends on magnetic polarity to store data,
rather than electricity like DRAM chips, and stores bits in magnetic layers rather than charges,
yielding non-volatile solid-state storage with speeds comparable to SRAM. Initial production will
use .25 micron technology with limited production expected to begin in 2005.
Review Quiz
Objective 1
Objective 2
3. What memory technology is used for data storage as an alternative to disk-based technology?
a. L2 cache
b. L5 cache
c. Intel Flex Memory Technology
d. Flash memory
Objective 3
4. What does double data rate (DDR) refer to with DDR2 and DDR3 memory?
a. Data is transferred on both rising and falling edges of clock.
b. DDR DIMMs must be installed in pairs.
c. DDR memory have read speeds that differ from their write speeds.
d. Multibit error correction.
Objective 6
Answer Key
1. A
2. B
3. D
4. A
5. C
6. B
7. C
8. B
PC Architecture (TXW102)
Topic 4:
Bus Architecture
© 2008 Lenovo
Objectives:
Bus Architecture
© 2008 Lenovo
© 2008 Lenovo
PCI Bus:
PCI Overview
• Industry-standard Peripheral
Component Interconnect (PCI)
bus used in most PCs since 1993
Processor +
• PCI slots still used in desktops PCI Express
L1/L2 cache
PCIe
• Usually implemented as 32-bit x16 slot Memory
MCH or
33 MHz bus PCI Express slots GMCH
Host Bridge PCIe Mobile
• Being replaced by PCI Express docking
PCIe PCIe
ExpressCard
PCI 2.0 I/O USB 2.0
Controller PCIe
Hub Mini Card
(ICH) USB 2.0
PCIe Integrated
PCI 2.0 slots systemboard
devices
Super I/O
Firmware
Hub
© 2008 Lenovo
PCI Overview
Peripheral Component Interconnect (PCI) is an industry standard bus architecture defined by the
PCI Special Interest Group (www.pcisig.com) used since 1993 in virtually all PCs, from notebooks
to servers. As a bus architecture, PCI defines how subsystems communicate with other subsystems.
Subsystems may be in integrated on a motherboard or via slots inside desktops or in notebook
docking stations. More subsystems are moving to integration in chips (such as the I/O Controller
Hub) or to dedicated buses/links (such as PCI Express), so PCI’s importance is not as critical as
previously.
Whereas ISA and Micro Channel support DMA, there is no DMA function with PCI. However,
busmasters can be devices on a PCI bus. The use of a busmaster device releases the processor from
the data transfer; this fact is important in multitasking operating systems. PCI supports automatic
configuration; thus there are no jumpers or DIP switches. All PCI adapters must include 256 bytes
to store configuration information.
The processor can write data to PCI peripherals, and the PCI bridge/controller can store the data
immediately in its buffer. This process lets the processor quickly go to the next operation rather
than waiting for it to complete the transfer. The buffer then feeds the data to the PCI peripheral in
efficient bursts. The bridge can buffer a non-burst write from the processor and present it to the PCI
bus as a burst write. A combination of buffering and bursting can essentially mask the delays
coming from bus isolation.
PCI burst transfers have an indefinite length, whereas most other architectures have a limited, fixed
burst length. PCI bursts continue until the master or target requests the transfer to end, or until a
higher priority peripheral needs to use the bus. PCI requires a fairness arbitration algorithm;
therefore, any device can preempt a long burst transfer.
Control signals are mixed with data transfers on the bus (AGP can do sideband signaling to
transmit control signals on separate lines from the data channel).
PCI Specifications
PCI, a local bus specification (an open standard), was released by Intel in May 1993 as PCI 2.0.
Although Intel developed PCI, it has formed an industry group called the PCI Special Interest
Group to control the specification, and several PCI patents are royalty free.
The PCI Bus Power Management Interface Specification establishes a standard set of PCI
peripheral power management hardware interfaces and behavioral policies and thereby enables an
operating system to intelligently manage the power of PCI functions and buses. PCs should be
labeled ACPI-compliant. Such states include PCI power management compliance. PCI power
management is intended to be an independent method of supporting power management on the PCI
bus (but is compatible with ACPI). Version 1.0 was ratified in 1997, and version 1.1 was ratified in
1998. Version 1.1 added a Vaux as a pin on the connector to be used by the I/O device. When
enabled by software, Vaux powers wake-up logic to wake up the system.
PCI Parity
Data and address parity is required for all PCI peripherals (in other architectures it is either
impossible or optional). The data source – master on a write and target on a read – always generates
parity. Parity checking (for the device receiving the data) is optional for systemboard devices and
required for adapters except devices that cannot cause a data integrity problem like sound cards.
PCI has a single parity bit that covers the address/data bus plus the command or byte enables.
Micro Channel supports parity per byte on both the address and data bus.
The bus isolation of PCI allows faster processors to use the bus. PCI adapter vendors can design
one card to operate with Intel, PowerPC, Transmeta and other brands.
Burst Mode
The following example shows the same master writing to different targets (or same target with
nonsequential address); thus, an idle period is not needed.
• 66 MB/s for writes (best case, no wait states, fast address decode by target):
Bus
Address Data Idle
Turnaround
30.3ns 30.3ns 30.3ns + 30.3ns
With a 33 MHz PCI bus, the maximum throughput is 132 MB/s. However, 132 MB/s is a burst data
transfer rate; in reality, transfers are always under 132 MB/s and depend on amount of data, write
or read, and wait states.
PCI Bus:
PCI 2.1, 2.2, and 2.3
32-Bit PCI B
PCI 2.2 (January 1999)
I/O Slots
• PCI hot plug capability
• PCI power management
PCI 2.1
PCI 2.1 was introduced in August 1995 to supersede PCI 2.0. One key new feature is the support of
bus speeds from 0 to 66 MHz (from 20 to 33 MHz); 0 MHz is necessary on notebooks in order to
improve battery life and support for delayed transactions.
PCI 2.1 supports a bus that is a compatible superset of PCI 2.0 and is defined to operate up to a
maximum clock speed of 66 MHz. The 66 MHz PCI bus is intended to be used by low-latency,
high-bandwidth bridges and peripherals. Systems may augment the 66 MHz PCI bus with a
separate 33 MHz PCI bus in order to handle lower speed peripherals.
Differences between 33 MHz PCI and 66 MHz PCI are minimal. Both share the same protocol,
signal definitions, and connector layout. To identify 66 MHz devices, one static signal is added by
redefining an existing ground pin, and one bit is added to the configuration status register. Bus
drivers for the 66 MHz PCI bus meet the same DC characteristics and AC drive point limits as 33
MHz PCI bus drivers; however, 66 MHz PCI requires faster timing parameters and redefined
measurement conditions. As a result, 66 MHz PCI buses may support smaller loading and trace
lengths.
A 66 MHz PCI device operates as a 33 MHz PCI device when it is connected to a 33 MHz PCI
bus. Similarly, if any 33 MHz PCI devices are connected to a 66 MHz PCI bus, the 66 MHz PCI
bus will operate as a 33 MHz PCI bus (forward and backward compatibility is maintained). The
programming models for 66 MHz PCI and 33 MHz PCI are the same, including configuration
headers and class types. Agents and bridges include a 66 MHz PCI status bit. A 66 MHz PCI
component/adapter must use the 3.3-volt, and not the 5.0 volt, signaling environment.
PCI 2.2
PCI 2.2 was ratified in January 1999 and included the following: support for hot pluggability,
updates to PCI power management, message signaled interrupts (MSI) (a requirement for 3.3-volt
signaling for PCI connectors), and a roll-up of engineering change notices (ECNs) and errata since
2.1.
Hot pluggability is the ability to insert and remove PCI adapter cards without powering off the
system. This capability allows for several implementations, including hot replace (replacing adapter
cards in "hot systems"), hot upgrade (upgrading existing adapter cards with new versions of cards
and drivers), and hot expansion (adding previously uninstalled cards and associated driver software
into the system).
PCI power management addresses the issues of standardized power management capabilities and
energy conservation on the PCI bus. The latest power management specification is aligned with the
ACPI specification, enabling PCI devices – both systemboard and add-in – to participate in
platform-wide operating system-directed power management.
ECNs adopted since version 2.1 of the PCI specification cover a variety of areas, including
modifications to accommodate PCI power management and mechanical issues such as bracket
mounting, tolerances, and riser connectors.
PCI 2.2 requires any PCI connector to support 3.3-volt power on the pins labeled +3.3v (as
opposed to 5v). As this logic becomes more widespread in the industry, it allows devices with this
logic to function. While a PCI adapter may still be a 5-volt adapter (and keyed for a 5-volt
connector), a 5-volt adapter may contain 3.3-volt logic on it. Providing 3.3-volt power on the
connector allows the use of 3.3-volt logic without the need for a +5v to +3.3v power converter. The
purpose of requiring 3.3-volt power on the connector is to enable the use of 3.3-volt logic and
encourage the development of Universal cards (keyed for both 5-volt and 3.3-volt signaling).
Message Signaled Interrupts (MSI) is a PCI interrupt signaling mechanism introduced as an
optional feature in PCI 2.2. Typically, a PCI device uses interrupt pins to request a service and is
limited to four interrupt pins. Thus, four IRQs are allowed for PCI devices in a system. While PCI
devices typically share a single IRQ, better performance can be obtained by not sharing IRQs. With
MSI, devices do not use interrupt pins to request service; rather, they write a system-specified
message to a system-specified address (a PCI memory write transaction). MSI will allow each
device to support up to 32 unique interrupts. In reality, having one interrupt per device is more
practical. Intel will probably support one unique interrupt per device and/or the OS will support
only one. The x86 architecture limits a system to 256 interrupts. (MSI theoretically supports
65,536.) The advantage is that systems can support a large number of interrupts without increasing
interrupt controller pin count, thereby reducing system cost and interrupt routing complexity. MSI
can increase performance in that each device can have its own interrupt.
PCI 2.3
PCI 2.3 was approved in February 2003. PCI 2.3 is an evolutionary change to the PCI local bus
specification. PCI 2.3 makes a significant step in migrating the PCI bus from original 5.0 volt
signaling to a 3.3 volt signaling bus. Revision 2.3 supports the 5V and 3.3V keyed systemboard
connectors (as did revision 2.2), but revision 2.3 supports only the 3.3V and Universal keyed add-
in cards. The 5V keyed add-in card is not supported in revision 2.3. PCI 66, PCI-X, Mini PCI, and
Low Profile PCI support only 3.3 volt signaling on 3.3V keyed systemboard connectors and 3.3V
and Universal keyed add-in cards.
PCI 2.3 also incorporated the following changes:
• Support added for the System Management Bus (SMBus) by adding a two-wire management
interface to the PCI connector
• New reset timing parameter added
• New bit fields added to registers in configuration address space
• Officially added the low profile PCI adapter card form factor, although it had been used since
2000
• Revision 2.3 also incorporates other ECNs and approved errata. Compliance to Revision 2.3 will
be required no later than January 1, 2004.
Internal delay of chips; rising clock edge on chip until valid signal 11ns 6ns
Propagation delay, time it takes master to control the bus 10ns 5ns
Input setup time 7ns 3ns
Clock skew 2ns 1ns
Total time: 30.3ns 15ns
PCI allows ten loads (at 33 MHz). One load goes to each systemboard peripheral, the PCI
bridge/controller, and an expansion bus bridge; two loads go to each adapter card slot. PCI is
therefore said to support a maximum of ten peripherals.
All subsystems of the PCI bus run at a specific clock rate; i.e., PCI cannot make a change in speed
based on the subsystem doing the transfer.
The PCI bus can be clocked at any frequency under 66 MHz. It does not have to be an exact
multiplier of the processor clock.
Doubling the bus to 64 bits is expensive in that it requires more pins on system chipsets, more
traces on systemboards, and more complex PCI adapters; a 66 MHz-speed is more economical.
Delayed Transactions
Delayed transactions is a new feature in PCI 2.1. It is primarily used in PCI-to-PCI bridges but
could also be implemented in the PCI host bridge controller. The purpose is to have predictable
time delays when transferring between slow devices, because in PCI 2.0 the length of time was
unpredictable. The result is that performance with PCI-to-PCI bridges is improved.
For example, when a read is initiated by the processor to a device on a secondary PCI bus, delayed
transaction allows the PCI-to-PCI bridge to take the read command and execute it on its own. (If
the secondary bus is busy when the processor does the read.) The PCI-to-PCI bridge will hold the
data in the buffer when the read is finally complete. When the processor executes a retry, it can get
the data from the buffer of the PCI-to-PCI bridge (instead of going across the secondary bus, which
may be busy again).
Delayed transactions also apply to writes. If the write is to prefetchable memory, the processor can
continue to other tasks while the PCI bridge eventually writes the data at a later point. Prefetchable
memory is defined as memory that is readable prior to the need for it. If it is not needed, it is
discarded.
PCI Bus:
PCI Connectors
Key = 5v slot
64-bit portion of connector
3.3 volt, 32-bit, 66 MHz connector
© 2008 Lenovo
PCI Connectors
PCI adapters use connectors (also called slots) which are either 32-bit or 64-bit for the data transfer
path. The 64-bit connector is a superset of the 32-bit connector. 32-bit PCI adapters can be used in
a 64-bit slots and vice versa. If a 64-bit adapter is plugged into a 32-bit slot, the adapter only uses
32-bit transfers. The connector is keyed for 5-volt or 3.3-volt adapters; PCI-X 2.0 adapters can use
1.5-volt signaling in a 3.3-volt connector. Universal adapters could be designed to differentiate
between the two voltages and be keyed to fit either type of slot connector. Every active signal on
the PCI bus is either next to or opposite a power supply or ground signal in order to minimize stray
radiation.
66 MHz, 3.3 V,
Support Support Support No No Support
64-bit Slot
66 MHz, 3.3 V,
Support Support Support No No Support
32-bit Slot
33 MHz, 5.0 V,
No No No Support Support Support
64-bit Slot
33 MHz, 5.0 V,
No No No Support Support Support
32-bit Slot
In the late 1990s, it was typical of systems to have "shared" I/O slots, which can be used for either
of two types of expansion boards. The shared slots illustrated above will accept either a PCI or an
ISA/EISA/Micro Channel card.
ISA/EISA/Micro Channel
Mounting ISA/EISA/MC expansion board
bracket connector
For PCI adapters, there is a difference between voltages regarding signaling levels and power
supply levels. The signaling level for PCI is for data transfer signaling. PCI connectors that are
keyed for 3.3 volts, 5 volts, or universal refer to this signaling level. Power supply levels are 3.3
volts and 5 volts and refer to powering the logic chips on the adapter. ThinkCentre systems have
always provided 3.3 volt and 5 volt power supply levels to PCI adapter slots, but many competitors
have only supplied 5 volt.
64-bit, 33 MHz
Key here = 5 V slot 64-bit extension
32-bit, 66 MHz
PCI Express
Half Duplex
Form Factor Use
Bandwidth (1.0)
(Older) PCI 2.3 32-bit 1 Gb/s Common in desktop and notebooks
PCI Express x1 1-bit 2.5 Gb/s Slots, Gb Ethernet
PCI Express x4 4-bit 10 Gb/s 10 Gb Ethernet, slots, links, SCSI, SAS
Slots, links, Infiniband adapters,
PCI Express x8 8-bit 20 Gb/s
Myrinet adapters
PCI Express x16 16-bit 40 Gb/s Graphics
© 2008 Lenovo
Unidirectional pair of
wires at 2.5 Gb/s
Packet Transmit
Device Device
Selectable width
Ref. clock A B Ref. clock
Packet Receive
Parallel bus
Original Crosstalk in
signals adjacent signals
Crosstalk happens when the signal on one wire in a parallel
bundle imprints itself on an adjacent wire.
Encoded Unencoded
PCI Express
Duplex Duplex
Implementation
Data Rate Data Rate
x1 5 Gb/s (625 MB/s) 4 Gb/s (500 MB/s)
x4 20 Gb/s (2.5 GB/s) 16 Gb/s (2 GB/s)
x8 40 Gb/s (5 GB/s) 32 Gb/s (4 GB/s)
x16 80 Gb/s (10 GB/s) 64 Gb/s (8 GB/s)
... ...
Byte 5 Byte 5
Byte 4 Byte 4
Byte 3 Byte 3 Byte stream
(conceptual)
Byte 2 Byte 2
Byte 1 Byte 1
Byte 0 Byte 0
Byte 3
Byte 2
Byte 1 Byte 4 Byte 5 Byte 6 Byte 7
Byte 0 Byte 0 Byte 1 Byte 2 Byte 3
GbE
TX- CAP RX-
Port 0 Port 0
RX+ CAP TX+
RX- CAP TX-
TX+
TX-
Port 1
RX+
RX-
ICH6
TX+
Lane
TX-
Port 2
RX+
RX-
TX+
x1 Link
TX-
Port 3
RX+
RX-
• Port
– A group of transmitters and receivers located on the same chip capable of forming an
independent link
• Lane
– A signal path that connects a set of differential signal pairs, one pair for transmission and one
pair for reception between two devices
• Link
– An associated port and lane or multiple ports and lanes forming a connection between two
devices
The three protocol layers are transaction, data link, and physical. From the transmitting side of a
transaction, packets are formed at the higher layers, and each successively lower layer adds more
information to the packet, until it is sent across the physical link to the receiving device. The packet
then traverses up the protocol stack at the receiving device until data is extracted and passed to the
application.
Software Software
Transaction Transaction
Physical Physical
Mechanical Mechanical
The following diagram illustrates the actual packet structure showing the envelope within an
envelope construct of layered protocols. The higher layers of packet information are encapsulated in
the lower layer envelopes. The application-level data is ultimately at the core of the packet. The
transaction layer uses a 32-bit CRC for end-to-end transfers by optionally including a trailer
section, known as a digest. The CRC for the data link layer is a 16-bit value.
Sequence
Frame Header Data CRC Frame
number
Transaction layer
Physical layer
PCI Express supports multiple virtual channels per lane. Up to eight different independently
controlled communication sessions may exist in a single lane. Each session may have different
quality of service definitions per the packet's Traffic Class (TC) attribute. As a packet travels
though a PCI Express fabric, at each switch or link endpoint, the traffic class information can be
interpreted and appropriate transport policies applied. The traffic class descriptor in the packet
header comprises three bits representing eight different traffic classes.
PCI Express has four different transaction types of transactions: memory, I/O, configuration, and
message.
Transaction Types for Different Address Spaces
Interrupts
PCI Express supports two types of interrupts: the older PCI INTx (where x = A, B, C, or D) legacy
interrupt using an emulation technique and the newer Message Signaled Interrupt (MSI) capability.
MSI is optional in PCI 2.2/2.3 devices but required as the native mode of PCI Express devices.
The INTx emulation can signal interrupts to the host chipset. This emulation is compatible with
existing PCI-compatible driver and operating system software. The emulations virtualizes PCI
physical hardwired interrupt signals by using an in-band signaling mechanism. PCI Express devices
must support both the legacy INTx and MSI modes, and legacy devices will encapsulate the INTx
interrupt information inside a PCI Express Message transaction.
MSI interrupts are edge-triggered and sent via memory write transactions. Driver rewrites would be
necessary to take advantage of MSI edge-triggered interrupts. The MSI scheme is the desired native
method of interrupt propagation when using a packetized protocol over a serial link (because there
are no sideband or extra hardwired interrupt signals).
PCI Express:
PCI Express 1.0/1.1 vs. PCI Express 2.0 (PCIe2)
• PCI Express 2.0 doubles bandwidth from 2.5 GT/s to 5.0 GT/s
• PCI Express 2.0 is compatible with earlier version (1.0 and 1.1) so older
adapters will work
• PCI Express 2.0 has improvements in data transfer protocol and software
architecture
• Vendors may implement a mix of PCI Express 2.0 for graphics and
PCI Express 1.0 for remaining devices
© 2008 Lenovo
PCI Express:
Implementation
Processor
x16
Graphics PCI Express Connectors
MCH Memory
PCI Express
PCI slots
Gb Ethernet
Serial ATA
PCI Express x1 slot ICHx
USB 2.0
PCI Express x1 slot Super I/O
© 2008 Lenovo
Desktop Slots
A family of connectors is specified, ranging from x1 to x16 bus widths, including x1, x4, x8, and
x16. The x2 configuration is reserved for other types of PCI Express interconnects, but not in slots.
The connectors for AGP replacement slots will be x16. Legacy PCI slots will exist on their own
and will sit adjacent to native PCI Express connectors. It will be possible to up-plug smaller PCI
Express cards into larger slots, but not vice-versa. Down-plugging is not allowed, so larger link-
width cards will not operate in smaller slots. PCI Express cards optionally can support hot-plug and
hot-swap features. Three voltage rails are available: +3.3V, +3.3Vaux, and +12V.
Both standard and low profile adapters for desktops, workstations, and servers are available. The
standard and low profile form factors support x1, x2, x4, and x16 implementations.
PCI 2.3
PCI 2.3
PCI Express x1
PCI Express
Connector, x1
PCI Express
Connector, x16
millimeters (mm)
0 10 20 30 40 50 60 70 80 90 100 110 120 130
PCI
x1
AGP 8X
x16
AGP Pro
x16
PCI-X
x4
x8
x16
PCIe x8 Adapter with x8 edge connector capable of operating in x8, x4, x2, or x1 negotiable
Link width, uses 2.5 GT/s signaling, and requires 25W to be delivered by the PCIe
slot.
PCIe x16 (16,8,4,1) 75W Adapter with x16 edge connector capable of operating in x16, x8, x4, or x1
negotiable Link width, uses 2.5 GT/s signaling, and requires 75W to be delivered by
the PCIe slot.
PCIe x16 (16,8,4,1) 75W Adapter with x16 edge connector capable of operating in x16, x8, x4, or x1
+EXT 75W negotiable Link width, uses 2.5 GT/s signaling, and requires 75W to be delivered by
the PCIe slot. Adapter also requires an additional 75W from the PCIe x16 Graphics
150W-ATX power connector. Adapter may not operate at full performance or only in
diagnostics mode if the additional power connector is not present.
PCIe2 x16 (16,8,4,1) 75W Adapter with x16 edge connector capable of operating in x16, x8, x4, or x1
+EXT 150W negotiable Link width, uses 5.0 GT/s signaling, and requires 75W to be delivered by
the PCIe slot. Adapter also requires an additional 150W from the PCIe High Power
Specification connector. Adapter may not operate at full performance or may only
operate in diagnostics mode if the additional power connector is not present.
PCIe2 x16 (16,8,4,1) 75W Adapter with x16 edge connector capable of operating in x16, x8, x4, or x1
+EXT 225W negotiable Link width, uses 5.0 GT/s signaling, and requires 75W to be delivered by
the PCIe slot. Adapter also requires an additional 225W from the PCIe High Power
Specification connector. Adapter may not operate at full performance or may only
operate in diagnostics mode if the additional power connector is not present.
PCIe2 x4 Adapter with x4 edge connector capable of operating in x4, x2, or x1 negotiable Link
width, supports 2.5 GT/s and 5.0 GT/s signaling, and requires 25W to be delivered
by the PCIe slot.
PCIe x16 75W Slot using a x16 connector, supports x16, x12, x8, x4, x2, and x1 adapters, uses 2.5
GT/s signaling and provides 75W power to an Adapter.
PCIe x8 (4,1) Slot using a x8 connector but with a x4 maximum Link width using 2.5 GT/s
signaling and provides 25W power to an Adapter.
PCIe x16 (8,1) 75W Slot using a x16 connector but with a x8 maximum or a x1 negotiable Link width
using 2.5 GT/s signaling and provides 75W power to an Adapter.
PCIe2 x16 (8,1) 300W Slot using a x16 connector but with a x8 maximum or a x1 negotiable Link width
using 5.0 GT/s signaling and provides 300W power to an Adapter.
PCIe2 x16 (16,1) Slot with x16 connector, supports a x16 maximum Link width or x1 negotiable Link
width using 5.0 GT/s signaling and provides 25W power to an Adapter.
PCIe 5 x8 Slot number 5. Slot with a x8 connector, supports x8, x4, x2, and x1 adapters, uses
2.5 GT/s signaling and provides 25W power to an Adapter.
PCIe Power Slot provides a PCIe connector but does not support the PCIe protocol. Default
power 25W is provided.
PCIe Power 75W Slot provides a PCIe connector but does not support the PCIe protocol. 75W power
is provided.
Typically, the size of a slot matches the number of lanes it has. For example, a x4 slot is typically a
x4 link (that is, it has 4 lanes). However, this is not always the case. The PCI Express specification
allows for the situation where the physical connector is larger than the number of lanes of data
connectivity. The only requirement on manufacturers is that the connector must still provide the full
complement of power and ground connections as required for the connector size.
For example, a system could have these two slots:
• PCIe x8
• PCIe2 x8 (4,1)
The first slot is PCI Express with x8 physical connector (in other words, it will physically accept x8
cards, as well as x4, x2, and x1 cards), and it has the bandwidth of a x8 link (8 x 2.5 GT/s or 20
GT/s). The second slot is a PCI Express 2.0 slot with x8 physical connector, but it only has the
bandwidth of a x4 link (4 x 2.5 GT/s or 10 GT/s).
If there is a need for x8 bandwidth (such as for an Infiniband or Myrinet adapter), then ensure the
correct slot is selected (one with x8 lanes).
The physical size of a PCI Express slot is not the sole indicator of its possible bandwidth. The
bandwidth capacity of each slot must be determined from slot descriptions on the system board or the
service label of the server.
PCI Express:
Mini PCI Express
Mini PCI Express adapters support two primary system bus interfaces: PCI Express and USB 2.0.
An adapter can use either PCI Express or USB 2.0 (or both).
PCI
Modem
Express
x1
System buses
LEDs
Processor
x16
Graphics Memory
MCH
Docking x16
x16
PCI Express
x1
Allows
2nd
51 mm 51 mm card
61 mm 30 mm 30 mm
Two Full-Mini PCI Express adapters will fit in same space as older Mini PCI
PCI Express:
Mini PCI Express Form Factors
© 2008 Lenovo
Front Back
Half-Mini PCI Express Adapter
(Intel Turbo Memory 2GB and 4GB)
Platform Example
One Type F1
F1
H2
Two Type F1 and One Type H2 F1 F1
Bottom Side
Bottom Side
PCI Express:
PCI Express 1.0 vs PCI
x8 40
x4 20
x2 10
x1 5
PCI-X 2.0
QDR 32
DDR 16
PCI-X 1.0
8
© 2008 Lenovo
PCI-X 2.0
Quad
32 Gb/s or 4.2 GB/s or 4200 MB/s at 64-bit 533 MHz
data rate
Double
16 Gb/s or 2.1 GB/s or 2100 MB/s at 64-bit 266 MHz
data rate
PCI-X 1.0
8 Gb/s or 1064 MB/s at 64-bit 133 MHz
4 Gb/s or 528 MB/s at 32-bit 133 MHz
6 Gb/s or 800 MB/s at 64-bit 100 MHz
3 Gb/s or 400 MB/s at 32-bit 100 MHz
4 Gb/s or 528 MB/s at 64-bit 66 MHz
2 Gb/s or 264 MB/s at 32-bit 66 MHz
PCI 2.3
4 Gb/s or 528 MB/s at 64-bit 66 MHz
2 Gb/s or 264 MB/s at 64-bit 33 MHz
2 Gb/s or 264 MB/s at 32-bit 66 MHz
PCI 1.0
1 Gb/s or 132 MB/s at 32-bit 33 MHz
ExpressCard
© 2008 Lenovo
ExpressCard
ExpressCard technology is a standard released in 2003 by the Personal Computer Memory Card
International Association (PCMCIA). ExpressCard is a small, modular add-in card designed to
replace the larger PC Card over the next couple years. ExpressCard slots were first introduced in
notebooks in 2005 with the Mobile Intel 9xx Express Chipset.
The ExpressCard add-in cards are called modules. Modules can include wired or wireless
communication devices, solid state or rotating optical and magnetic storage devices, identity
sensors, flash memory cards, networking devices, smart card readers, TV tuner devices, etc.
To support a broad range of device types, there are two sizes available; both are smaller than the
common PC Card. The smaller card, the ExpressCard/34 module, has a width of 34 mm. The larger card,
the ExpressCard/54 module, has a width of 54 mm. All modules are 5 mm thick and 75 mm long, but the
standard allows for developers to build longer, extended modules that have thicker portions projecting
beyond the envelope of the host system. The larger ExpressCard/54 module provides approximately
140% of the internal volume capacity of the ExpressCard/34 module.
54mm
PC Card
(54mm x 85.6mm)
ExpressCard/34
(34mm x 75mm)
85.6mm
ExpressCard/54
(54mm x 75mm)
ExpressCard:
Implementation
ExpressCard/34
PCI
Express
Host chipset
54 mm slot
USB
ExpressCard/54
© 2008 Lenovo
ExpressCard Implementation
ExpressCard slots require support of both USB 2.0 and PCI Express ( 1 link). An ExpressCard
module can be implemented using either PCI Express or USB, depending on the bandwidth
required. A USB-based ExpressCard module is practical for lower-speed devices such as Bluetooth
wireless cards or flash memory. A PCI Express-based ExpressCard is useful for higher-bandwidth
devices such as Gigabit Ethernet or 1394b cards. All ExpressCard slots will support cards using
either interface. The host platform no longer needs to incorporate a bridge chip between the chipset
and the socket.
The ExpressCard link has a potential transfer rate of up to 5.0 Gb/s or 400 MB/s (2.5 Gb/s or 200
MB/s in each direction) using a single-lane 1 PCI Express link; this link is up to four times faster
than a CardBus PC Card transfer. USB 2.0 uses a transfer rate of 480 Mb/s or 60 MB/s.
The connector is a 26-pin, beam-on-blade style with a serial interface. The connector includes
signals for control, power, and I/O; it uses a beam or blade connector type. The older PC Card used
68 pins with a parallel interface and a pin-in-socket connector type.
A conventional push-button or other module ejection mechanism can be implemented at each
system OEM's discretion.
ExpressCard is fully hot-pluggable and hot-swappable.
See www.expresscard.org for more information.
PCI
Host chipset
Express
x1
34 mm slot
USB
2.0
ExpressCard/34
ExpressCard/34
PCI
Express
x1
Host chipset
54mm slot
USB
2.0
ExpressCard/54
ExpressCard/34 PCI
Express
Host chipset
x1
68 mm slot USB
2.0
ExpressCard/34
PCI
ExpressCard/54
Express
Host chipset
x1
68 mm slot USB
2.0
While ExpressCard slots are expected in notebooks, ExpressCard slots are useful for desktops
because they allow expansion to a desktop without requiring the opening of the cover (such as to
add PCI or PCI Express adapters). ExpressCard slots give desktops the same ‘sealed box’
computing benefits enjoyed by notebooks.
ExpressCard technology draws upon many of the features of existing PC Card technology.
ExpressCard technology balances size and utility, reliability and durability, and features hot plug-n-
play and auto-configuration. There are also other significant differences between the PC Card
standard and ExpressCard standard.
1. Size: ExpressCard modules are roughly half the size of PC Card; the modules are lighter weight.
2. Speed: ExpressCard modules use serial data interfaces rather than the PCI parallel bus interface
of PC Card, improving bus speed in data transfer while reducing the number of signals needed in
the interface.
3. Cost: Because of its system and mechanical design, ExpressCard designs are anticipated to have
a lower implementation cost.
4. Less power: ExpressCard modules are expected to require less power than has traditionally been
required. Both types of modules put out less than 1.3 watts of dissipation.
5. Ease of use: ExpressCard modules offer a much easier method for installing new capabilities in a
desktop computer, because it eliminates the need to open the CPU chassis in order to add
functionality. In addition, ExpressCard is hot-swappable between mobile and desktop systems,
which is another plus for end users.
PC Monitor Keyboard
Phone/
Speaker Mic Mouse Digitizer
modem
© 2008 Lenovo
Lenovo USB 2.0 Super Multi-Burner Drive Lenovo USB 2.0 Security Memory Key 4 GB
(part number 41N5565) (part number 41U5120)
With USB-enabled PCs, users are able to hot-plug USB peripherals without needing to reboot their
systems or change IRQ settings, DMA channels, and I/O addresses.
If many USB devices are in use, it is best to use powered USB hubs. Also, it is useful to look for a
hub with per-port switching, which prevents a failed device in the hub from disabling a whole
chain.
USB devices do not require IRQ settings, DMA channels, or I/O settings. Thus, COM and LPT
ports currently occupying an IRQ can be made available.
USB is a tiered-star topology which relies on hubs that permit connection of multiple devices; it
operates as a host/slave architecture. For example, the PC could act as a hub for modems or printers
while a monitor acts as a hub for speakers and microphones, and a keyboard could act as a hub for
a mouse and a joystick. Each USB link (segment) is a point-to-point connection, so a hub is
required at each point where multiple connections are needed. Hubs act as repeaters, which redrive
the signals in each direction and provide termination for each line. Little intelligence is required
because hubs do not process data as it is passed through. Hubs include control and status registers
that enable the host to enable and disable each port and to determine whether a device is connected
to each port. USB supports eight hubs, and each hub can support up to sixteen nodes. For each
USB connector on a PC, if more than one USB device is to be attached, the device attached must
be a hub.
USB can handle isochronous and asynchronous data streams. Isochronous support allows multiple
devices to operate concurrently with guaranteed throughput and data latency (for audio to
synchronized with video). Asynchronous operation is possible for devices that do not require
guaranteed bandwidth.
USB port
USB port that attaches
that attaches 7.3 mm to peripheral
to computer Type B
4.5 mm
Type A (“B” Plug)
(“A” Plug)
12.0 mm 8.5 mm
Cable Application
Std-A plug to
Primary cable for connecting Std-B peripherals to PCs and other hosts
Std-B plug
Std-A plug to
Primary cable for connecting Mini-B peripherals to PCs and other hosts
Mini-B plug
Std-A plug to New – Primary cable for connecting Micro-B or Micro-AB peripherals to PCs and
Micro-B plug other hosts
Micro-A plug to New – Provides OTG products with the same receptacle (Std-A) that is available
Std-A receptacle on PCs. Any peripheral that can connect to a PC can connect to an OTG product
(Adapter) by using this adapter
Micro-A plug to
New – Allows direct interconnection between OTG products
Micro-B plug
Hard-wired
New – Supported on products, such as roll-up keyboards, that are targeted
captive cable with
exclusively for use with OTG hosts
Micro-A plug
U3
U3 is a software platform that lets vendors load software applications that run entirely from a flash-
based USB key. These applications are not just simple file synchronization; there are dozens of U3
applications available, including e-mail clients, antivirus scanners, word processors, Web browsers,
and even a U3 version of Skype. You plug in the key and you can run those applications on any
PC. No changes are made to the system registry, leaving the PC without any evidence of use. See
www.u3.com for more information.
Often systemboards have internal USB connectors. For example, on select Lenovo ThinkCentre
M57 desktops, the USB ports are implemented in the following manner:
• The 6 rear USB ports are soldered onto the systemboard.
• The 2 front USB ports are connected to USB Connector #2 on the systemboard.
There are a total of two USB connectors on the systemboard (both yellow). The one on the left is
unconnected (USB Connector #1); the one on the right is connected (USB Connector #2).
Each systemboard USB connector is capable of supporting two USB ports.
The engineers left USB Connector #1 unconnected so that customers can take advantage of it if
they wish to. If a customer wants two more USB ports in the rear, they can connect two more USB
ports to USB Connector #1 on the systemboard, but this will occupy one PCI slot via an adapter. If
a customer wants to install a memory card reader (in the diskette drive bay), then they can connect
the memory card reader internally to the USB Connector #1 on the systemboard.
• Most USB ports and products shipping since 2004 are USB 2.0-compliant.
© 2008 Lenovo
External
hard drive
Video
camera
Printer
Wireless
USB host
Wireless
USB hub
Digital
camera
Certified Wireless USB uses a hub-and-spoke model where a
wireless USB hub and devices with integrated wireless USB
can communicate with a single host.
• A dual-role model where a device can also provide limited host capabilities. This model would
allow mobile devices to access services with a central host supporting the services (i.e., printers
and viewers). It would also allow devices to access data outside a cluster they are connected to by
creating a second cluster as a limited host.
Performance
Wireless USB performance at launch will provide adequate bandwidth to meet the requirements of
a typical user experience with wired connections. The 480 Mb/s initial target bandwidth is
comparable to the current wired Hi-Speed USB standard. With 480 Mb/s as the initial target, the
Wireless USB specification will allow for generation steps of data throughput. As the Ultra-
Wideband (UWB) radio evolves and future process technologies take shape, bandwidth could
exceed 1 Gb/s. The specification intends for Wireless USB to operate as a wire replacement with
targeted usage models for cluster connectivity to the host and device-to-device connectivity at less
than 10 meters. The 480 Mb/s target is for a range of 3 meters; a range of 10 meters will likely
achieve about 110 Mb/s. It operates in the 3.1 to 10.6 GHz frequency range.
Security
Wireless USB security will be designed to deliver the same level of security as wired USB.
Connection-level security between devices, for instance, will be designed to ensure a device is
associated and authenticated before operation of the device is permitted. Higher levels of security
involving encryption will be implemented at the application level. An important goal will be to
ensure that processing overhead supporting security does not impose noticeable performance
impacts or device cost.
© 2008 Lenovo
peripherals (USB 2.0 provides only 1.5 watts). The smaller 4-pin connectors found in cameras and
other self-powered peripherals omit the power. The new 9-pin IEEE 1934b cables use two pins to
attach a grounded shield that surrounds the other wires and prevents interference from outside
electromagnetic noise, which helps speed up data transmission rates by reducing crosstalk. The
third new pin is unused. (The 1394b committee decided to use a pre-existing cable technology and
didn't want to force cable makers to tool up for eight conductor cables and connectors.) IEEE
1394b is backward compatible, so there are also 9-pin-to-6-pin and 9-pin-to-4-pin adapter cables.
You will not get the higher speed of FireWire 800 if you attach legacy peripherals to what is called
a bilingual port (it speaks both IEEE 1394a and b). The newer b-only, or beta, ports don't support
older IEEE 1394 devices. Due to slight physical differences between b-only and bilingual
connectors, a bilingual port can take both FireWire 800 and older FireWire connectors, while a b-
only port will take only a FireWire 800 connector.
FireWire Architecture
The 1394 bus is a scalable architecture with speeds up to 800 Mb/s (100 MB/s), and work is
underway for a faster speed. The speed depends on vendor implementation. A 1394 controller will
be able to be attached to the PCI bus. One or more 1394 ports may be on the PC. PCI adapter cards
with 1394 controllers and ports are available also.
1394 uses a tree topology; it supports up to 63 nodes on up to 1,023 buses. A PC can address a
single node, broadcast to all nodes, and bridge across buses to as many as 64,000 nodes. 1394
automatically configures peripherals, which are hot pluggable. Addresses are automatically
assigned, so no switches are set. Time required to reconfigure is not more than 400 microseconds.
Each 1394-compatible device will have a unique 64-bit ID number in order for FireWire to identify
it. More than one PC can be connected to the 1394 bus. Devices do not need terminators, special
sequencing, or user awareness of device identifiers. 1394 is a peer-to-peer bus, not a master/slave
bus, as SCSI and Universal Serial Bus (USB) is.
An advantage to FireWire is that it does not need a computer host, nor does it need to signal the
other component that it’s "alive", as current USB implementations must. This kind of data
interruption makes USB impractical for most professional video work. FireWire uses fewer
resources than USB. FireWire can easily coexist with the USB on the same system.
1394 supports synchronous and isochronous (real time) communications. Isochronous support
guarantees on-time delivery, which is necessary for ensuring proper synchronization of audio and
video. Traditional methods of handling digital video require a video capture adapter to convert
analog NTSC/PAL-compatible signals to digital format. 1394 supports
direct connection of digital devices. USB does not handle isochronous data well.
PC
s
b/
M
0
t 20 FireWire
a
er Hub
nsf
a 200 Mb/s
Tr
HDD
400 Mb/s
The FireWire bus transfers at different speeds between devices. Each device transfers at the speed
of the slowest between the two, but not any faster than the the speed of an upstream device.
Windows XP has limited support for 1394 to the 100 Mb/s speed. Microsoft's Windows Vista
operating system will initially support 1394a only; 1394b support will be provided in a service
pack.
The FireWire Trade Association can be reached at www.1394ta.com.
PC Card:
Introduction
© 2008 Lenovo
PC Card Introduction
PCMCIA is the name of a committee of hardware and software vendors (about 500 including
Lenovo) that defines standards for expansion cards that are primarily for portable computers. PC
Cards (as they have come to be called) have roughly the dimensions of credit cards, with varying
thickness, making them suitable for battery-powered notebook computers.
As the name implies, the original intent of the committee was to define a standard specifically for
memory cards such as SRAM memory. Its role has expanded considerably in that I/O cards such as
modems, LAN adapters, and disks have been developed to conform to this standard. In addition to
I/O cards, audio cards with DSPs, global positioning cards, wireless LAN cards, pagers, and other
types have been developed. The ultimate goal of PCMCIA is to provide a set of hardware and
software standards that will allow for the hot pluggability and interoperability of any PC Card in
any computer conforming to the published standard.
There is a hierarchical software structure that must be adhered to in order for PCMCIA to achieve
its promise of hardware independence and interoperability. This structure was finalized in the
November 1992 PCMCIA Standards Release 2.0. Release 2.1 became effective July 1993. PC Card
Standard does not have a version; was originally referred to as 5.0. The PC Card Standard was
published in early 1995, but controllers adhering to this spec were not available until 1996.
See www.pcmcia.org for more information.
PC Card:
Physical Design
Type II Example:
5 mm
54 mm
85.6 mm
© 2008 Lenovo
Type II
Type I Type III
Type I Type II
Type II
PC Card / PCMCIA
• PC Card slots are standard in all ThinkPad notebooks.
• Operating systems include utilities to make installing, configuring, and monitoring PC Cards
extremely easy.
• PC Card Standard and CardBus will increase the performance and use of PC Cards.
• Lenovo is a major PC Card vendor.
• Lenovo is on the PCMCIA board so the company is a major influencer of the standard.
• At its January 1996 meeting, the Personal Computer
Memory Card International Association (PCMCIA)
approved a system of icons designed to help users
easily identify the basic capabilities of a PC Card PCMCA Member DMA Support 3 Volt
or PC Card slot. Several manufacturers have
expressed that they will be implementing the icons
on their products. The icons are the same shape as
the PCMCIA's "PC Card" logo, but contain 16 Bit Zoomed Video 5 Volt
information about a product such as operating
voltage, bandwidth, and optional capabilities such
as CardBus and DMA. The use of the icons is
restricted to the members of PCMCIA and is CardBus Digital Video
completely voluntary. Broadcasting
PC Card:
PC Card Standard
© 2008 Lenovo
PC Card Standard
The PC Card standard is designed to address compatibility problems prevalent in PCMCIA and
facilitate higher performance, lower power, and broader platform applicability. The new standard
includes a number of additional features, forcing network administrators to carefully consider the
features they need and the appropriate products. PC Cards and PC Card-compatible platforms that
worked under the previous standard will also work with the new standard, allowing users a great
deal of flexibility. However, individuals seeking to take advantage of the new features may require
a new or updated PC Card. The new standard includes several features meant to broaden
applications for PC Card technology.
By adding DMA to the standard, PC Cards can have on-board DMA channels which are ideally
suited to devices that frequently generate large amounts of data such as LAN PC Cards.
The previous PCMCIA 2.1 had limitations such as 16-bit transfers, no busmastering support, no
burst or streaming modes, and no data or address parity.
In late 1999, PC Card Standard 8.0 was released, which added a variety of new features including a
new Small PC Card form factor and PCI-style Power Management specification for CardBus. See
www.pcmcia.org for more information. As of late 2003, the latest release is version 8.1.
PC Card:
CardBus and CardBus Plus
CardBus
• Superset of PC Card Standard
• 32-bit transfers based on PCI specification
• 33 MHz with 132 MB/s transfers
• Backward compatible with existing 16-bit
PC Cards
• Standard in ThinkPad systems
10/100 Ethernet
• CardBus PC Cards identified by brass-looking CardBus PC Card
plate with bumps near connector
CardBus Plus
• Includes USB signal to slot
• Enables support for the USB-based
ExpressCard when placed in a special adapter
CardBus Plus is used in
select ThinkPad Notebooks
© 2008 Lenovo
CardBus
The CardBus system has been driven primarily to be compatible with the Peripheral Component
Interconnect (PCI) local bus. CardBus provides for busmastering and allows for a 32-bit data path
by multiplexing address and data. The CardBus requires shielding to the system and card
connectors to achieve the 33 MHz performance. (The original PC card standard had a theoretical
maximum of 10 MHz but cards were typically run at 5 MHz.) This performance, combined with
the 32-bit data capability, provides a transfer rate of 132 MB/s.
• CardBus maintains backward compatibility with existing 8- and 16-bit cards (for PCMCIA
Release 2.0/2.1).
• CardBus uses 68-pin format with additional shielding.
• Vendors can design their products with CardBus-only sockets or CardBus-only PC Cards.
CardBus PC Cards are usually identified visually by a brass-looking-gold-colored plate that often
has eight bumps on it near the connector. This functions as a grounding shield for the higher speeds
across the interface.
CardBus PC Cards have different address space; therefore, they do not have attribute memory
space. Instead, CardBus PC Cards have a special 256-byte configuration space that 16-bit PC Cards
do not have. A pointer to the start of the card information structure (CIS) is stored inside the
configuration space. The CIS itself may reside in any address space on the CardBus card except in
its I/O space.
CardBus PC Cards also do not have configuration registers. In their place is a setup of up to eight
base address registers (BARs). Each BAR is capable of responding to either I/O or memory access
in the host system address space.
CardBus PC Cards may support up to eight separate functions on a single card. Each of these
functions is treated almost as if it were a separate card. Each function has its own configuration
space, CIS, and BARs.
CardBus PC Cards no longer map memory or I/O. Instead, the CardBus PC Card directly decodes
host system access. The down side is that it requires additional logic to handle the decoding.
However, the card now controls the number of address spaces available for both memory and I/O.
On systems and cards that rely on the system adapter to perform decoding, the number of memory
windows is constrained by the adapter. The limit today is typically five memory and two I/O
windows per socket.
While CardBus still relies on client drivers working in conjunction with Card and Socket Services,
modifications have been made to the metaformat and Card and Socket Services while maintaining
compatibility with the 16-bit client drivers. Most notably, in order to support the multi-function
capability of these cards, both Card and Socket Services have been modified. These changes do not
have an impact existing 16-bit client drivers. Rather, a CardBus client driver exploits these
enhanced functions.
All major operating systems support CardBus.
In late 1997, the PCI Bus Power Management Interface Specification from PCMCIA was
approved. This integrates CardBus PC Card power management with ACPI.
CardBus host controllers are a type of PCI bridge and are supported (enumerated and configured)
by the PCI software in operating systems just like other PCI bridges.
• 100 Mb/s Ethernet CardBus PC Card are about 50% faster than an equivalent 16-bit PC Card and
about 70% faster than a 16-bit 10 Mb/s Ethernet PC Card
• 10 Mb/s Ethernet CardBus PC Cards are about 10% faster than an equivalent 16-bit PC Card
CardBus Plus
CardBus Plus was introduced in 2005 in some notebook systems (such as the ThinkPad X41
notebook). CardBus Plus is a normal CardBus slot with a USB 2.0 signal passed to it so that USB-
based ExpressCard modules can be used in a PC Card slot with an adapter. This permits a single
slot to support the older CardBus PC Cards and some new ExpressCard modules. Note that the
ExpressCard module must be placed in a special adapter and must be USB-based, not PCI Express-
based.
CardBus Plus is used in select ThinkPad notebooks.
Chipsets
© 2008 Lenovo
Chipsets
Chipsets are physical hardware chips (circuitry) that control the information flow between
subsystems. Also known as core logic, the chipset of a system is generally as important as the
processor type in that the chipset determines the features and performance of a system.
Intel is the main vendor for chipsets, but other vendors market competitive chipsets. Chipsets are
associated with specific processors, and new chipsets are continually released that provide new
features and performance enhancements.
Intel was calling its chipsets PCIsets because they contained controllers for the PCI bus, but when
accelerated graphics port (AGP) was introduced, the name for chipsets supporting AGP graphics
became AGPset. As PCI is becoming less of a major focus, the generic term chipset is now
common.
Chipsets:
Old and New PC Architectures
Older desktop architecture (2000-2004) Newer desktop architecture (2004 and after)
• PCI bus and Hub Interface • PCI Express and Direct Media Interface
• AGP for graphics • PCI Express x16 graphics (no AGP)
• EIDE disks • Serial ATA disks
Processor + Processor +
L1/L2 cache L1/L2 cache
AGP slot or Memory and opt PCI Express Memory and opt
display cache graphics cont X16 slot graphics cont
MCH or MCH or
PCI Slots GMCH PCI Express slots GMCH
host bridge Memory host bridge Memory
Hub Direct
Interface Media
PCI controller Interface PCIe controller
I/O IDE controller I/O PCI controller
PCI bus controller SATA controller PCIe Controller SATA controller
hub DMA controller Hub IDE controller
(ICH) (ICH)
4 IDE disks USB controller USB controller
4 SATA disks
Super I/O USB Super I/O USB 2.0
Firmware AC '97 codecs Firmware AC '97 codecs
hub hub or
Low Pin (Box) Low Pin
High Definition Audio
Count interface Accel hub arch Count interface
© 2008 Lenovo
Firmware Hub
The firmware hub stores system BIOS and video BIOS in flash memory, eliminating a redundant
nonvolatile memory component. Also, it contains a hardware random number generator (RNG),
which provides random numbers to enable fundamental security building blocks supporting
stronger encryption, digital signing, and security protocols. The hardware RNG is more effective
than a software-based RNG. The device uses thermal noise in a semiconductor junction to produce
random circuit transitions. These transitions are aggregated and checked for true randomness, then
assembled into a random key of any desired length. Software uses this to provide security in
applications.
AC ’97 Audio
With the I/O Controller Hub (ICH) and its follow up versions (ICHx), audio is implemented in
software as soft audio and is effectively moved off the PCI bus. Soft audio is a software solution
that combines a low-cost audio codec integrated circuit (IC) with a small portion of the core
chipset's processing power to form a complete PC audio subsystem. Soft audio processing
consumes minimal CPU overhead and eliminates the typical PCI audio controller from the system.
The result is reduced systemboard space and overall system cost. The diagram that follows
illustrates the transition from legacy audio to soft audio. A sound card such as the Creative Labs
Sound Blaster Audigy 2 PCI adapter does provide the highest quality for musicians, gamers, and
DVD movie buffs. However, Analog Devices SoundMAX 2.0 and 3.0 implement a software-based
sound solution at a $2 USD cost compared to almost $100 USD for a PCI sound card.
ICHx or
South Bridge
ISA PCI Audio
AC-Link
Single Accelerator
Chip
AC-Link AC '97 Codec
Audio
Sigma Tel
AC '97 Codec
• Increasing CPU Performance
Moving to “Soft” Audio • Lower Cost
• Less Area
The SoundMAX includes soft audio (processed in software) from Staccato Systems which is
responsible for high-performance features such as wavetable music synthesis, EAX environmental
effects, and a customizable 3-D positioning environment.
The ICHx performs many I/O control functions, and its audio controller manages audio stream
transfers between system memory and audio codecs, leaving the CPU and PCI bus free to service
other system requests. Included in the ICHx is a controller that has a digital serial link (AC link).
The digital serial link can communicate with codecs like the Analog Devices AD188x audio IC
series found in the SoundMax 2.0 technology.
In 2001, Analog Devices announced SoundMAX with SPX (or SoundMAX 3.0) as a follow on to
SoundMAX 2.0. SoundMAX 3.0 with SPX (Sound Production eXtensions) is a low-cost,
integrated audio solution that surpasses the sound of many expensive PCI-based sound adapters.
Residing on the PC’s systemboard or on a Communications Network Riser (CNR) soundcard,
SoundMAX consists of high-performance hardware codecs, featuring hardware sample rate
conversion (SRC) and professional quality 94-dB playback. SoundMAX software includes
Windows device drivers and applications that supports 3D audio, DirectX, EAX, A3D, unlimited
voice DLS-2 wavetable, 5.1 virtual theater surround, CNR multi-channel output options, and SPX
“audio animation” technologies.
Audio Codec '97 (AC '97) defines a high-quality, 16-bit audio architecture for a PC. The latest
specification is Audio Codec '97 Component Specification v2.3, which can be located at
www.developer.intel.com/ial/scalableplatforms/audio/ on the Internet. The specification is updated
to reflect support for an audio riser, support for numerous codec/audio upgrades, and pertinent
material concerning S/PDIF (Sony/Philips Digital Interface). S/PDIF is a digital audio interface that
is widely used in consumer electronics, specifically all Dolby digital equipment, DVD players,
many CD players, middle-and high-end sound cards, and electronic musical instruments.
The “AC ’97 System Diagram” above shows the essential features of a typical ’97 system design.
The AC ’97 Codec performs DAC and ADC conversions, mixing, and analog I/O for audio (or
modem), and always functions as slave to an AC ’97 Digital Controller, which is typically either a
discrete PCI accelerator or a controller that comes integrated within core logic chipsets.
The digital link that connects the AC ’97 Digital Controller to the AC ’97 Codec, referred to as
AC-link, is a bi-directional, 5-wire, serial TDM format interface at 48kHz. AC-link supports
connections between a single Controller and up to 4 Codecs on a circuit board or riser card.
The system diagram illustrates many of the common PC audio connections, both digital and analog.
PC audio today is rapidly moving towards a Digital Ready architecture that requires all audio
sources must be available in digital form, but a number of legacy analog sources still require the
support of an analog mixing stage.
The AC ’97 architecture supports a variety of audio output options, including:
• Analog stereo output (LINE_OUT) transmitted to amplified stereo PC speaker array via stereo
mini-jack.
• Amplified analog stereo headphone output (HP_OUT) transmitted to headphones or headset via
stereo minijack.
• Discrete analog 4-channel output (LINE_OUT plus 4CH_OUT) transmitted to Front and
Surround amplified stereo PC speaker arrays via dual stereo mini-jacks.
• Analog matrix-encoded Surround output (such as Dolby ProLogic) transmitted via stereo line
level output jack (LNLVL_OUT) to consumer A/V equipment that drives a home theater multi-
speaker array.
• Digital 5.1 channel output (such as Dolby Digital AC-3) transmitted via S/PDIF (SPDIF_OUT)
to digital ready consumer A/V equipment which drives a home theater multi-speaker array.
Chipsets:
Block Diagram with PCI Express
• Chipset components
- Memory Controller Hub (MCH) or Graphics Memory Controller Hub (GMCH)
- I/O Controller Hub (ICH)
• Used in latest Intel chipsets Processor +
L1/L2 cache
PCI Express
X16 slot PCIe
Memory
MCH or
GMCH
Direct Host Bridge PCIe Mobile
PCI Express slots Media docking
Interface
PCIe PCIe
ExpressCard
PCI 2.0 I/O USB 2.0
Controller PCIe
Hub Mini Card
PCI 2.0 slots 4 SATA
(ICH) USB 2.0
disks
PCIe Integrated
systemboard
USB 2.0 devices
Super I/O
Firmware AC '97 codecs
Low Pin Hub or
Count interface High Definition Audio
© 2008 Lenovo
x4 port
RX Point-to-point TX
Differential low
voltage
TX Software RX
transparency
Intel ICHx
SPI BIOS
Chipsets:
I/O Controller Hub
PCIe PCIe
ExpressCard
PCI 2.0 I/O USB 2.0
Controller PCIe
Hub Mini Card
PCI 2.0 slots 4 SATA
(ICH) USB 2.0
disks
PCIe Integrated
systemboard
USB 2.0 devices
Super I/O
AC '97 codecs
Low Pin or
Count interface High Definition Audio
© 2008 Lenovo
Chipsets:
ICH LAN Connect Interface (LCI)
© 2008 Lenovo
Chipsets:
Intel 3 Series Express Chipset Family (Desktop)
Direct Memory
Media
Interface PCIe controller
I/O
PCIe Controller PCI controller
Hub SATA controller
(ICH) USB controller
6 SATA disks
Super I/O Serial USB 2.0
Peripheral High Definition Audio
Low Pin Interface
G33 Express Chipset
Count interface
© 2008 Lenovo
All the chipsets support Intel Fast Memory Access which is a backbone architecture that improves
system performance by optimizing the use of available memory bandwidth and reducing the
latency of the memory accesses. Intel Fast Memory Access consists of these features:
– Just in Time Command Scheduling – Maximizes bandwidth by monitoring all pending
accesses to memory, allowing for the safe and efficient overlapping of commands on the
system memory bus.
– Out of Order Scheduling – This isolation functionality stops infected systems from affecting
others on the network by isolating clients and blocking outbound communication.
– Opportunistic Writes – Monitors system memory requests and issues pending write requests to
memory during idle times, allowing for a more efficient flow of data.
– Clock Crossing Optimizations – Ensures that data is transferred in a highly optimized manner,
enabling data transfer on the first usable clock phase encountered between the two frequency
domains.
Intel Q35 Express Chipset with heat sink on Intel Q35 Express Chipset without heat sink on
Lenovo ThinkCentre systemboard (red box) Lenovo ThinkCentre systemboard (red box)
Chipsets:
Intel G31, G33, G35 Express Chipset Versions (Desktop)
G31 G33 G35
Mainstream PC Mainstream/performance Performance PC
Core 2 Duo, Core 2 Quad Core 2 Duo, Core 2 Quad Core 2 Duo, Core 2 Quad
DDR2-667, DDR2-800,
DDR2-667, DDR2-800 DDR2-667, DDR2-800
DDR3-800, DDR3-1066
800, 1067 MHz bus 800, 1067, 1333 MHz bus 800, 1067, 1333 MHz bus
PCI Express1.1 x16 slot PCI Express 1.1 x16 slot PCI Express 1.1 x16 slot
© 2008 Lenovo
Processor
800/1067/1333 MHz
Intel G33 Express Chipset
Analog
System memory
Display
VGA
Channel A
DDR2/DDR3
LPC interface
Other ASICs
(optional)
Super I/O
Trusted
Platform Module Firmware
(optional) Hub
Chipsets:
Intel Q33, Q35 Express Chipset Versions (Desktop)
Q33 Q35
Corporate Stable Corporate Stable
(Fundamental) (Professional)
Core 2 Duo, Core 2 Quad Core 2 Duo, Core 2 Quad
DDR2-667, DDR2-800 DDR2-667, DDR2-800
800, 1067, 1333 MHz bus 800, 1067, 1333 MHz bus
PCI Express 1.1 x16 slot PCI Express 1.1 x16 slot
© 2008 Lenovo
Chipsets:
Intel P31, P35, X38 Express Chipset Versions (Desktop)
© 2008 Lenovo
Processor
800/1067/1333 MHz
Intel P35 Express Chipset
System memory
Channel A
DDR2/DDR3
PCI Express
Graphics x16 Graphics
Display P35 Channel B
Card MCH DDR2/DDR3
DMI Controller
Interface Link
USB 2.0 Power management
(supports 12 ports,
dual EHCI controller) Clock generation
LPC interface
Other ASICs
(optional)
Super I/O
Trusted
Platform Module Firmware
(optional) Hub
Chipsets:
I/O Controller Hub 9 (ICH9) for 3 Series chipsets (Desktops)
© 2008 Lenovo
ICH8
The I/O Controller Hub 9 (ICH9) was announced June 2007 with four distinct chips:
• Intel 82801IB ICH9
• Intel 82801HR ICH9R
• Intel 82801IH ICH9DH
• Intel 82801IO ICH9DO
Processor
DMI Interface
USB 2.0 Power management
(supports 12 ports,
dual EHCI controller) Clock generation
SATA (6 ports)
System Management
(TCO)
Intel High Definition
Audio CODEC(s) Intel ICH9
SMBus 2.0/I2C
PCI Express x1
SPI Flash
GLCI
Intel Gigabit
Ethernet PHY Slots
LCI
PCI Bus
GPIO
LPC interface
Other ASICs
(optional)
Super I/O
Trusted
Platform Module Firmware
(optional) Hub
ICH9R
The Intel 82801IR I/O Controller Hub 9 (ICH9R) [“R” stands for RAID] supports all the features
of the ICH9 plus the following features:
• Supported with the G33, Q33, Q35, P35, and X38 chipsets
• Six Serial ATA controllers to support six 300 MB/s Serial ATA ports. External Serial ATA
(eSATA) support.
• The ICH9R provides hardware support for Advanced Host Controller Interface (AHCI) with
the Serial ATA host controller; AHCI is not supported with the non-RAID ICH9.
• The ICH9R provides support for Intel Matrix Storage Technology, providing both AHCI and
integrated RAID functionality. The industry-leading RAID capability provides high-
performance RAID 0, 1, 5, and 10 functionality on up to six SATA ports. Matrix RAID
support is provided to allow multiple RAID levels to be combined on a single set of hard
drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot spare
support, SMART alerting, and RAID 0 auto replace. Software components include an Option
ROM for pre-boot configuration and boot functionality, a Microsoft Windows compatible
driver, and a user interface for configuration and management of the RAID capability of
ICH9R.
• Support for Intel Rapid Recovery Technology and Command Based Port Multiplier
• Support for Intel Viiv Technology
RAID 0 Volume
S0 S2 S1 S3
S4 S6 S5 S7
S8 SA S9 SB
RAID 1 Volume
S0 S1 S0 S1
S2 S3 S2 S3
S4 S5 S4 S5
Disk 0 Disk 1
P1-4 S1 S2 S3 S4
S5 P5-8 S6 S7 S8
S9 S10 P9-12 S11 S12
S13 S14 S15 P13-16 S16
S17 S18 S19 S20 P17-20
Physical disks for data and parity (S1 through S20 represent sectors of data from one
file. P1 through P20 represent the parity of sectors S1 through S20).
RAID-5
1 2 3
4 5 6
7 8 9
Note: In data capacity, n refers to the number of equally sized disks in the array.
RAID Also known as Fault tolerance Redundancy type Hot spare option Disks required
0 Striping No None No 1 or more
1 Mirroring Yes Duplicate Yes 2
Striping with distributed
5 Yes Parity Yes 3 or more
parity
Striping across multiple
10 Yes Duplicate Yes 4 or more
RAID-1 arrays
ICH9DH
The Intel 82801IH I/O Controller Hub 8 (ICH8DH) [“DH” stands for Digital Home] supports all
the features of the ICH9 and ICH9R plus the following features:
• Supported with the consumer-oriented G33, P35, and X38 chipsets
• Intel Quick Resume Technology
• Supports Intel Matrix Storage Technology (including Advanced Host Controller Interface)
• Support for Intel Viiv Technology
ICH9DO
The Intel 82801IO I/O Controller Hub 9 (ICH9DO) [“DO” stands for Digital Office] supports all
the features of the ICH9 and ICH9R plus the following features:
• Supported with the corporate-oriented Q35 and X38 chipset
• Support for the Intel Active Management Technology (IAMT) 3.0 for client manageability
when used with the supported Intel Ethernet controller.
• Supports Intel Matrix Storage Technology (including Advanced Host Controller Interface)
with RAID 0/1/5/10
• Support for Intel Rapid Recovery Technology and Command Based Port Multiplier
• Support for Intel vPro Technology
Chipsets:
Intel 4 Series Express Chipset Family (Desktop)
Direct Memory
Media
Interface PCIe controller
I/O
PCIe Controller PCI controller
Hub SATA controller
(ICH) USB controller
6 SATA disks
Super I/O Serial USB 2.0
Peripheral High Definition Audio
Low Pin Interface
G45 Express Chipset
Count interface
© 2008 Lenovo
All the chipsets support Intel Fast Memory Access which is a backbone architecture that improves
system performance by optimizing the use of available memory bandwidth and reducing the
latency of the memory accesses. Intel Fast Memory Access consists of these features:
– Just in Time Command Scheduling – Maximizes bandwidth by monitoring all pending
accesses to memory, allowing for the safe and efficient overlapping of commands on the
system memory bus.
– Out of Order Scheduling – This isolation functionality stops infected systems from affecting
others on the network by isolating clients and blocking outbound communication.
– Opportunistic Writes – Monitors system memory requests and issues pending write requests to
memory during idle times, allowing for a more efficient flow of data.
– Clock Crossing Optimizations – Ensures that data is transferred in a highly optimized manner,
enabling data transfer on the first usable clock phase encountered between the two frequency
domains.
All the chipsets support Intel Flex Memory Technology which facilitates easier upgrades by
allowing different memory sizes to be populated and remain in dual-channel mode.
Chipsets:
Intel G41, G43, G45 Express Chipset Versions (Desktop)
G41 G43 G45
Essential PC Mainstream PC Mainstream/performance PC
Core 2 Duo/Quad Core 2 Duo/Quad Core 2 Duo/Quad
DDR2 or DDR3 DDR2 or DDR3 DDR2 or DDR3
800, 1066, 1333 MHz bus 800, 1066, 1333 MHz bus 800, 1066, 1333 MHz bus
1 DIMM/2 channels 1 DIMM/2 channels 2 DIMM/2 channels
8 GB max memory (DDR2) 8 GB max memory (DDR2) 16 GB max memory (DDR2)
4 GB max memory (DDR3) 4 GB max memory (DDR3) 8 GB max memory (DDR3)
GMA X4500 GMA X4500 GMA X4500HD
DirectX 10-compatible DirectX 10-compatible DirectX 10-compatible
Clear Video Technology Clear Video Technology Clear Video Technology
PCI Express 1.1 x16 slot PCI Express 2.0 x16 slot PCI Express 2.0 x16 slot
Dual Independent Display Dual Independent Display Dual Independent Display
with ADD2 or MEC with ADD2 or MEC with ADD2 or MEC
VGA, sDVO, DVI, VGA, sDVO, DVI, VGA, sDVO, DVI,
DisplayPort DisplayPort, HDMI DisplayPort, HDMI
Full hardware decode of
No No
MPEG2, VC1, AVC
ICH7 ICH10, ICH10R ICH10, ICH10R
No iAMT support No iAMT support No iAMT support
August 2008 June 2008 June 2008
© 2008 Lenovo
Processor
800/1066/1333 MHz
16
ADD2 8 System memory
or MEC
4 Channel A
DDR2/DDR3
PCI Express 4
x16 Graphics GMCH Channel B
DDR2/DDR3
DP/HDMI/DVI
DP/HDMI/DVI
DMI Controller
HDA
Interface Link
USB 2.0 Power management
(12 ports)
SMBus 2.0/I2C
GPIO
Intel High Definition
Audio Codec(s)
6 Serial ATA Ports
Intel ICH10 LCI
SPI Intel 82567 Gigabit Platform
SPI Flash BIOS GLCI LAN Connect
LPC interface
Trusted
Platform Module Super I/O
Chipsets:
Intel Q43, Q45 Express Chipset Versions (Desktop)
Q43 Q45
Corporate Stable Corporate Stable
(Fundamental) (Professional)
Core 2 Duo/Quad Core 2 Duo/Quad
DDR2 or DDR3 DDR2 or DDR3
800, 1066, 1333 MHz bus 800, 1066, 1333 MHz bus
2 DIMM/2 channels 2 DIMM/2 channels
16 GB max memory (DDR2) 16 GB max memory (DDR2)
8 GB max memory (DDR3) 8 GB max memory (DDR3)
GMA 4500 GMA 4500
DirectX 10-compatible DirectX 10-compatible
No Clear Video Technology No Clear Video Technology
PCI Express 2.0 x16 slot PCI Express 2.0 x16 slot
Dual Independent Display Dual Independent Display
with ADD2 or MEC with ADD2 or MEC
VGA, sDVO, DVI, VGA, sDVO, DVI,
DisplayPort DisplayPort
Full hardware decode of Full hardware decode of
MPEG2, VC1, AVC MPEG2, VC1, AVC
ICH10D ICH10DO
iAMT 3.5 support iAMT 5 support
August 2008 August 2008
© 2008 Lenovo
Chipsets:
Intel P43, P45, X48 Express Chipset Versions (Desktop)
© 2008 Lenovo
Processor
800/1066/1333 MHz
Intel P35 Express Chipset
System memory
Channel A
DDR2/DDR3
PCI Express
x16 Graphics MCH Channel B
DDR2/DDR3
DMI Controller
HDA
Interface Link
USB 2.0 Power management
(12 ports)
SMBus 2.0/I2C
GPIO
Intel High Definition
Audio Codec(s)
6 Serial ATA Ports
Intel ICH10 LCI
SPI Intel 82567 Gigabit Platform
SPI Flash BIOS GLCI LAN Connect
LPC interface
Trusted
Platform Module Super I/O
Chipsets:
I/O Controller Hub 10 (ICH10) for 4 Series chipset (desktop)
© 2008 Lenovo
x4x chipset
Direct Media
Interface (DMI)
ICH10
The I/O Controller Hub 10 (ICH10) was announced June and August 2008 with four distinct chips:
• Intel 82801JIB ICH10 Base
• Intel 82801JIR ICH10R Raid
• Intel 82801JID ICH10D Digital
• Intel 82801JIO ICH10DO Digital Office
The Intel 82801JIB I/O Controller Hub 10 (ICH10) supports the following features:
• Supported with G41, G43, G45, P43, and P45 chipset.
• Up to six PCI Express x1 ports (OEM can configure ports 1 to 6 with one to six x1 slots [or
one x4 slot]).
• Six Serial ATA controllers to support six Serial ATA 3.0 Gb/s ports. External Serial ATA
(eSATA) support. It supports an integrated Advanced Host Controller Interface (AHCI)
controller.
• Six USB 2.0 controllers, each supporting two ports and with a maximum of twelve total ports.
The ICH10 contains two Enhanced Host Controller Interface (EHCI) host controllers that
support USB high-speed signaling. The ICH10 also contains six Universal Host Controller
Interface (UHCI) controllers that support USB full-speed and low-speed signaling.
• Integrated Gigabit Ethernet controller (LAN Connect Interface [LCI] and Gigabit LAN
Connect Interface [GLCI]) MAC layer; it requires an Intel family PHY layer or compatible
chip for complete Ethernet functionality.
• PCI 2.3-compliant controller with support for 32-bit, 33 MHz PCI operations (up to six PCI
devices or slots).
• Interface to the memory controller (Intel chipset) via the Direct Media Interface (DMI) link.
• An Alert Standard Format (ASF) 2.0 systems management controller for network
manageability.
• Intel High Definition Audio (Intel HD Audio) interface with support for three external codecs.
• Intel Quiet System Technology (four TACH signals and three PWM signals)
• Simple Serial Transport (SST) Bus and Platform Environmental Control Interface (PECI).
SST provides a single-wire 1 MB/s serial bus for easier board routing and the flexibility to
place sensors where needed.
• Supports up to two Serial Peripheral Interface (SPI) devices as an alternative for the BIOS
flash device; an SPI flash device can be used as a replacement for the Firmware Hub.
• Low Pin Count (LPC) interface for support of a Super I/O chip (diskette, serial, parallel,
keyboard, mouse functions), optional ASICs, and flash BIOS.
• Systems Management Bus (SMBus) 2.0 with additional support for I2C devices.
Processor
DMI Interface
USB 2.0 Power management
(supports 12 ports,
dual EHCI controller) Clock generation
SATA (6 ports)
System Management
(TCO)
Intel High Definition
Audio CODEC(s) Intel ICH10
SMBus 2.0/I2C
PCI Express x1
SPI Flash
GLCI
Intel Gigabit
Ethernet PHY Slots
LCI
PCI Bus
GPIO
LPC interface
Other ASICs
(optional)
Super I/O
Trusted
Platform Module Firmware
(optional) Hub
ICH10R
The Intel 82801JIR I/O Controller Hub 10 (ICH9R) [“R” stands for RAID] supports all the features
of the ICH10 Base plus the following features:
• Supported with G41, G43, G45, P43, and P45 chipset.
• The ICH10R provides support for Intel Matrix Storage Technology, providing both AHCI and
integrated RAID functionality. The industry-leading RAID capability provides high-
performance RAID 0, 1, 5, and 10 functionality on up to six SATA ports. Matrix RAID
support is provided to allow multiple RAID levels to be combined on a single set of hard
drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot spare
support, SMART alerting, and RAID 0 auto replace. Software components include an Option
ROM for pre-boot configuration and boot functionality, a Microsoft Windows compatible
driver, and a user interface for configuration and management of the RAID capability of
ICH10R.
RAID 0 Volume
S0 S2 S1 S3
S4 S6 S5 S7
S8 SA S9 SB
RAID 1 Volume
S0 S1 S0 S1
S2 S3 S2 S3
S4 S5 S4 S5
Disk 0 Disk 1
P1-4 S1 S2 S3 S4
S5 P5-8 S6 S7 S8
S9 S10 P9-12 S11 S12
S13 S14 S15 P13-16 S16
S17 S18 S19 S20 P17-20
Physical disks for data and parity (S1 through S20 represent sectors of data from one
file. P1 through P20 represent the parity of sectors S1 through S20).
RAID-5
1 2 3
4 5 6
7 8 9
Note: In data capacity, n refers to the number of equally sized disks in the array.
RAID Also known as Fault tolerance Redundancy type Hot spare option Disks required
0 Striping No None No 1 or more
1 Mirroring Yes Duplicate Yes 2
Striping with distributed
5 Yes Parity Yes 3 or more
parity
Striping across multiple
10 Yes Duplicate Yes 4 or more
RAID-1 arrays
ICH10D
The Intel 82801JID I/O Controller Hub 10 (ICH8D) [“D” stands for Digital] supports all the
features of the ICH10 plus the following features:
• Supported with corporate-oriented Q43 chipset.
• Integrated Trusted Platform Module (TPM) security chip.
• Support for DASH 1.0 and Intel Active Management Technology (IAMT) 3.5 for client
manageability when used with the supported Intel Ethernet controller.
ICH10DO
The Intel 82801JIO I/O Controller Hub 10 (ICH10DO) [“DO” stands for Digital Office] supports
all the features of the ICH10 plus the following features:
• Supported with corporate-oriented Q45 chipset.
• Integrated Trusted Platform Module (TPM) security chip.
• Support for DASH 1.0 and Intel Active Management Technology (IAMT) 5.0 for client
manageability when used with the supported Intel Ethernet controller.
• Support for Intel vPro Technology.
Chipsets:
Mobile Intel 965 Express Chipset Family (Notebook)
• GM965 (integrated graphics), PM965 (discrete graphics)
• Intel Core 2 Duo processor support for notebooks
• (Graphics) Memory Controller Hub
- Dual-channel DDR2 533 or 667 MHz memory
- Integrated graphics (Graphics Media Accelerator X3100)
or discrete graphics (via PCI Express x16)
• I/O Controller Hub 8M (ICH8M)
Processor
- PCI Express x1 for ethernet, PCI Express Memory and graphics
ExpressCard, Intel Turbo Memory x16 graphics controller
- Serial SATA support MCH or
ExpressCard GMCH Memory
• Announced May 2007 host bridge
Memory
Intel Turbo
Memory Ethernet
PCIe controller
I/O PCI controller
PCI Express x1 Controller SATA controller
The Mobile Intel Hub IDE controller
GM965 Express 3 SATA ports (ICH8M)
USB controller
Chipset is used in
select Lenovo Super I/O USB 2.0
notebooks such as High Definition
the ThinkPad R61. Low Pin Audio
Count interface
© 2008 Lenovo
CRT Channel A
DDR2
533/667 MHz
LVDS interface Intel
GM965
GMCH
TV out Channel B
DDR2
533/667 MHz
SDVO (2 ports)
DMI
Interface
USB 2.0 Power management
10 ports, 480 Mb/s
Clock generation
GPIO
CardBus
ExpressCard controller
controller
Ethernet
SPI BIOS
Intel Turbo Memory LPC interface
Other ASICs
(optional)
Super I/O
TPM
(optional) Flash BIOS
Channel A
DDR2
533/667 MHz
PCI Express x16 Intel
PCI Express PM965
x16 Graphics MCH
Channel B
DDR2
533/667 MHz
DMI
Interface
USB 2.0 Power management
10 ports, 480 Mb/s
Clock generation
GPIO
CardBus
ExpressCard controller
controller
Ethernet
SPI BIOS
TPM
(optional) Flash BIOS
Chipsets:
Mobile Intel 965 Express Chipset Versions (Notebook)
Chipsets:
I/O Controller Hub 8M (ICH8M) for 965 chipset (notebook)
ICH8M ICH8M-Enhanced
No Intel AMT support Intel AMT support
GL960, GM965, PM965 GM965, PM965
Six PCI Express x1 ports Six PCI Express x1 ports
Three Serial ATA ports (SATA300) Three Serial ATA ports (SATA300)
One ATA-100 controller One ATA-100 controller
(two ports) (two ports)
Ten USB 2.0 ports Ten USB 2.0 ports
Gigabit Ethernet controller Gigabit Ethernet controller
(MAC layer) (MAC layer)
No integrated RAID Integrated RAID 0 or 1
May 2007 May 2007
I/O Controller Hub 8M
(ICH8M)
© 2008 Lenovo
96x chipset
New ICH8M Features
• Intel Active Management Technology 2.5 Management
• Intel Management Engine Engine
The Intel I/O Controller Hub 8M (ICH8M) and ICH8M-Enhanced were announced May 2007.
Features of the chip include the following:
• ICH8M-Enhanced supports Intel Active Management Technology 2.5. The Intel Management
Engine via the controller link between the Memory Hub and ICH provides communication for
this function.
• ICH8M-Enhanced supports RAID 0 and 1.
• Six PCI Express x1 ports (OEM can configure between one and six x1 slots including one x4
slot). ExpressCard slots are supported through this interface.
• Three Serial ATA controllers to support two 300 MB/s Serial ATA (SATA300) ports.
• One IDE controller supporting ATA-100/66/33 and PIO modes; the one controller supports
two devices (ports).
• Five USB 2.0 controllers, each supporting two ports and with a maximum of ten total ports.
• Integrated Gigabit Ethernet controller (LAN Connect Interface (LCI)) MAC layer; it requires
an Intel family PHY layer or compatible chip for complete Ethernet functionality.
• PCI 2.3-compliant controller with support for 32-bit, 33 MHz PCI operations.
• Interface to the memory controller (Intel 96x chipset) via the Direct Media Interface (DMI)
link.
• Intel High Definition Audio (Intel HD Audio) interface with support for three external codecs.
• Low Pin Count (LPC) interface for support of a Super I/O chip (security chip, serial, parallel,
keyboard, mouse functions), optional ASICs, and flash BIOS.
• ACPI 2.0 power management logic support.
• Systems Management Bus (SMBus) 2.0 with additional support for I2C devices.
• Enhanced DMA controller, interrupt controller, and timer functions.
• Serial Peripheral Interface (SPI) as an alternative for the BIOS flash device; an SPI flash
device can be used as a replacement for the Firmware Hub.
The ICH8M-S Enhanced is the same as the ICH8M Enhanced except it is a smaller physical size
(smaller package size, package height, and ball pitch).
Processor
(G)MCH
Memory
Intel
Management
Engine
DMI Controller
Interface Link
USB 2.0 Intel
Management Power management
10 ports, 480 Mb/s Engine
Clock generation
GPIO
CardBus
ExpressCard controller
controller
Ethernet
SPI BIOS
Chipsets:
Mobile Intel 4 Series Express Chipset Family (Notebook)
• GL40, GS45, GM45, PM45
• Intel processor support for notebooks
• Integrated graphics (Graphics Media Accelerator 4500M or 4500MHD)
or discrete graphics (via PCI Express x16)
or switchable graphics
• (Graphics) Memory Controller Hub
- Dual-channel DDR2 or DDR3 memory
Processor
• I/O Controller Hub 9M (ICH9M) PCI Express Memory and graphics
- ICH9M x16 graphics controller
MCH or
- ICH9M-Enhanced ExpressCard GMCH Memory
host bridge
- ICH9M-SFF-Enhanced Memory
Intel Turbo
• Announced July 2008 Memory Ethernet
PCIe controller
I/O PCI controller
PCI Express x1 Controller SATA controller
The Mobile Intel GM45 Hub IDE controller
Express Chipset is 4 SATA ports (ICH9M)
USB controller
used in select Lenovo
notebooks such as Super I/O USB 2.0
the ThinkPad R500 High Definition
Low Pin Audio
Count interface
© 2008 Lenovo
CRT Channel A
DDR2 or DDR3
667/800/1066 MHz
LVDS interface
Intel GM45
GMCH
TV out
Channel B
PCI Express x16 DDR2 or DDR3
2 SDVO ports 667/800/1066 MHz
DMI
HDMI/DVI
Interface
PCI Express x1
USB 2.0 Intel ICH9M
12 ports, 480 Mb/s PCI Express x1 WLAN/WiMax
Other ASICs
(optional)
Super I/O
TPM
Channel A
PCI Express x16 DDR2 or DD3
2 SDVO ports
533/667/1066 MHz
Intel
HDMI/DVI PM45
MCH
DisplayPort Channel B
DDR2 or DDR3
Discrete graphics 533/667/1066 MHz
DMI
Interface
PCI Express x1 ExpressCard controller
PCI Express x1
PCI Express x1
USB 2.0 Intel ICH9M
12 ports, 480 Mb/s PCI Express x1 WLAN/WiMax
Other ASICs
(optional)
Super I/O
TPM
Chipsets:
Mobile Intel 4 Series Express Chipset Versions (Notebook)
Chipsets:
I/O Controller Hub 9M (ICH9M) for Series 4 chipset (Notebook)
ICH9M ICH9M-Enhanced
No Intel AMT support Intel AMT support
GL40, GM45, PM45 GM45, PM45
Six PCI Express x1 ports Six PCI Express x1 ports
Four Serial ATA ports (SATA300) Four Serial ATA ports (SATA300)
Integrated security chip (TPM) Integrated security chip (TPM)
12 USB 2.0 ports 12 USB 2.0 ports
Gigabit Ethernet controller Gigabit Ethernet controller
(MAC layer) (MAC layer)
No integrated RAID Integrated RAID 0 or 1
July 2008 July 2008
© 2008 Lenovo
4 Series
chipset
Management
Engine
The Intel I/O Controller Hub 9M (ICH89M), ICH9M-Enhanced, and ICH9M-SFF-Enhanced were
announced July 2008. Features of the chip include the following:
• ICH9M-Enhanced and ICH9M-SFF-Enhanced support Intel Active Management Technology
4.0. The Intel Management Engine via the controller link between the Memory Hub and ICH
provides communication for this function.
• ICH9M-Enhanced and ICH9M-SFF-Enhanced support RAID 0 and 1.
• Six PCI Express x1 ports (OEM can configure between one and six x1 slots including one x4
slot). ExpressCard slots are supported through this interface.
• Four Serial ATA controllers to support four Serial ATA (SATA 3.0Gb/s) ports.
• Six USB 2.0 controllers, each supporting two ports and with a maximum of 12 total ports.
• Integrated Gigabit Ethernet controller (LAN Connect Interface (LCI)) MAC layer; it requires
an Intel family PHY layer or compatible chip for complete Ethernet functionality.
• PCI 2.3-compliant controller with support for 32-bit, 33 MHz PCI operations.
• Interface to the memory controller (Intel 4 Series chipset) via the Direct Media Interface
(DMI) link.
• Integrated security chip (Trusted Platform Module); it can be disabled via a strapping option.
• Intel High Definition Audio (Intel HD Audio) interface with support for three external codecs.
• Low Pin Count (LPC) interface for support of a Super I/O chip (security chip, serial, parallel,
keyboard, mouse functions), optional ASICs, and flash BIOS.
• ACPI 2.0 power management logic support.
• Systems Management Bus (SMBus) 2.0 with additional support for I2C devices.
• Enhanced DMA controller, interrupt controller, and timer functions.
• Serial Peripheral Interface (SPI) as an alternative for the BIOS flash device; an SPI flash
device can be used as a replacement for the Firmware Hub.
The ICH9M-SFF-Enhanced is the same as the ICH9M-Enhanced except it is a smaller physical size
(smaller package size, package height, and ball pitch).
Processor
(G)MCH
Discrete graphics Memory
Intel
Management
Engine
DMI Controller
Interface Link
Intel
Management PCI Express x1 ExpressCard controller
Engine
PCI Express x1 Intel Turbo Memory
PCI Express x1
PCI Express x1
USB 2.0 Intel ICH9M
12 ports, 480 Mb/s PCI Express x1 WLAN/WiMax
Other ASICs
(optional)
Super I/O
TPM
Summary:
Bus Architecture
© 2008 Lenovo
Review Quiz
Objective 1
1. What 16-bit bus was common a decade ago and is considered the original PC bus?
a. ISA (or AT bus)
b. Micro Channel
c. EISA
d. PCI
Objective 2
2. What is the most common implementation of PCI in desktop and notebook systems?
a. 32-bit at 33 MHz for 132 MB/s
b. 64-bit at 66 MHz for 528 MB/s
c. 64-bit at 100 MHz for 800 MB/s
d. 64-bit at 133 MHz for 1064 MB/s
4. What is the latest version of PCI that also includes support for low profile PCI adapters?
a. PCI 1.0
b. PCI 2.0
c. PCI 2.3
d. SATA300
Objective 3
Objective 4
Objective 5
8. What standard for external devices supports transfers at up to 480 Mb/s or 60 MB/s using small
cables and requires no IRQ settings?
a. Universal Serial Bus (USB)
b. PCI 2.2
c. Point Enabler
d. JEIDA
9. What interface uses ultra-wideband (UWB) radio technology for the connection of home
consumer products to a PC or TV?
a. Wireless USB
b. FireWire 800
c. CardBus Plus
d. Serial Peripheral Interface
Objective 6
11. What is the name of the CardBus slot with a USB 2.0 signal passed to it so that USB-based
ExpressCard modules can be used in a PC Card slot with an adapter?
a. ExpressCard/54
b. CardBus Plus
c. CardBus ExpressCard
d. Serial Peripheral Interface
Objective 7
12. What is the name of the chip that consolidates many I/O functions needed by a system and
interfaces with the Memory Controller Hub?
a. South Bridge
b. XA-32
c. Super I/O
d. I/O Controller Hub (ICH)
14. Which desktop-based Intel chipset only uses discrete graphics through a PCI Express x16
adapter?
a. G41
b. G45
c. Q45
d. P45
15. What I/O Controller Hub is used with the desktop-based Intel Q45 Express chipset?
a. ICH8
b. ICH9
c. ICH9M
d. ICH10
16. Which desktop chipset with support for a high-performance PCI Express x16 graphics adapter
would be the best choice for the corporate stable segment?
a. Intel X48 Express Chipset
b. Intel Q45 Express Chipset
c. Intel G45 Express Chipset
d. Intel P45 Express Chipset
17. What mainstream desktop chipset has support for integrated graphics controller with Intel Clear
Video Technology and an available PCI Express x16 graphics slot?
a. Intel X48 Express Chipset
b. Intel Q45 Express Chipset
c. Intel G45 Express Chipset
d. Intel P45 Express Chipset
18. What is an important difference between the older notebook I/O Controller Hub 8M (ICH8M)
and the new ICH9M?
a. The ICH9M includes an integrated security chip
b. The ICH9M supports authentication to a WiMax network
c. The ICH9M is integrated in the processor
d. The ICH9M supports two PCI Express x16 slots
Answer Key
1. A
2. A
3. A
4. C
5. B
6. D
7. A
8. A
9. A
10. B
11. B
12. D
13. D
14. D
15. D
16. B
17. C
18. A
PC Architecture (TXW102)
Topic 5:
Storage Architecture
© 2008 Lenovo
Objectives:
Storage Architecture
© 2008 Lenovo
Storage Architecture
IBM invented the disk drive in 1956. The first disk drives were the size of two large refrigerators
and held 5 MB. It cost $10,000 per MB.
The platter(s) of disks typically spin about 100 miles per hour.
1 GB of data is equivalent to 1,500 paperback novels. An areal density of 1.44 billion bits per
square inch is equivalent to 87 college textbooks (1 inch=25.4 mm). 5 GB is equivalent to 50 years
of a typical daily newspapers, one million printed pages, and a stack of paper 62 stories tall.
A 500 GB disk holds 125 hours of high-definition video, 178 feature-length non-HD movies, or
125,000 four minute songs.
Disk Subsystem
• Common disk
controllers PCI Express slots
PCI Express MCH or Memory
- Enhanced IDE (EIDE) x16 slot GMCH
Host Bridge
PCIe
- Serial ATA (SATA)
IDE controller
PCIe
- Serial Attached SCSI (SAS) SATA controller
PCI 2.0 I/O
- Fibre Channel Controller 2 EIDE
Hub disks
SCSI
- iSCSI over 10G ethernet 4 SATA (ICH)
EIDE optical
disks
Firmware USB
PCI 2.0 slots Super I/O Hub
© 2008 Lenovo
Disk Subsystem
The disk subsystem consists of a disk and a disk controller (also called disk interface). Common
disk controllers today include Enhanced IDE (EIDE), Serial ATA (SATA), Serial Attached SCSI
(SAS), Fibre Channel, and iSCSI over 10G ethernet.
Disk Subsystem:
Disk Functions
RPM
© 2008 Lenovo
Disk Functions
The main storage of data in a computer is on a magnetic disk (hard disk or hard drive). A magnetic
disk stores the on and off bits of binary data as microscopic magnetized needles on the surface of
the disk. This data can be recorded and erased any number of times. When computer power is
turned off, the data remains stored on the disk.
Disk speeds are often measured in average access time, which is the sum of the average seek time
and average latency.
Seek time is the time required for the read/write head to be positioned on the correct track of the
disk. Measurements are in milliseconds (ms). A faster seek time yields better performance.
Sometimes the term track-to-track seek time is used. It defines the time that it takes the device to
move the read/write head from one track to another. Typical seek times today vary from 5 ms to 12
ms. For living room entertainment disks, seek time is not critical. A slower seek time will reduce
noise and power.
Latency is the time (measured in milliseconds) required for the intended sector on a track to come
under the read/write head. Average latency is determined by rotational speed. Usually, the figure for
latency is the time it takes the drive to do half of a rotation. A shorter latency is better for the
performance. Today, seek times are almost at the same level as latency, but latency occurs more
often than seeks, so latency has a bigger influence on the total performance. Latency is becoming the
factor that has the biggest influence on the performance.
Rotation speed is the speed at which the disk rotates. The higher the rotation speed, the faster the data
can be moved to and from the disk. Measurements are in revolutions per minute (rpm). The rotation
speed determines the latency of the drive. Common rotation speeds of a disk is 5400, 7200, 10,000,
and 15,000 rpm. An increase in rotation speed reduces latency and improves seek time. The
maximum rotation speed of a device of a certain size is limited. For example, a 3.5-inch device can
run at about 10,000 rpm at the most before the reliability of the device becomes questionable. To get
a higher speed, a smaller device form factor is needed. A 2.5-inch disk is able to have a much higher
speed than a larger disk.
• 4200 rpm disks have a 7.1 ms latency
• 5400 rpm disks have a 5.6 ms latency
• 7200 rpm disks have a 4.17 ms latency
• 10,000 rpm disks have a 2.99 ms latency
• 15,000 rpm disks have a 2.00 ms latency
Sustained transfer rate (STR) is the average rate at which the hard disk makes data available to the
host system. For example, the IBM Ultrastar 36Z15, which is an Ultra160 SCSI disk, has an STR
between 36.6 and 52.8 MB/s. The IBM Ultrastar 146Z10, which is an Ultra320 SCSI disk, has a STR
between 33.9 to 66.7 MB/s. STR assumes the disk is always available. STR is sometimes called the
internal formatted transfer rate.
Media transfer rate (MTR) is faster than sustained transfer rate. It determines how fast a device can
move data between the media and its sector buffer. The MTR depends on the rotation speed and on
the density with which data is stored. (If a sector takes up less space on the disk, it can be read
faster.) It is usually measured in megabytes per second (MB/s). MTR is usually the bottleneck in the
data transfer rate of the disk subsystems of today. Compared to the speed of the system bus of the
host system and the speed for transporting data across the cabling, this rate is the lowest.
Disk Components
A disk is made up of several components, each with parts of its own. These components can include:
• Head disk assembly (HDA), which consists of:
– A number of disks on which data is stored
– A motor to rotate the disks
– A head to read and write data (The heads "fly" over the surface of a disk at a height of two to
three micro inches; a human hair is 3000 micro inches.)
– An actuator to move the heads over the disks
• Printed circuit board (PCB), which consists of:
– A microprocessor unit to control the operation of the HDA and to communicate with the disk
subsystem controller
– Servo circuitry to position the actuator exactly
– A read/write channel to transform the electrical signals between a format that can be accepted by
the host system and a format that can be accepted by the disk
– A disk subsystem cable connector
Platter
Track
Cylinder
Sector
Each disk is segmented into tracks. Tracks are about 300 millionths of an inch apart. Each track is
divided into sectors. A sector is the smallest addressable unit on a direct access storage device and
usually contains 512 bytes of data. The figure shows the layout of a disk; the example shows a disk
with five tracks. Each track usually contains at least 32 sectors, but the number of sectors per track
varies.
A cylinder is made up of all the tracks that are at the same location of each platter in the device. The
figure shows a device that has four disks. The white rings in each platter indicate a specific track.
The white rings compose a cylinder.
When data that is larger than one track is read or written to a device that has multiple platters, a head
change is required to continue reading or writing. Although changing to another head can be done
quickly, the time required may be long enough to miss the first sector of the track on the next platter.
If the first sector is missed, the head has to wait almost a complete rotation before it can continue. To
prevent this situation, a technique called track skewing can be implemented. Today's devices are fast
enough to be able to use track skew of one or two.
When data that is larger than one cylinder is read or written, the read/write head(s) need(s) to be
moved to an adjacent cylinder to continue reading or writing. Although moving to another cylinder
can be done quickly, the elapsed time might be long enough to miss the first sector of the track on the
next cylinder. If the first sector is missed, the head will have to wait almost a complete rotation before
it can continue. To prevent this situation, cylinder skewing can be implemented.
Areal density is defined as how tightly information is packed together on a medium. Increasing
capacity per platter results in fewer parts, lower power consumption, lower heat, and lower sound
generation. Increasing areal density increases performance in that the head reads bits quickly as more
pass under the head in the same amount of time; a lower speed disk could outperform a higher speed
disk.
As shown in the diagram, when track skewing is implemented, the first sector of the next disk is
located at a further location on the platter. When sector 8 of track 1 on platter 1 has been read, the next
sector to be read is sector 1 of track 1 on platter 2. In the example, the disk subsystem has as much
time to perform the head change as it takes the disk to rotate one sector.
When cylinder skewing is implemented, the first sector of the next cylinder is located at a further
location on the disk. When sector 8 of track 1 has been read, the next sector to be read is sector 1 of
track 2. In the example, the disk subsystem has as much time to move the head to track 2 as it takes
the disk to rotate two sectors. Today's devices are fast enough to be able to use a track skew of one or
two.
The following terms are often used to describe availability:
Mean time data loss (MTDL) defines the average time until data loss occurs. When data loss occurs,
the lost data is no longer available to the end user.
Mean time between failures (MTBF) is the average time (measured in hours) between consecutive
failures of a component. It is a term often misinterpreted as a figure indicating the average lifetime of
a component.
Servo information is magnetic patterns on the disk platter that the disk uses to position the read/write
heads accurately at the proper location on the platter for read/write operation.
Disks with encoded servo design place servo information inside the data sectors (on all the tracks).
Doing so eliminates constraints of storing servo information between data sectors (sometimes called
embedded servo). The older dedicated servo technique reserves an entire side of a platter for only
servo information.
Zone-bit recording (or zoned recording) allows the device to better use the available disk space by
adding more sectors to the outer tracks of a device in order to store more data.
3 4
2 5
2 3
1 1 4 6
Zone-Bit Recording
12 8 5 7
11 7 6 8
10 9
Disk Subsystem:
Disk Terminology
Disk Terminology
Perpendicular magnetic recording (PMR) – Introduced in 2006, perpendicular magnetic recording
(PMR) is a new recording method that aligns the magnetized bits perpendicular (vertically at 90
degrees) to the surface in contrast to the longitudinal (horizontal) parallel method. PMR essentially
aligns the magnetized particles like dominoes standing on end. PMR increases the areal density by
as much as 10 times so disks can store more data on every platter. PMR requires the development
of new disk media, heads, and electronics.
Media surface
S N N S S N N S
Media surface
S N S N S N S N
N S N S N S N S
Additional layer
• ThinkPad Roll Cage – The ThinkPad Roll Cage is a protective magnesium frame featured on select
ThinkPad notebooks that provides shock protection to the disk and other notebook components.
Hard
Drive
Magnesium Frame Protected
by HDD
Protection
Pack
System
Planar
ThinkPad Roll Cage Protection
• Hard Disk Drive Shock Absorber – The Hard Disk Drive Shock Absorber was introduced in select
ThinkPad notebooks in 2003. It helps to absorb some shock to the disk by allowing the connector
to float in a range of 0.5mm.
Clearance
0.5 mm
Up
Up!
Clearance
Down
Down! 0.0 mm
• Drive Fitness Test (DFT) is a technology that uses a PC-based program that accesses special disk
microcode and enables OEM system manufacturers and service providers to accurately diagnose
the proper operation of hard disks. DFT is designed to address problem situations in which end
users suspect hard drive malfunction. The DFT program can be integrated into the system
diagnostic package and preloaded by system OEMs into a special, protected partition on the hard
drive. DFT can then be invoked by the end user (for example, by pressing Ctrl+Alt+X), possibly at
the direction of the system OEM telephone support staff. DFT is supported in both IDE and SCSI
disks.
DFT microcode automatically logs significant error events, such as hard errors and a history of all
reassigned sectors; this log is kept in a reserved area of the drive. Also, DFT microcode performs
mechanical analysis of the disk in real time. Parameters such as disk shift, servo stability, and
repeatable runout (RRO) can be calculated dynamically by reading the position error signal (PES)
of the servo and analyzing the patterns in the PES. It also uses SMART to predict imminent failure.
DFT software is stand alone in that it runs under DOS in a manner independent of the end-user
operating system.
• Automatic defect reallocation identifies and remaps defective sectors with good sectors in real
time.
• SMART (Self-Monitoring, Analysis, and Reporting Technology) is an industry-standard
specification for disks that allows the monitoring of disks for reliability and impending disk drive
failures. (It is similar to Predictive Failure Analysis; PFA is a superset of SMART). Disks meeting
this specification monitor such factors as spindle performance and error rates. Software can
interrogate the disk at any time to see if any error conditions exist. SMART cannot predict disk
failures caused by electronic connectors and integrated circuits. Approximately 60 percent of disk
failures are predictable.
• The look-ahead buffer reads additional data ahead of the data currently requested and stores it in
the fast buffer memory.
• The segmented look-ahead buffer divides the total amount of buffer memory into smaller buffers
so that data from more than one read can be stored at a time.
• Adaptive buffering allows the disk to adjust the number and size of the buffer segments when the
disk logic determines that the buffer hit rate can be increased.
• Write caching uses the disk buffer for writes (and reads) in order to increase throughput. The disk
signals completion of the write when it is received in the buffer and before it is written to the disk.
The system then does other work while the disk writes the data.
• An asynchronous device must acknowledge each byte as it comes from the controller. Synchronous
devices may transfer data in bursts, and the acknowledgments happen after the fact. The latter is
significantly faster than the former, and most newer devices support this mode of operation. The
adapters negotiate with devices on the SCSI bus to ensure that the mode and data transfer rates are
acceptable to both the host adapter and the devices. This process prevents data from being lost and
ensures error free data transmission.
• Hot-swap disks can be removed and/or inserted without tools while the system is powered on. An
example of a server with multiple hot-swap bays for hot-swap disks is shown. Most servers have
hot-swap bays for hot-swap disks. Disks can be hot-swappable with appropriate connector,
enclosure, bus, and controller support.
• Some commands take a relatively long time to complete (for example, a seek command takes
roughly 10 ms). With this feature, the controller can disconnect from the bus while the device is
positioning the heads (seeking). When the seek is complete and data is ready to be transferred, the
device arbitrates for the bus and reconnects with the controller in order to transfer the data. This
process allows a more efficient use of the available SCSI bandwidth. If the controller held onto the
bus while waiting for the device to seek, the other devices would be locked out. This process is
sometimes referred to as overlapped operations or multithreaded I/O on the SCSI bus.
• Notebook disks are typically 2.5 inches wide (but small notebooks are using 1.8 inch, 1.0 inch, or
0.85 inch disks) and are generally classified by one of the following three heights:
– 17 mm
– 12.5 mm
– 9.5 mm
Plastic is used for the disk rail on select ThinkCentre desktops that is thicker and
stronger than flimsy metal for added durability.
Disk Subsystem:
Active Protection System
The Active Protection System contains both a hardware and a software component. The hardware
(accelerometer) detects acceleration of the system where speed is increasing, or accelerating. This
hardware signals the software component identifying movement. The accelerometer chip measures
the tilt in the system and uses the information that comes from the tilt to try and predict when a
shock event will occur. The accelerometer has an absolute maximum shock rating of 3000 Gs.
The software component is the thinking portion of the protection system. This software makes a
decision on whether the movement is potentially harmful to the system or if it is normal, repetitive
motion. It decides whether or not to turn off the hard disk drive.
If a ThinkPad system is going to fall off a table, it will tilt before it falls. The accelerometer will
detect the tilting and falling, then the software will interact to protect the hard disk drive by parking
the hard disk drive head within 500 milliseconds.
At any time, you can see the status of the Active Protection System through the real-time on-screen
status under the Properties window. This feature allows the customer to see a graphical picture of
the state of their Active Protection System.
Disk Subsystem:
Flash Memory with Disks
© 2008 Lenovo
A Windows Vista feature, ReadyBoost, is a read cache that allows Windows to cache memory pages
onto flash memory (such as on a USB drive, Secure Digital Card, Compact Flash, Intel Turbo
Memory) that will not fit into main memory. Because a removable flash device could be removed at
anytime, unique data cannot be stored on it, and data is encrypted for security reasons.
ReadyBoot uses the ReadyBoost services to speed up the boot processes and recover from
hibernation by building a temporary cache of the main files needed during boot.
The final solution is ReadyDrive, a write cache that can cache portions of Windows Vista to facilitate
faster boot up and resume times. 30% boot time savings can be expected using ReadyDrive and
during normal operations, data retrieved from the cache will be transferred two to three times as fast
as from a disk.
Disk Subsystem:
Full Disk Encryption (FDE)
Hardware-based encryption
built on the disk
Better performance than
software-based encryption
Secures all data by
encrypting every bit of data,
including the OS, swap
space, and temporary files
Encryption transparent to
user
Encryption keys are bound to
hard disk password Lenovo ThinkPad
200GB FDE Disk
Requires system to have
BIOS support
Security with
encryption
© 2008 Lenovo
Disk Subsystem:
Solid State Drives
Density 80 GB 64 GB
SSD Performance
SSD drives are good at random read operations which is the basis for claims that boot times and
program loads for some applications are faster. However, the write process for SSD drives is
complicated because large blocks must be erased before data can be written. SSD wears out with
many writes, so the controller in an SSD must move data around so all of the memory locations see
similar numbers of writes.
2007 112 1%
2008 146 5%
Disk Subsystem:
Serial Attached SCSI (SAS)
• Serial (not parallel) link
• Used in workstation and servers SATA SCSI/SAS
mostly with disks 1.5 Gb/s
3 Gb/s
3 Gb/s
- Large capacity 15K rpm disks
No Dual Port Dual Port
• Supports SATA and SAS devices Half Duplex Full Duplex
• Uses the SCSI command set 7200 rpm 10,000 – 15,000 rpm
• Many cabling options Low duty cycle Highest duty cycle
10x5 operation Server and
• Used in select Lenovo networked storage
ThinkStation systems
24x7 operation
3.5
inch and
3.5 and 2.5 inch
mobile SATA
© 2008 Lenovo
Performance 320 MB/s (Ultra320 SCSI); performance degrades 3.0 Gb/s, roadmap to 12.0 Gb/s; performance
as devices added to shared bus maintained as more drives added
Compatibility Incompatible with all other drive interfaces Compatible with Serial ATA (SATA)
Max. cable length 12 meters total (must sum lengths of all cables 8 meters per discrete connection; total domain
used on bus) cabling thousands of feet
Cable form factor Multitude of conductors adds bulk, cost Compact connectors and cabling save space, cost
Device identification Manually set, user must ensure no ID number Worldwide unique ID set at time of manufacture;
conflicts on bus no user action required
Termination Manually set, user must ensure proper installation Discrete signal paths enable devices to include
and functionality of terminators termination by default; no user action required
Device 1
- Do not mix slow and fast devices
on the same cable
• Typically 100 MB/s data transfer speed
and called ATA-100
2 Connectors for IDE
Devices
© 2008 Lenovo
The ATA Packet Interface (ATAPI) is a standard designed for devices such as CD-ROMs and tape
drives that plug into an ordinary ATA (IDE) port. ATA-4 was released in 1998 and added a queuing
function that allows disks to take multiple commands and perform them in the sequence that is most
mechanically efficient.
The maximum cable length for IDE and Enhanced IDE is 18 inches. This restriction confines IDE
devices to be internal only.
On each IDE connector, one IDE device is the primary (master), and the other IDE device is the
secondary (slave). The primary/secondary designation is determined by switch or jumper settings on
each IDE device.
There is no performance impact between a master and slave of the same type on the same IDE
connector. A bootable IDE disk can be a master or a slave.
Primary
IDE Primary IDE Cable
Interface
Disk Subsystem Controller Disk Subsystem Controller
Disk Disk
Secondary
IDE Secondary IDE Cable
Interface
Disk Subsystem Controller Disk Subsystem Controller
Host
System CD-ROM Device Tape Device
ATA-66
In 1998, Quantum announced the ATA-5 (ATA/ATAPI-5, Ultra ATA/66, ATA-66, and Ultra DMA
Mode 3 or 4) interface, which supports up to 66 MB/s transfers. Chipset support began in 1999. The
interface provides enhanced data integrity with improved timing margins and use of CRC data
integrity. It uses a 40-pin, 80-conductor cable instead of the previous 40-pin, 40-conductor cable to
lower electromagnetic interference. The additional 40 conductors in the 80-conductor cable are
dedicated to "signal ground" functions to reduce signal cross-talk. Yet it retains the 40-pin connector,
which has been used on PCs since the original IDE connector. Aside from the different cable, the
new standard is fully backward compatible with previous IDE, EIDE, or ATA drives. A system with
an ATA-66 interface can read and write any IDE, EIDE, or ATA drive that has been made. Similarly,
a drive with an integrated ATA-66 controller can be used on older IDE interfaces, through drives
attached to slow controllers will slow to the slowest speed. Older cables may still be used with an
ATA-66 controller; however, only Ultra DMA/33 mode or slower operation is supported; this can be
detected by a new cable sense pin, which is detected by systemboard logic.
80-conductor cables have color-coded connectors. A two-drop cable has a black connector for the
master device, a gray connector for the slave device, and a blue connector for the systemboard. A
one-drop cable has a black connector for the master device and a blue connector for the systemboard.
Because ATA-66 has a faster transfer rate over the cable, having the master and slave in optimum
position reduces the risk of errors from reflection and delays for two devices on the cable.
The specification implements two modes: Ultra DMA mode 3, providing up to 44 MB/s transfer rate,
and Ultra DMA mode 4, providing 66 MB/s.
ATA-100
In 2000, the ATA-100, ATA/100, or Ultra ATA/100 specification was released which supports 100
MB/s transfers through the IDE interface. It requires the same 40-pin 80-conductor cabling as ATA-
66. It basically has the same features as ATA66, and it is backwards compatible to ATA-33 and
ATA-66. Both the disk and the controller (such as the ICH2) need to support ATA-100 for the 100
MB/s speed.
ATA-133
In 2002, Maxtor introduced ATA-133 which provides 133 MB/s data transfer rates. ATA-133 is
not expected to gain wide acceptance because Intel and many leading disk and chipset vendors are
focusing on the expected successor to ATA-100, which is Serial ATA. ATA-133 disks became
available in 2002, but Intel-based chipset systems require an add-in PCI adapter with an ATA-133
controller. Via Technologies supports ATA-133 in some of its chipsets.
Power Cable
The base SATA transfers at 150 MB/s or 1.5 Gb/s over a 7-pin interface. SATA is clocked at
750 MHz with two samples per clock so it transfers at double data rate on rising and falling
edges of clock. Because the data width is one bit, this feature provides a data rate of 1500
mega-samples or 150 MB/s bandwidth. The specification also defines a 300 MB/s or 3 Gb/s
(3,000 MHz clocking) followed by a 600 MB/s or 6 Gb/s (6,000 MHz clocking) transfer. It
supports full duplex operation (support to send and receive data at the same time); IDE only
supports half duplex transmission.
To ensure rapid adoption, SATA products are 100% software compatible with the existing
ATA protocol and current operating systems, so no new changes or drivers are needed to
existing operating systems. SATA devices can be mixed with EIDE (parallel ATA) devices in
the same system.
SATA is primarily for inside-the-box drive connections with a maximum cable length of one
meter. The cables are thinner (about 8 mm wide) than EIDE cables so they are smaller and
more flexible. The smaller cables allow better ventilation, access, and visibility inside a system.
SATA uses point-to-point connectivity for significant performance and reliability advantages
over the shared connectivity approach employed by both the ATA and SCSI parallel interfaces.
Each port on a Serial ATA controller serves just one device; that is, the controller
communicates with a given drive only through the port where it is connected. Any SATA
device is treated as a master device, so there are no jumper settings or slave devices. Because
there is no sharing of the bus, each drive can communicate directly with the system at any time.
As a result, the entire available interface bandwidth is dedicated to each device. This dedicated
link approach eliminates the arbitration delays sometimes associated with shared bus
topologies. With a shared bus approach, overhead increases as drives are added to the shared
bus. This means that, in a typical ATA or SCSI RAID system, adding a disk will increase the
total system throughput by some amount less than the throughput of the disk. With Serial ATA,
on the other hand, each added disk can deliver its maximum throughput. Point-to-point
connectivity offers the added benefit of simpler configuration. Dedicated links make a Serial
ATA RAID system easy, fast, and relatively inexpensive to set up. Less complex trace runs on
systemboards permit smaller systemboards.
Cyclical Redundancy Checking (CRC) error detection is standard in SATA as each protocol
layer has the capability to identify errors and can perform recovery and control actions as well
as forward information to the next higher layer in the stack.
SATA supports hot-plugging, the ability to swap out a failed disk drive without having to
power down the system or reboot. This capability contributes to both data availability and
serviceability, without any associated downtime. The Serial ATA 1.0 specification requires
staggered pins for both the hard disk drive and drive receptacles. Staggered pins mate the power
signals in the appropriate sequences required for powering up the hot-plugged device. These
pins are also specified to handle in excess of the maximum allowed inrush current that occurs
during drive insertion.
Serial
2.5”
power data
Serial
3.5”
power data
EIDE ATA-100
3.5”
Serial ATA Power Cable (Left) and Signal Cable (Right) Serial ATA Hot-plug Disk
The basic Serial ATA connector design is a remarkably efficient and practical design offering a
number of notable features/benefits:
• Plugs are blind-mated (can plug them in blindfolded without making an error).
• The “L” shaped Serial ATA data and power connectors make plug orientation very obvious
to the end user, and prevent incorrect mating.
• The extrusion has “ears” which guide and align the plug during the mating process.
• The conductors are engineered for hot-plugging; they connect in three stages–first pre-charge,
then ground, then power.
• The connector locations on the back of 2.5” devices are the same as for 3.5” devices,
allowing design of backplanes that can accommodate either size device.
The Serial ATA standard is a simplified packet switching network between a systemboard and
a disk drive (or any SATA device). It employs balanced voltage (differential) amplifiers and
four wires/two pairs (transmission line) to connect transmitters to receivers in a manner similar
to the 100BASE-TX Ethernet. The pins in the spec are labeled TX+, TX-, RX+, and RX- just
as they are in the twisted-pair Ethernet. There is no specification for a standard Serial ATA
cable (just electrical requirements it must meet), but each pair of wires is usually parallel and
shielded.
SATA devices use a separate power cable. They require power connectors with +12, +5, and
+3.3 volts. Current 4-pin ATX-type power supplies provide only driver power connectors with
the traditional +12 and +5 volt signals, so a PC may need a power supply fitted with SATA
drive power connectors or an adapter.
Serial ATA is supported in RAID implementations.
See the Serial ATA International Organization (SATA-IO) Web site at www.sata-io.org for
more information.
EIDE Cable (Left) vs Serial ATA Cable (Right) EIDE Cable (Left) vs Serial ATA Cable (Right)
Serial ATA
Interface
Connector
Serial ATA
Power
Connector
EIDE cables are bulky and SATA cabling is thinner and allows
get in the way. cleaner design.
Lenovo 160 GB Serial ATA Hard Disk Drive (part number 09N4254)
Serial ATA:
SATA300 or SATA 3.0 Gb/s
© 2008 Lenovo
• External multi-lane datacenter cable and connector solution for connecting multiple Serial ATA
channels between chassis in a datacenter
The Intel ICH7 family was announced in May 2005 with full support for the SATA specification.
Later Intel I/O Controller Hubs continue to support both the original SATA 1.5 Gb/s speeds and the
new SATA 3.0 Gb/s speeds.
The Serial ATA International Organization (SATA-IO) is an independent, non-profit organization
developed by and for leading industry companies. Officially formed in July 2004 by incorporating
the previous Serial ATA Working Group, the SATA-IO provides the industry with guidance and
support for implementing the SATA specification.
For more on SATA technologies and the SATA-IO, visit www.sata-io.org.
Serial ATA:
External Serial ATA (eSATA)
Systemboard
External SATA storage
© 2008 Lenovo
External SATA port cable (both Low Profile bracket Rear view shows bracket with eSATA in one slot
for Desktop and Full Height bracket on supported Lenovo ThinkCentre Tower
for Tower)
Disk Performance:
Cache Position
Disk Disk
Controller Cache
© 2008 Lenovo
If the speed of a processor, L2 cache, memory, and disk were equivalent in units related to each
other, a 1 ns processor cycle (a single cycle for 1 GHz) would be equivalent to 120 days for a single
access (10 ms) of a disk, because there is a difference of a million between a nanosecond (ns) and
millisecond (ms). A nanosecond is a billionth of a second, and a millisecond is a thousandth of a
second.
Disk Performance:
Cache
© 2008 Lenovo
Disk Performance:
Factors in Disk Performance
Media
Disk request Command Seek transfer
to controller decode time Latency rate
or
.002 ms 1 ms 12 ms 6.6 ms .073 ms
© 2008 Lenovo
Disk Performance:
Many Factors of Disk Throughput
Width of Bus
Type of Controller Size of Disk Buffer
Device Driver Type of Buffer
Type of Bus
Width of Bus
Data Transfer Rate
© 2008 Lenovo
The throughput figures assume constant numbers of sectors per track. (This assumption tends to be
a somewhat unrealistic expectation.)
Drive geometry, data density, speed of electronics, and innovative technique in the drive controller
and firmware can significantly influence performance. More data per track (more sectors per track)
yields better performance. Track-to-track seek time affects performance (0.9 ms track-to-track seek
time outperforms 2.2 ms).
Summary:
Storage Architecture
© 2008 Lenovo
Review Quiz
Objective 1
2. Many Lenovo ThinkPad notebooks utilize a ThinkVantage Technology that has a motion sensor
and software utility system that protect the hard disk drive from damage due to a fall or rough
handling. What is the name of this ThinkVantage Technology?
a. Access Connections
b. Active Protection System
c. Embedded Security Subsystem
d. ThinkVantage System Update
3. What disk technology provides a new recording method that aligns bits at 90 degrees to the
surface so that disk capacities are increased significantly?
a. Femto slider
b. Hard Disk Drive Shock Absorber
c. Perpendicular magnetic recording
d. Active Protection System
Objective 2
Objective 3
7. Desktops such as Lenovo ThinkCentre desktops primarily use what disk interface?
a. SCSI
b. Fibre Channel
c. Enhanced IDE
d. Serial ATA
8. Which is the second-generation Serial ATA technology and what is the transfer speed?
a. PCI Express, 200 MB/s
b. USB 2.0, 300 MB/s
c. SATA 3.0 Gb/s, 150 MB/s
d. SATA 3.0 Gb/s, 300 MB/s
Objective 4
10. What difference in disk performance does software and/or hardware disk cache on EIDE and
SCSI disks make?
a. Reduction of disk performance because of overhead caused by looking through cache
b. Little difference in performance
c. 10 percent increase in disk performance
d. Two to four times faster than if no cache is available
Answer Key
1. B
2. B
3. C
4. A
5. A
6. B
7. D
8. D
9. B
10. D
11. A
PC Architecture (TXW102)
Topic 6:
Graphics Architecture
© 2008 Lenovo
Objectives:
Graphics Architecture
© 2008 Lenovo
© 2008 Lenovo
Graphics Overview
This topic will cover the many parts that make up the graphics subsystem. The diagram shows a
high-level overview of what is covered in this topic.
The main memory of a PC contains the applications and associated code for the appropriate
images. To view the interface of applications, the appropriate calls must be transferred from
memory to the graphics controller. The graphics controller utilizes its own memory or the main
system memory to create the exact color of each pixel on the monitor in a digital binary format.
The graphics controller also drives the digital-to-analog converter (DAC), so the signal is converted
to an analog signal that a CRT monitor can understand. Some monitors accept digital signals, so the
graphics controller does not have a DAC.
Many characteristics of monitors vary from product to product.
Device Driver
© 2008 Lenovo
Graphics Processing
There are three elements to graphics processing: the graphics controller, the monitor, and the video
device driver. All three of these elements must support the specific resolution and refresh rate
desired. Examples of the limitations inherent in these graphics processing elements include:
• Graphics controller limitation – Say that a given monitor supports a resolution of 1280x1024, but
it has an older graphics controller that supports only a maximum resolution of 1024x768. The
monitor can only support the lower resolution of the graphics controller. Some graphics
controllers may only have the newer DVI connector in one of its forms which could limit its
attachment to older monitors.
• Monitor limitation – Say that an older monitor supports a resolution of only 1024x768 at 72 Hz,
but it has a newer graphics controller is capable of supporting a maximum resolution of
1600x1200 at 85 Hz. The monitor can only support the lower resolution in this case as well.
Some monitors may only accept a digital signal instead of the traditional analog signal, in which
case it will be physically impossible to connect them. Monitors are migrating to the newer DVI
connectors from the 15-pin D-sub connector.
• Device driver limitations – It is also possible for a monitor’s resolution to be limited by its device
driver. Newer device drivers can be installed to support greater resolution, more simultaneous
colors, and better performance.
The terms video controller and graphics controller are often used interchangeably, but video more
accurately reflects full motion video. Video actually means television in the form of NTSC or PAL
video.
1024
• Resolution refers to how many
pixels can be addressed on the
display horizontally and vertically.
Addressability
The terms resolution and addressability are often used interchangeably. The correct technical
definitions are as follows:
• Addressability is the number of pixels that can be addressed on the display horizontally and
vertically.
• Resolution is the clarity of the final image. It is a function of addressability and memory quantity.
However, the industry uses the term resolution to mean addressability, so the term addressability is
rarely used.
All monitors have the same minimum resolution of VGA (640 by 480). Monitors support different
resolutions. Better quality premium units have a clearer, sharper picture than cheap, entry-level
units.
Video information always goes to the display on a pixel-by-pixel basis as the raster lines are
scanned. The distinctions between text mode and graphics mode are in the system and the software,
not in the display.
Aspect Ratio
The ratio of width to height of an object. It states the relationship of one side to the other. For
example, the aspect ratio of the screen of a standard computer monitor is 4:3, which is a rectangle
that is somewhat square. The "4" means four units wide, and the "3" means three units high.
Another way of expressing this ratio is 1.33:1.
Viewing Angle
Viewing angle is the maximum angle at which a display can be viewed with acceptable definition.
The viewing angle is measured from one direction to the opposite, giving a maximum of 180° for a
flat, one-sided screen.
Example of a 130 degree viewing angle; Example of a 178 degree viewing angle;
beyond 65 degrees horizontal or vertical is 89 degrees horizontal or vertical is readable
blurry
Common Resolutions
This table shows commonly used resolutions of monitors, also known as graphics mode. Graphics
mode is when the software generates the image on a pixel-by-pixel (not character-by-character) basis.
Less common resolutions are the following:
• 320x240 QVGA (Quarter VGA); for cell phones
• 3840x2400 QUXGA-W (Quarter-UXGA Wide)
• 1280x768 or 1366x768 or 1440x990 WXGA (1280x1024 is 16:10 aspect ratio)
• 1600x900 WSXGA (1600x1024 is 16:10 aspect ratio)
• 16:9 and 16:10 – The most accurate representation of video content for Blu-ray, games, and
digital TV is 16:9 (not 16:10). 16:9 provides a narrower image than 16:10 which makes the image
taller.
Text Mode
Software uses two visual modes: text mode and graphics mode.
• Text mode
– PC software generates the image of the display on a
character-by-character basis rather than a pixel-by-pixel
basis.
– This mode is used only for character-based applications (DOS, full
screen DOS applications, diagnostic programs). The screen
is divided into 25 rows by 80 columns, so each character
occupies a 9-by-16 pixel.
– Common addressability of text mode:
• 720x350 (25 rows by 80 columns)
• 720x400 (25 rows by 80 columns)
• 720x400 (50 rows by 80 columns)
1600×1200 1 MB 2 MB 4 MB 6 MB
1800×1440 2 MB 4 MB 8 MB 8 MB
Text mode (720 by 350 and 720 by 400) requires only 4 KB per frame.
Color Table
© 2008 Lenovo
Graphics Controller
The functions of a graphics controller (sometimes known as a graphics processing unit [GPU]) are
summarized as follows:
The GPU processes commands from the main processor, converting graphics calls into a data
stream to be written into graphics memory (the frame buffer) prior to being sent out to the monitor.
In the frame buffer, the screen image is laid out and stored according to the horizontal and vertical
grid, depicting the 2D resolution on the screen. Then, the DAC (or RAMDAC) converts the digital
pixels to the RGB (red, green, blue) analog signal needed by the CRT monitor.
The speed of the DAC determines the maximum refresh rate possible at a given screen
addressability. For example, a 250 MHz DAC can drive an 80 Hz maximum refresh rate at 1920 by
1080 addressability, while a 220 MHz DAC would drive the same addressability
at 75 Hz.
Graphics controllers have had increased performance over time because they have migrated from
32-bit to 64-bit to 128-bit to 256-bit graphics accelerators. In other words, the internal processing of
the commands and data is done with a 32, 64, 128, or 256-bit wide engine. Generally, the wider the
engine, the better the performance. For the graphics engine to utilize its 128- (or 256-) bit capability
fully, it needs to obtain data from memory at the same bit width. Increasing the width of this data
path increases both the cost and complexity of the processor, as well as the amount of memory that
is required.
A 128-bit graphics controller needs a 128-bit data path, while a 256-bit graphics controller needs a
256-bit data path; otherwise, multiple transfers are needed. For example, a 128-bit controller with a
32-bit memory path would need four transfers before it received its 128 bits of data. The type of
memory architecture (SDRAM, DDR2) and packaging (DIMM, embedded) play a role in the
transfer, and, therefore, the performance.
The graphics processing unit (GPU) acts as a second processor to a system because it plays an
extremely important role in system performance. The GPU has become a coprocessor to the main
processor by taking on more tasks and relieving some of the tasks from the main processor. GPUs
provide tremendous floating-point performance and are highly programmable and parallelizable;
parallelizable means it can break up tasks into smaller pieces and run each piece simultaneously.
GPUs handle 3D acceleration, physics calculations, and video transcoding (converting from one
video format to another). Video transcoding on a GPU can process from four to eight times faster
than a high-end, dual-core processor.
• Typical implementation
- Notebook
Integrated (in Graphics Memory Controller Hub)
Discrete (chip using PCI Express x16)
Switchable (both integrated and discrete)
- Desktop
Integrated (in Graphics Memory Controller Hub) Integrated Graphics for
Desktop (Intel G45 Graphics
Discrete (PCI Express x16 adapter) Memory Controller Hub)
• Integrated graphics uses main system memory
- Low cost and widely used
• Discrete graphics uses its own memory
- Higher cost with best performance
Notebooks utilize either integrated graphics or discrete graphics. Notebooks using the Intel 8xx
chipsets with discrete graphics typically use the AGP 4X bus with graphics controllers from
typically either NVIDIA or ATI. Notebooks using the Intel 9xx chipsets with discrete graphics use
the PCI Express x16 bus with graphic controllers from NVIDIA or ATI.
Desktops utilize either integrated graphics or discrete graphics also. Desktops using the Intel 8xx
chipsets with discrete graphics typically use the AGP 8X bus with graphics controllers from either
NVIDIA or ATI. Desktops using the Intel 9xx or later chipsets with discrete graphics typically use
the PCI Express x16 bus with graphics controllers typically from NVIDIA or ATI.
Switchable Graphics
Switchable graphics is a hardware/software feature that allows the user to maximize battery life or
maximize performance by switching between integrated graphics or discrete graphics based on
AC/DC state or user initiation.
The switch is made dynamically (such as switching from AC power to a battery on a notebook) or
manually (via a hot-key or software dialog). This feature only works on Windows Vista.
Exceptions:
• Running an OpenGL application
• An application in exclusive mode
• System is connected to a DisplayPort or DVI monitor
Switch time:
• Switch time from discrete graphics to integrated graphics: 2 seconds
• Switch time from integrated graphics to discrete graphics: 5 seconds
No reboot is required to make the switch. A unified driver is used in this environment as there are
not different drivers for each controller.
ThinkPad X61 Intel GMA X3100 in GM965 Integrated Uses main memory
ThinkPad T61p NVIDIA NVIDIA Quadro FX 570M PCI Express x16 256 MB
ThinkCentre A61 ATI ATI Radeon X1250 Integrated Uses main memory
ThinkCentre M57 Intel GMA 3100 in Intel Q35 Integrated Uses main memory
VGA
DVI-D
© 2008 Lenovo
DOS had only a 640×480 by 16-color driver; each DOS application needs its own driver. However,
under Windows, one driver supports all Windows applications. (i.e., a separate driver is not needed
for each application.)
Color depth and addressability can be adjusted in the Display Properties window in Windows OSes,
as shown below:
© 2008 Lenovo
2D versus 3D Colors
The difference between 2D and 3D colors is that some memory is used up for a Z buffer in 3D.
The maximum number of colors is determined by the size resolution and how much memory the
graphics card has. For 2D, there is no Z buffer. When 3D is enabled, Z information must be
kept for each pixel, and 3D reduces the number of colors that can be seen in each resolution.
The calculation that determines how much memory is needed is as follows:
memory = [(resolution x * resolution y) * (bytes of color depth + Z buffer depth)].
So, for 1024 by 768 at 16 million colors and 16-bit Z buffer: memory=[(1024*768) + (3 bytes +
2 bytes)] = 3.9 MB.
Another aspect that may be seen on high-end 3D cards is double buffering. If double buffering
is enabled, there are two frame buffers in memory, i.e., the bytes of color depth term in the
equation above will double and cutting down on the maximum colors available in a given
resolution. Double buffering increases the number of frames drawn per second.
Running 3D applications requires more memory than 2D applications. When a user starts a 3D
application (usually games), the addressability and color depth reduces automatically without
giving an error message. Most 3D applications support 640 by 480 with 256 colors to maintain
compatibility with 3D controllers with a minimum of 2 MB. When the application exits, the
original settings are restored.
When an application utilizing 3D is loaded, the software queries the system to see if the appropriate
level of 3D support is present. If the proper support is present, the application utilizes hardware-
assisted acceleration; otherwise, slower software acceleration is used (the processor itself must
recalculate each 3D object). The application cannot mix hardware acceleration for some functions
and software emulation for others; it is all one way or the other.
3D Graphics
The term 3D graphics implies displaying an image from all sides, providing an illusion of depth
with motion. With the emergence of Microsoft Direct3D API and many new 3D-capable, low-cost
chipsets, developers of games, business software, and VRML Web browser plug-ins are using 3D
graphics with increased frequency. 3D graphics bring advanced workstation graphics to the PC,
speeding both two-dimensional and three-dimensional graphics. The result is more realistic
graphical representations; pictures are more detailed, and animation is more fluid. Using 3D
graphics, a software program may allow you to walk through a room or race a car. The faster the
PC processes the graphics, the more smoothly and realistically things appear as you view the
changes.
3D acceleration is necessary for the computation-intensive graphics found in today's games. There
are few business applications that use 3D (even the 3D chart function in Microsoft Excel is handled
by software). Business applications run smoothly with 2D support, e.g., waiting for a screen to
refresh or Microsoft Word to scroll down a page is 2D.
3D combines geometry engines, texturing, and shading with motion. Graphics controllers may have
3D acceleration, which is not the same as a 3D hardware engine. A 3D hardware engine is what
gives high-performance 3D. 2D graphics refers to tasks such as scrolling, moving windows, and
opening dialog boxes (including 3D bar charts and DVD decoding). CAD and solid modeling
programs are not really 3D in that their goal is to produce a single instance of an object, although
the underlying geometry, surface textures, and colors of that object may be included in an
animation program.
Some of the more important features of 3D chips include Z buffering (defined in the definitions
section), lighting, texture mapping, and rendering. These basic tasks can be further enhanced with
various texture-mapping options and special rendering features. 3D chips vary as to what functions
they support.
Lighting is an important part of the 3D process because you have to tell the computer how an object
or scene is going to be lit – there is no automatic or inherent lighting. And it would be difficult if
not impossible to make an object look three dimensional without it. The shadows, color shading,
reflections and other effects that result from the virtual light source are essential to making it look
realistic.
Texture mapping involves triangles. In order to make pictures on a PC seem to have three
dimensions (height, width, and depth), the screen is divided into triangles. The triangles may be of
any size, and the sides may be of the same lengths or different lengths. The more triangles, the more
detailed the scene can be. A big, flat wall, for example, may be drawn as two huge triangles, while
a picture on that wall may consist of many tiny triangles. Texture mapping is the way the creator of
the scene paints each triangle with a pattern or texture.
Rendering is the process by which an object, after it has been designed and defined geometrically,
is actually represented on the monitor. In other words, the 3D representation
of the object or scene must be turned into a 2D set of pixels that are “painted” onto a display screen.
The rendering process takes into account all the (virtual) lights that affect the particular image being
rendered. Three common rendering processes are ray tracing, radiosity, and scanline rendering.
The creation of a 3D image starts with a wireframe skeleton, which comprises polygons and is
stored as a complex mathematical model. Because these models are three-dimensional, an object
can be rotated to any point of view and can be manipulated in many ways. To make the wireframe
appear solid, it is then dressed with color, texture, and light. Each of these stages requires additional
processing power, because each time the model is changed, the calculations need to be redone.
In late 1999, mainstream 3D graphics chips began to integrate transform and lighting (T&L)
calculations from the main processor to the graphics chip. Commonly called T&L acceleration, this
acceleration increases the performance of the 3D images.
There are several components to the 3D pipeline. (The pipeline is what assembles all the
information and transfers it to the monitor.) These components include: transforms, lighting, setup,
and rendering. Transforms consist of the mathematical calculations used to determine translation
(movement), rotation, and other changes in objects. Lighting calculations determine how a scene
and its various objects are illuminated. (When we speak of lighting in this context, we mean
geometrically calculated light sources, not light maps, which are special texture maps that simulate
lighting effects.) Texture coordinates are then assigned, and the objects are deconstructed into
triangles and vertex data (vertices are the corners of polygons – typically triangles) and sent to the
setup engine. Setup is the process by which vertex data generated by the transform and lighting
steps is translated into data formats suitable for pixel generation. The final step is rendering, in
which pixels are actually created, properly shaded, and colored for display in the frame buffer. It's
at this point that the actual texels (texture elements) from the various textures are blended into the
colors of the base object's pixels to create each pixel's final color.
3D Graphics Definitions
•Alpha blending allows one object to show through another and provides the illusion of
transparency. Color keying is a different way of providing transparency.
•Anisotropic filtering is a technique to improve the look of texture images that are viewed at an
angle.
•Anti-aliasing helps clean up jagged edges at seams between mapped textures by using
transitional pixels of blended colors. It works by blending the color of each pixel with the
color of others around it.
• Bilinear and trilinear filtering averages the nearest points in the texture to calculate a point in the
triangle rather than selecting the nearest point and results in smoother pictures and less jagged
lines. (Textures must be scaled to fit the triangle to which they are being mapped.)
• Bump mapping is giving a surface relief texture by changing its colors and shadows, depending
on the implied intensity and direction of the light hitting the surface.
• Double buffering – The Windows XP interface is single-buffered, meaning that one screen
update is painted on top of the last. But 3D graphics use a rendering method called page flipping,
in which graphics memory is allocated so it contains two full screens. The first is called the front
buffer. The back buffer contains the screen information for the next frame or 3D animation.
When content in the back buffer is ready to be displayed onscreen, the 3D card does a page flip,
swapping the buffers. Now what was the back buffer is onscreen as the front buffer. And what
was the front buffer becomes the back buffer, where it is cleared for the next frame of animation.
This technique also goes by the term double buffering.
• Fogging is used to make objects appear fuzzy and adds realism to scenes with fog or those scenes
in which an eerie feeling is implied. It can also be used for blurring distant objects.
• MIP mapping allows several versions of a texture to be used, depending on the nearness of the
object. Closer objects appear sharper to the eye and need more detailed texture. More distant
objects appear fuzzier and need less detailed texture.
• Perspective corrected texture mapping automatically maps the surface texture of each triangle on
an object to the perspective. As an object turns or moves forward or backward in a scene, the
perspective drawing of the object needs to change for visual correctness. Closer points on the
object must appear larger, and further points become increasingly smaller.
• A polygon is a shape defined by lines; a polygon must have at least three lines (sides). On a
polygon, the point where the lines connect is called a vertex.
• Reflection mapping is accurately drawing reflections of objects in glass, water, metal, and other
reflective surfaces.
• Shaders – Small programs that operate on individual pixel and vertex data to create impressive
3D effects. DirectX 8 and DirectX 9 give developers commands for building custom shader
programs.
• Shader Model 3.0 – In 2005, the Microsoft DirectX 9 interface introduced an advanced
programming model called Shader Model 3.0. This model permits a simpler programming style
for game developers and allows better performance. Games written to this model need DirectX 9
version 9.0c or later. Games utilizing Shader Model 3.0 will still run on graphics controllers that
do not support this interface; these games normally have many ways of rendering animations and
use the one that works best for the controller. The NVIDIA 6800 line of graphics controllers
support this interface.
• Smooth shading (or Gouraud shading) allows color shading and brightness to change gradually
across each triangle. Across real objects, colors and brightness change gradually. Without smooth
shading, there would be a sharp transition between triangles, giving a blocky appearance (called
flat shading).
• Specular highlighting shows the reflection from a light source or the surface of an object.
• Transparency allows two surfaces to be blended for effects such as looking through window glass
or seeing through smoke.
• T-Buffer A T-Buffer (developed by 3dfx) holds multiple rendered frames before they are
displayed on your monitor. (An ordinary graphics chip stores only one image in its frame buffer,
swapping that screen with the one that is currently being displayed.) When enough screens are
stored up, the T-Buffer blends them together to eliminate the jagged edges that can sometimes
appear. The new image is then rendered on-screen.
• Z-buffering tracks the depth of the vertices of each triangle from the perspective of the viewer
and sorts the triangles to ensure that the objects that fall in front are the only ones drawn. 24-bit z-
buffering provides 24 distinct levels of depth for each pixel, and 32-bit z-buffering provides 32 of
these levels. The greater the bit depth, the more precise the indication of depth.
3D Benchmarks
3DMark05 is the first benchmark to require a DirectX 9.0-compliant hardware with support for
Pixel Shaders 2.0 or higher. 3DMark05 is the answer to the continuously growing challenge in
benchmarking. Visit www.futuremark.com for more information.
3DMark06 is the latest version in the popular 3DMark series, including advanced SM2.0 and
HDR/SM3.0 Shader graphics tests and now including single, multiple core, and multiple processor
CPU tests as part of the 3DMark score.
3DMarkMobile06 is a robust OpenGL ES 1.0 and 1.1 benchmark that tests 3D graphics
performance of future mobile 3D hardware. High-detail game content generates workloads that tax
OpenGL ES 3D hardware in a realistic way. Visit www.futuremark.com for more information.
© 2008 Lenovo
DirectX 10
• DirectX 9 – Released in 2003, a Microsoft API for Windows used to produce realistic 3D
functions. DirectX 9 includes a High Level Shader Language. As of 2004 only high-end graphics
support DirectX 9; high-end game software also supports DirectX 9.
• DirectX 10 – DirectX 10 was released in 2007 with support only in Windows Vista. In previous
versions, programmers used separate languages to write pixel shaders and vector shaders. In
DirectX 10, there is a common language, reducing a programmer's development time. This
allows for up to 64,000 instructions in a shader program, as opposed to 512 instructions in
DirectX 9. New also are geometry shaders, which allow the graphics processor to create or
destroy geometry programmatically on the fly, something that previously was done on the
processor.
Direct3D10 is the graphics rendering part of the DirectX10 API and allows developers to take
better advantage of the DirectX 10 capabilities of AMD’s latest Radeon HD 2000 Series of
products
DirectX 9 DirectX 10
Shader Model 2.0/3.0 4.0
Temporary Registers 32 4096
Constant Registers 256 65,536
Multiple Render Targets 4 8
Textures 16 128
Maximum Texture Size 4096 x 4096 8192 x 8192
Resource Validation Required on every use Required only on creation
Geometry Shaders No Yes
Unified Shader Instruction Set No Yes
Stream Output No Yes
Alpha to Coverage No Yes
Constant Buffers No Yes
State Objects No Yes
Texture Arrays No Yes
Integer & Bitwise Operations No Yes
Comparison Sampling No Yes
Render to Volume No Yes
Multiple Resource Views No Yes
Shared Exponent HDR Format No Yes
© 2008 Lenovo
Pixel/Character Relationship
As resolution increases, more information can be displayed in greater detail (more pixels per inch),
but the information shrinks the image in size rather than making the same size image crisper. The
text size on a 17-inch display may be adequate at 1024×768, but it would be too small to be read
easily with 1600×1200 resolution. The Windows Control Panel allows some changing of type size,
but most text and application text can not be altered easily.
The following characteristics are true, on the same display:
• At 800×600, characters are 20 percent smaller than they are at 640×480.
• At 1024×768, characters are 37 percent smaller than they are at 640×480.
• 1024×768 shows 2.5 times more information than 640×480 (many more spreadsheet numbers).
• A 17-inch display provides almost 50 percent more viewing area than a 14-inch display.
• A 19-inch display provides almost 84 percent more viewing area than a 14-inch display.
The actual viewable area is smaller than the stated size of a display. CRTs do not produce a picture
edge-to-edge, so a 17-inch display typically yields a 15.5-inch viewing area.
• A typical 14-inch display is about 10.4-inch wide; at 800×600 that is 77 dots per inch.
• A typical 17-inch display is about 12.8-inch wide; at 1024×768 that is 77 dots per inch.
© 2008 Lenovo
Multiple Monitors
A PC can support multiple monitors. Typically, in a multiple monitor situation, most users will
have two monitors, but it is possible to have more than two monitors.
There are two different types of multiple monitor support: cloning or multi-monitoring. There are
no formal names for the various ways that multiple displays can be used. Each graphics vendor has
its own unique (and usually trademarked) names. The term multi-monitoring is becoming common
for using multiple monitors.
• Cloning – Cloning (or dual display clone) means that the same image appears on both displays.
Cloning is only really useful if two groups of people need to see the same image, such as in
training situations. The second output can be redirected to a large TV or video projector. Each
display device can be configured independently, allowing each to have a different refresh rate,
color depth, and resolution for optimum display on each device.
• Multi-monitoring – Multi-monitoring means the desktop addressability is increased so that it fills
all monitors. For two monitors, this is often called dual independent display. If each monitor is
set to 1024×768, then two desktops would be 2048×768. Multi-monitoring means that each
monitor can see different applications or windows on each monitor. Spanning or wide desktop is
another term for maximizing a window to fill both displays when the system is set up for dual
display, which is an expanded desktop that stretches across the two monitors. NVIDIA calls this
TwinView, a term that they trademarked. Intel calls this feature Extended Desktop.
• Users get more pixels for the money with two smaller (17-inch) monitors
than with one larger (20-inch) monitor
- Two monitors are less costly (even with cost of additional graphics card).
- A dual-head graphics card or additional graphics card is required.
• Users are more productive and have fewer errors with multiple monitors.
Two 17-inch SXGA monitors side by side: One 20-inch UXGA monitor:
© 2008 Lenovo
• Nearly one-third of users felt they became more productive in each task faster when using more
than one monitor.
You can even have two monitors on a single stand. Almost all desktop flat panels can be detached
from their stands and attached to stands that use VESA-standard mounting brackets.
The operating system must support multiple monitors. Windows 98, Windows Millennium Edition,
Windows 2000, and Windows XP Professional all support multiple monitors. Windows must be
configured to use two or more monitors. In Windows XP, right-click an open area of your Desktop
and choose Properties from the pop-up menu, then the Settings tab. If you have two monitors,
click the second and check Extend my Windows desktop onto this monitor.
Some dual-head or other graphics adapters have their own software utilities for setting up and
configuring multiple monitors. These utilities normally offer more features than the base function in
Windows XP.
Multi-monitoring, dual independent display, or quad independent display: Each monitor shows an
independent or unique image.
Two Lenovo ThinkVision monitors used with Multi-monitoring helps improve productivity by
a ThinkCentre tower, which would be providing users with more information at one
positioned beneath the desk. This multi- time. This ThinkPad notebook on a ThinkPad
monitoring configuration provides the user Advanced Dock is shown with a Lenovo
with more viewable area than one larger ThinkVision monitor.
monitor, and at a comparable cost.
• Aero
- Optional interface for Windows Vista
- Adds support for 3D graphics,
translucency, window animation,
and visual effects
• Vista Aero requires:
- DirectX 9 (DirectX 10 preferred) 3-D
Windows Aero (translucency)
graphics processing unit with a WDDM driver
- 128 MB graphics memory (minimum)
- Support for Pixel Shader 2.0
- Ability to display a color depth of
32 bits per pixel
- 1 GB or more of main memory
© 2008 Lenovo
Processor
GMA X3100
Graphics Main
Memory memory
Controller Hub
ICH
© 2008 Lenovo
512 MB 128 MB 64 MB
1 GB 256 MB 251 MB
1.5 GB or more 384 MB 358 MB
The GMA X3100 supports Intel Clear Video Technology (discussed on following pages).
Graphics Main
Memory memory
Controller Hub
ICH
© 2008 Lenovo
Processor
GMA X3500
Graphics Main
Memory memory
Controller Hub
ICH
© 2008 Lenovo
512 MB 128 MB 64 MB
1 GB 256 MB 251 MB
1.5 GB or more 384 MB 358 MB
The GMA X3500 supports Intel Clear Video Technology (discussed on following pages).
Intel Graphics Core: Intel GMA 950 Intel GMA 3000 Intel GMA 3100 Intel GMA X3000 Intel GMA X3100 Intel GMA X3500
945G, 945GM 946GZ, Q963, G31, G33, G965 GM965, GL960 G35
Intel Chipset:
Q965 Q33, Q35
DirectX Support DirectX 9.0c DirectX 9.0c DirectX 9.0c DirectX 9.0c DirectX 101 DirectX 101
OpenGL Support 1.4 + Extensions 1.4 + Extensions 1.4 + Extensions OpenGL 1.5 OpenGL 1.5 OpenGL 2.0
Shader Model
2.0 2.0 2.0 3.02 4.01 4.01
Support
HD hardware Acceleration
VC-1 Decode
Supported4 No No No Yes Yes Yes
(can support (can support (can support (MC + In Loop (MC + In Loop (MC + In Loop
through software) through software) through software) Filter –WMV9 only) Filter –WMV9 only) Filter)
HD Video Playback
MPEG-2 1080p, 1080i, 1080p, 1080i, 1080p, 1080i, 1080p, 1080i, 1080p, 1080i, 1080p, 1080i,
and 720p and 720p and 720p and 720p and 720p and 720p
VC-1 1080p, 1080i, 1080p, 1080i, 1080p, 1080i, 1080p, 1080i, 1080p, 1080i, 1080p, 1080i,
and 720p and 720p and 720p and 720p and 720p and 720p
AVC/H.2646 1080i and 720p 1080i and 720p 1080i and 720p 1080i and 720p 1080i and 720p 1080i and 720p
1 DirectX 10 and Shader Model 4.0 software driver support expected in Q1 2008
2 Hardware T&L and Shader Model 3.0 software driver support expected in August 2007
3 HW accelerated MPEG-2 VLD not currently supported on Windows Vista due to OS issue (to be resolved in Vista SP1)
4 HW accelerated WMV9b/VC-1 not supported on Windows Vista until August 2007
5 HD-DVD or Blu-ray disc media playback requires the use of a third-party decoder card and appropriate software drivers
6 Ability to play back AVC/H2.64 content is dependent on system configuration, content bitrate, and resolution
Graphics Main
Memory memory
Controller Hub
ICH
© 2008 Lenovo
Monitor ports DVI, DisplayPort DVI, DisplayPort, HDMI DVI, DisplayPort, HDMI
Full hardware decode acceleration of
Hardware decode No No
MPEG2, VC1, and AVC
The Intel Graphics Media Accelerator 4500 (GMA 4500) family supports 3D enhancements for
everyday games and improved realism with support for Microsoft DirectX 10, Shader Model 4.0,
OpenGL 2.0, and HDCP key integration.
Graphics Media
GMA 4500 GMA X4500 GMA X4500 GMA X4500HD
Accelerator
Full Hardware MPEG2
No Yes Yes Yes
Video Decode
Full Hardware
Acceleration VC1 Yes No No Yes
Decode
Full Hardware
Acceleration AVC Yes No No Yes
Decode
HD Security
Yes Yes Yes Yes
PAVP/HDCP
DisplayPort, DVI, DisplayPort, DVI, DisplayPort, HDMI, DVI, DisplayPort, HDMI, DVI,
Display Interfaces SDVO Dual Independent SDVO Dual Independent SDVO Dual Independent SDVO Dual Independent
Display Display Display Display
Hi-Def resolutions 1080p/I, 720p 1080p/I, 720p 1080p/I, 720p 1080p/I, 720p
© 2008 Lenovo
Advanced Display Capability – Allows your PC to connect to a wide range of digital displays by
supporting the latest digital display interfaces, including the High-Definition Multimedia Interface
(HDMI), which carries uncompressed HD video and multi-channel audio in one cable.
For PCs using digital TV tuners, Intel Clear Video Technology adds support for Media Expansion
or ADD2 cards which enable digital display connections such as DVI and TV-out in a single-card
solution.
Visit www.intel.com/go/clearvideo for more information.
Feature Benefit
MPEG-2 decode iDCT + motion compensation. Up to 2 stream support
(1 HD and 1 SD)
Intel Clear Video Technology uses advanced hardware and software techniques
to deliver smooth high-definition playback, sharp images with fine detail, and
precise color control, enabling a premium visual experience.
It is possible to combine the two multiplexed SDVO ports to drive large (high addressability) digital
displays. When combined with a DVI-compliant external device and connector, the GMCH has a
high-speed interface to a digital monitor (e.g., flat panel or digital CRT).
SDVO ports in either single/single-combined or dual operation modes are supported with these
features:
• Each SDVO port runs at a pixel rate of 200 MP/s. The two ports can be combined to work together
as a single port with an effective pixel rate of 400 MP/s. The 400 MP/s pixel rate allows for
support of QXGA resolutions (2048×1536 pixels) at refresh rates up to 85 Hz.
• Intel SDVO ports can interface to codecs that enable support for LVDS panels, DVI-I and DVI-D
displays, standard- and high-definition televisions and CRTs.
• Analog display support.
• HDTV 720p and 1080i display resolution support.
• Each SVDO port can support a single channel device.
• If both SDVO ports are active they will have identical display timings and data.
• 400 MHz integrated 24-bit RAMDAC (200 MHz per channel).
• Hardware color cursor support.
• DDC2B-compliant interface.
• Dual Independent Display support with digital display.
• Multiplexed Digital Display Channels (supported with ADD2 Card).
• Two channels multiplexed with PCI Express x16 slot.
• 200 MHz dot clock on each 12-bit interface.
• Can combine two channels to form one larger interface.
• Supports flat panels up to 2048x1536 at 60 Hz or digital CRT/HDTV at 1920×1080 at 85 Hz.
• Supports hot plug and display.
• Supports TMDS transmitters or TV-out encoders.
• ADD2 card utilizes PCI Express graphics x16 connector.
Analog
Display
VGA
ADD2 Intel
Display
Card 910GL
915GV
SDVO
Display 915G
or 945G
PCI Express GMCH
Graphics x16 Graphics
Display
Card only in 915G
And 945G
ADD2 Adapters
Lenovo markets the following Advanced Digital Display 2 (ADD2) adapters:
• DVI-I Connection Adapter which was introduced in 2005 and has a DVI-I connector to support
either an analog or digital monitor; an analog monitor requires an optional dongle to convert the
connector to a DB-15 connector
• ADD2 DVI-D Monitor Connection Adapter (HDCP) which was introduced in 2007 and has a
DVI-D connector to support a digital monitor; it supports High-bandwidth Digital Content
Protection (HDCP) which is digital rights management to control the digital audio and video
content as it travels across the DVI interface. It ships with both a Low Profile and Full Height
bracket.
DVI
TV out
DVI-D Cable
connects to
DVI header on
Lenovo ThinkCentre A61 supporting systemboard
four monitors
© 2008 Lenovo
SurroundView
SurroundView is the AMD/ATI technology that provides low-cost multiple monitor support.
SurroundView allows the integrated graphics controller (such as the ATI Radeon X1250 or Xpress
200) to support two monitors with the addition of a single cable; a separate graphics adapter is not
required.
A supported desktop or tower can support two monitors without the use of a PCI Express x16
adapter. The first monitor uses the standard VGA connector. The second monitor is connected to a
DVI-D connector through only a cable that utilizes the integrated graphics controller. The
integrated graphics controller will drive two monitors. The second monitor is supported by
plugging in a DVI-D cable into a DVI header on the systemboard. The DVI-D cable has a DVI-D
connector on either a low profile or a full height bracket. The installed cable will prevent the use of
the PCI Express x1 slot.
SurroundView also allows a desktop or tower to support four monitors with only one ATI PCI
Express x16 graphics adapter via the following:
• An analog monitor with the standard VGA connector
• A digital monitor with an optional DVI-D Cable that plugs into a DVI header on the systemboard
and has a DVI-D connector on a bracket
• Two additional monitors via a dual-head adapter in the PCI Express x16 slot. Only ATI adapters
are supported to get four monitor support; if a non-ATI adapter is installed, the integrated
graphics is disabled.
SurroundView also will allow the dual-head adapter in the PCI Express x16 slot to not disable the
integrated graphics controller but only if an ATI adapter is used (regardless of whether a DVI-D
Cable is installed).
DVI-D
VGA
DVI header
Lenovo ThinkCentre A61 Systemboard with Lenovo ThinkCentre A61 Systemboard with
DVI-D Cable installed in DVI header to dual head graphics adapter installed in PCI
support two monitors Express x16 slot for four monitor support
© 2008 Lenovo
Processor
x16
Graphics
MCH Memory
PCI Express
PCI slots
Gb Ethernet
Serial ATA
PCI Express x1 slot ICH
USB 2.0
PCI Express x4 slot
Super I/O
Unlike the AGP slot, the PCI Express x16 slot can be used for other PCI Express adapters if a PCI
Express graphics adapter is not required.
PCI Express x16 graphics adapters are one of the following sizes:
• Low Profile (LP) – Allows the graphics adapter to fit both into Low Profile and full-height
systems. A full-height system requires a full-height bracket to be attached. Allows for customers
to choose the smallest systems and still achieve dual monitor output.
• Full-Height – Allows the graphics adapter to fit in full-height systems. Sometimes referenced as
ATX (based on ATX system motherboard design).
Processor
Memory
Controller System Memory
Hub
Aux. Memory
Interface
PCI Express x16
Auxiliary Memory
Channel
Graphics
512 MB 768 MB 1 GB 2 GB
Controller
Main Memory Main Memory Main Memory Main Memory
Memory
64 MB 128 MB 191 MB 319 MB 831 MB
128 MB 192 MB 255 MB 383 MB 895 MB
256 MB 320 MB 383 MB 511 MB 1023 MB
PCI Express:
PCI Express Graphics 150W-ATX, 225W, 300W Specifications
Uses 25 watts Uses 75 watts Uses 75 to 150 watts Uses 151 to 225 watts Uses 226 to 300 watts
Component side
Component side
reserved area
reserved area
These specifications are intended to support both workstation and consumer graphics. The
specifications do not support the optional hot-plug functionality of PCI Express CEM 1.1.
Together, PCI Express CEM 1.1 and these specifications support three distinct maximum power
levels for graphics:
• 25 watt (low profile card)
• 75 watt (standard size)
• 150 watt (76 to 150 watts)
• 225 watt (151 to 225 watts)
• 300 watt (226 to 300 watts)
These graphics cards may use the space of the adjacent expansion slot(s), thereby providing more
volume for thermal solutions and components on the primary side of the card than the standard PCI
Express add-in card which is constrained to the width of a single expansion slot. For example, a
system that supports a PCI Express x16 Graphics 150W-ATX add-in card is required to ensure that
sufficient power and thermal support exists. In an ATX form factor system, the adjacent expansion
slot can be left vacant allowing for 1.37 inches of clearance for the add-in card as illustrated in the
figure. The area on the add-in card that can utilize this height, as well as the restricted height of the
secondary side, is not defined in this specification; instead, it leverages the general PCI Express
add-in card requirements for these dimensions.
34.8 Max
[1.370]
Component side
reserved area
Systemboard
20.32 20.32
[0.800] [0.800]
55.12 mm Max
[2.170 inches
Component side
reserved area
Systemboard
20.32 20.32
[0.800] [0.800]
Monitor Features:
CRT Monitor Characteristics
0.28 mm
© 2008 Lenovo
In noninterlaced (or progressive scan) displays, each image is scanned onto the front of the CRT of
a monitor in a single pass by three electron guns that sweep line by line across the screen in
horizontal strokes. In standard television sets or interlaced monitors, a complete image requires two
scans. Most computer users should consider only noninterlaced displays, because people sit closer
to computer monitors than to televisions, from which they typically sit several feet away looking
primarily at large moving images; most of what is seen on the computer monitor is detailed, static
images like word processing text and numbers.
Scanners and monitors are RGB devices, meaning that they define all colors as mixtures of red,
green, and blue.
Due to the earth’s magnetic field, CRT monitors are manufactured to work in the northern,
southern, and equatorial regions of the earth and may not produce a satisfactory image when moved
between them. The magnetic field does not affect Flat Panel LCD Monitors and ThinkPad LCD
displays.
Monitor Definitions
Black level is the amount of brightness retained when the video signal is set for complete blackness
or zero.
Color temperature is the color tint of the white screen of a monitor (such as red or blue). It is often
measured in 6500ºK or 9300ºK.
Convergence is a measure of how accurately aligned the red, green, and blue electron guns of a
monitor are. Misaligned guns result in misconvergence and unwanted color halos around object
edges.
Degauss is demagnetization of a monitor to reduce picture distortion.
Diagonal pitch or dot pitch is the diagonal or adjacent spacing of same color phosphors, i.e., the
distance between adjacent holes in shadow mask, stripes in aperture grill, ellipses in slot mask, or
the distance between red phosphor dots. .28mm is a common dot pitch. Dot pitch is not the same as
a pixel size. Dot pitch is a physical characteristic of the display and cannot be changed.
Gray-scale shift is a measure of the change in the brightness level of gray areas on screen when
adjacent areas alternate between dim and bright states.
Horizontal dot pitch is the horizontal spacing of same-color phosphors. This term became popular
in 1998 as a way to compare different tube technologies. Previously, dot pitch referred to diagonal
dot pitch. This is a physical characteristic of a monitor and can not be changed. .24mm is a
common horizontal dot pitch.
Interlaced controllers draw images with two passes, scanning every other line on the first pass (1, 3,
5, etc.) and filling in the rest on the second pass (2, 4, 6, etc.). Interlaced is sometimes quoted as
43.5 or 87 Hz. The 43.5 Hz is for both fields (passes) to make a complete frame, and the 87 Hz is
for one field to do so. Interlacing is not used in new displays, but these new displays are interlace-
compatible for use with old graphics controllers.
1
4
2
Second scan 5 First scan
3
6
Luminance is a measure of the brightness of the monitor and is measured in foot-Lamberts (fL).
Luminance allows a monitor to produce a brighter image without bringing the black areas to gray
and thereby lowering the sharpness and contrast.
A moiré pattern is a wavy pattern resulting from a mismatch between the pattern of a shadow mask
or aperture grill and the horizontal line pattern of the image.
Noninterlaced controllers draw all lines in one pass. Noninterlacing graphics controllers and
displays are more expensive than interlaced. Most displays today are noninterlaced.
Pincushion is the curvature of a straight line on the screen. Lines at the edges of the screen tend to
exhibit more pincushioning than lines at the center because of the increased deflection of the
electron beam.
Pixel size is the exact number of phosphor dots composing the pixel; this size will vary with the
resolution and addressability (640x480, 800x600, and 1024x768). Pixel size is also called pel size.
Note: These pixel sizes are for 14-inch, 0.28mm dot pitch
0.28mm
Example:
z In VGA (640×480), each pixel is composed of more than two triads (sets of phosphor dots).
Screen regulation is the stability of the dimensions of the display area of a monitor. The screen
image on a poor quality monitor might be bowed or irregular in size or shape.
The shadow mask is a screen just inside the front glass of the display. It is drilled with small holes;
each corresponds to one triad. (It looks sort of like a window screen, or gauze material.) Its purpose
is to guide electron beams so that each beam only hits one phosphor dot in the triad.
Shadow mask
A triad refers to one of the thousands of triangles that are arranged on a computer screen in order to
produce an image. Color monitors display a combination of red, green, and blue. Each triad is
composed of three phosphor dots – one red, one green, and one blue. One electron gun is dedicated
to each of the three colors, so there are three guns in total. The beams from the electron gun move
together. As the beams scan the screen, each triad produces a single color as each gun controls the
intensity of the red, green, and blue.
Electron beams
Red
Blue
phosphor
Green Green
phosphor
Red
phosphor
Blue
Uniformity is a measure of the variance of luminance and color across the display.
Video bandwidth is the amount of data dedicated to projecting an image to a monitor. The video
bandwidth is allocated in horizontal and vertical scan rates.
Presets
Presets are a bank of memory locations with stored data (for example, picture size, position, shape)
corresponding to the most commonly used modes (addressability and refresh rates). Presets make the
geometry (picture size, position, shape) appear proportionally on the screen with a border.
In 2000, factory loads started to be used on monitors. Factory loads (also called preloads) are not
checked on all monitors, but the information the monitor needs is extrapolated from the preset
information. These have a higher tolerance on size, etc., but should produce a reasonable image. In
contrast, presets are inspected on all units in production and have a tighter tolerance for
size/position/geometry.
The microprocessor of the display detects the signal from the graphics controller and adjusts the
geometry according to the data it finds in the corresponding memory locations (presets).
A number of memory locations are available for users to store geometry settings according to their
preference (for example, a borderless geometry).
The microprocessor always checks the user memory locations first for geometry preference; if none
exists, it checks for presets. If neither exists, the geometry may appear nonproportional (odd shaped)
and need adjustment. A specific resolution and refresh rate (e.g., 800 by 600 by 256 colors at 72 Hz)
can have only one geometry saved by the user.
VESA DDC
VESA established a standard called Display Data Channel (DDC) in late 1994. This standard is also
called the Display Data Channel Command Interface (DDC/CI). The DDC specification defines how a
monitor and a system will communicate refresh rates at different resolutions, power conservation
capabilities, model number, serial number, vendor, preset modes, and other capabilities.
For the benefits of this automatic identification to be effective, the graphics hardware, BIOS, and
operating system of the system must be enabled for DDC. There are two main standards: DDC1 and
DDC2B. Most monitors and systems support DDC2B today. (DDC1 is no longer used in current
systems.)
DDC1
DDC2B
If a DDC monitor plugs into a DDC system, the system will automatically configure the display to
a high resolution and refresh rate rather than the current but outdated VGA standard. If a monitor is
not automatically detected, make certain that the following two files, which typically ship with a
monitor, are installed on the disk: *.INF (Windows Information for plug and play) and *.ICM (ICC
profile for color calibration).
The original DDC1 specification was later expanded to include two-way communication between
the monitor and graphics adapter using two pins on a standard VGA cable. This specification is
called DDC2B, and it has the added benefits of being much faster than the DDC1 specification and
of allowing the operating system to query the monitor (via the graphics adapter) to find out what
that monitors features are. A compatible graphics controller allows one to switch addressabilities
on the fly without rebooting. DDC2B allows the monitor to always support the highest refresh rate
that both the monitor and graphics adapter can support.
All major operating systems support DDC2-enabled monitors when used with DDC2-compliant
systems.
The latest version of the specification is "Display Data Channel Command Interface (DDC/CI)
Standard-Version 1.1," October 2004 (VESA document VESA-2004-10); see www.vesa.org for
more information.
Monitor Features:
CRT Monitor Tube
FD Trinitron
and
Flat Shadow Mask
© 2008 Lenovo
Aperture grill
• Trademarked Trinitron and developed by Sony Corporation.
• Cylinder is completely flat vertically and only slightly curved
horizontally.
• Uses tensioned vertical wires, called an aperture grill,
instead of a shadow mask.
• One or two horizontal wires keep vertical wires in position
and may be visible as thin lines across a light colored screen. Trinitron/Diamondtron
• Phosphor is laid in stripes (versus triad), so it is measured in
stripe pitch instead of dot pitch, which is used on most displays. Stripe pitch
• Used today in many monitors.
• In 1999, FD Trinitron was introduced (FD stands for flat display)
has a flat screen vertically and horizontally, eliminating distortion
of shapes and rendering everything accurately.
• Mitsubishi uses a similar technology named Diamondtron.
• In 1998, Mitsubishi introduced the Diamondtron NF (natural flat) R G B R
with a flat screen vertically and horizontally. Aperture Grill Mask
Flat Shadow Mask
• In 2000, Samsung introduced the Full Flat Shadow Mask.
• Uses a shadow mask.
• Flat in horizontal and vertical axis.
• Used in the ThinkVision C170 and C190.
Other CRT Monitor Tubes and Technologies Flat Display (FD) Trinitron
CromaClear Flat Shadow Mask
In 1998, monitors implementing wide deflection yoke, which use a 100-degree deflection of the
electron beam, appeared. A typical CRT uses 90 degrees from one side to the other and result in a
monitor case that is as deep as the diagonal screen measurement. A wide deflection yoke will save
about two inches of depth, so that a 17-inch monitor will have a similar footprint to a 15-inch
monitor, and a 19-inch monitor will fit a 17-inch monitor footprint.
In 1998, short-neck tube monitors that use smaller components at the electron-gun end of the
picture tube were introduced. This reduces the depth of the CRT by about an inch (slightly less than
that of a wide-deflection yoke design). A short-neck tube is not a wide deflection yoke.
Types of Masks
There are three types of masks used by monitors.
A shadow mask (dot-trio shadow mask) is a thin sheet of metal perforated
with holes that align with the phosphor dots on the front of the tube.
The spacing between the phosphor dots varies with the grade of the monitor.
It delivers clean edges and sharp diagonals; these factors are important for text.
An aperture grill, used by the Sony Trinitron and Mitsubishi Diamondtron,
uses an array of thinly stretched wires with phosphor stripes to create the Shadow Mask
screen image. The aperture grille typically has a stripe pitch of .24mm to
.28mm. It is the best choice for image and graphics work, because poorer
horizontal definition makes it less suited for text. A .24mm stripe pitch
(horizontal dot pitch) is equivalent to a .28 dot pitch. Aperture grill tubes
generally deliver richer, more saturated colors, so they are optimized for
image editing and gaming.
A slot mask, introduced by NEC in 1996 under the name CromaClear, Aperture Grill
uses elongated phosphor ovals rather than dots, delivering a crisper
image than other designs, as NEC claims. Some monitor makers
(for example, NEC) have tried to bridge the gap between shadow masks
and aperture grills by offering slot mask designs. A slot mask is
optimized for text and uses an elongated 0.25mm mask opening instead
of dots, which does not require damping wires.
Monitor Features:
Flat Panel Monitors Overview
© 2008 Lenovo
Ergonomic Stand
• Tilt
• Swivel
• Height Adjustment
Contrast ratio
Contrast ratio is the ratio between the brightest white and darkest black. The higher the contrast
ratio, the deeper and richer the coloring.
Brightness
Brightness is a measurement of light intensity produced by an LCD’s backlight measured in nits
(lumens) or candelas per meter square (cd/m2). Higher brightness produces better images
(greater readability) under high ambient light. Flat panel monitors typically average about 250
nits; CRTs typically have an average of 100 nits.
Glossy Anti-Glare
Monitor Features:
Color Gamut
© 2008 Lenovo
Gamut
Color gamut is the range of colors a monitor can display. The higher the percentage, the better.
For example, the Lenovo ThinkVision L193p has a 72% color gamut, and the Lenovo ThinkVision
L220x Wide has a 92% color gamut. The ThinkPad W700 has a 72% color gamut display.
Monitor Features:
Color Calibration
© 2008 Lenovo
Color Calibration
The aim of color calibration is to adjust the colors of one output device to match that of another.
The device that is to be calibrated is commonly known as calibration source; the device that serves
as a comparison standard is commonly known as calibration target.
Monitor Features:
CCFL vs LED Backlight
- Excellent contrast
- Thinner screens
Monitor Features:
Widescreen Monitors and Notebooks
• Widescreen
- 9% wider screen
- 16:9 or 16:10 aspect ratio
• Advantages
- See more columns of spreadsheet/database
- Allows smaller windows on the side
- Most movies widescreen format Lenovo ThinkVision L220x Wide
• Disadvantages
- Text easier to read and scroll vertically
- Notebooks hard to fit in standard carrying cases
• Lenovo offers widescreen monitors and notebooks
© 2008 Lenovo
Origin
CONTENT INCREASE
Widescreen Advantages
Following are the advantages of a widescreen monitors and notebooks:
• Users can see two windows side by side which offers productivity advantages.
• Spreadsheet and database users can see more column data at a time which reduces horizontal
scrolling.
• Many movies are produced in widescreen format so viewing movies utilizes more screen.
• The height of the screen is reduced which is advantageous in the tight area of a plane or train
so that the seat in front of you does not bump into a notebook.
• Various chat windows or sidebar applications can be placed on the side of a window instead
of directly on top of the main applications.
Widescreen Disadvantages
Following are the disadvantages of a widescreen monitors and notebooks:
• The taller screen of a standard monitor or notebook requires less vertical scrolling.
• Reading text is easier on the eyes when it is more vertically-oriented, as in a standard format.
• Standard screen notebooks fit into a backpack or carrying case better because the space is
more square
• Some Web pages or applications are fixed width so are optimized for standard screen sizes.
• Some older games are distorted or may not fill the full screen of a widescreen.
• The view heights of 22" wide and 19" standard flat panel monitors are similar
• View area: 22" wide view area is a little larger than 19" standard flat panel monitor
• Similar heights between 19” standard and 22” wide
Wide
std
std Wide
Due to shorter system depth and display height, a 14.1" widescreen system offers an increased
chance of having better display angle and palm rest position when used in airplane seating
because the widescreen provides 1.5" (3.8 cm) more space.
© 2008 Lenovo
MPR-II
MPR-II is a guideline developed by the Swedish Board for Technical Accreditation (SWEDAC) to
limit the electromagnetic emissions and electrostatic fields generated by workstations.
Electric and magnetic fields with frequencies between 5 Hz and 2 kHz are called extremely low
frequency (ELF) fields. Those with frequencies between 2 kHz and 400 kHz are called very low
frequency (VLF) fields. The Swedish MPR-II guidelines intend to limit the ELF. Sources of these
fields include the main power supply (50 or 60 Hz) from the wall socket and the circuits responsible
for sweeping the electron beam across the face of the CRT.
High voltages used within CRTs induce an electrostatic field (ESF) on the surface of the monitor
screen. The MPR-II guideline requires that this charge be minimized.
MPR-3
The draft for MPR-3 was ratified as a formal Swedish standard on November 30, 1995. MPR-3
deals with the emission levels (electrical and magnetic) of displays. The earlier MPR-I and II
documents were voluntary guidelines but were widely respected in the scientific community.
Key elements of MPR-3 include the following:
• MPR-3 was designed for all types of visual displays, not just standard CRT monitors. This is a
significant element, because not all VDTs today use CRT technology. Some VDTs use liquid
crystal display (LCD) technology. Others use electroluminescent or plasma technologies. MPR-II
was restricted to CRT technology.
• MPR-3 was expanded to contain three separate emissions categories, a slightly simplified
protocol for laboratory measurements, guidance on the assessment of measurement uncertainty,
and directions for workplace surveys.
• MPR-3 incorporates elements from guidelines developed in the US, Europe, and Japan and
represents broad participation by many groups, including Swedish government agencies, labor
unions, and large computer manufacturers.
MPR-3A is a colloquial name for Swedish Standard SS43614 90:1995.
Emissions
All electronically powered equipment emits electrical and/or magnetic fields. There is no evidence
that monitor emissions are a health risk. The following guidelines exist for monitors:
MPR-I
• Issued 1984
• MPR-I addresses:
– ESF (electrostatic fields)
– VLMF (very low magnetic fields)
MPR-II
• More restrictive = MPR-I +
• MPR-II addresses:
– ELMF (extremely low magnetic fields)
– ELEF (extremely low electric fields)
MPR-3A
• Equivalent to TCO'95
TCO'92
• Swedish Confederation of Professional Employees Guideline
• Uses a different measurement methodology than MPR-II and made compliance much stricter
with lower emissions than MPR-II
TCO'95
• Incorporated all the guidelines in TCO'92
• Ensured that the monitor incorporates ecological and environmental benefits
• Mandated that the monitor and its packaging be composed of recyclable materials
• A TCO'95-compliant monitor is Energy Star-compliant
TCO'99
• Was released in late 1998 and incorporated all the guidelines in TCO'95
• Tightened picture quality and controls, visual ergonomics and electromagnetic emissions, and
added alternative keyboard design guidelines
• Required higher image refresh rates to eliminate entirely perceived flickering
• Called for massive reductions in magnetic and electric fields, reduced heat emission to keep
humidity levels constant for the user, and reduced energy consumption
• Included various environmental improvements, such as reduced cadmium and bromide pollution
TCO'03
TCO'03 was released in late 2002 and incorporated all the guidelines in TCO'99. It tightened the
requirements in the area of visual ergonomics. See www.tcodevelopment.com for more
information.
ENERGY STAR
In 1992 the US Environmental Protection Agency (EPA) evolved its voluntary program, called
ENERGY STAR, to cover computers. The ENERGY STAR program for computers has the goal of
generating awareness of energy saving capabilities, as well as differentiating the market for more
energy-efficient computers and accelerating the market penetration of more energy-efficient
technologies. On July 20, 2007, the EPA updated the ENERGY STAR computer specification to
Version 4.0.
Power management in most Lenovo monitors follows the VESA DPMS (Display Power
Management Signaling) standard, shutting off circuitry in stages after a defined period of system
inactivity. The stages are controlled by the horizontal and vertical sync lines on the incoming video
signal, as shown on the chart above.
Most Lenovo monitors utilize the VESA DPMS protocol software to execute the power saving
stages. The power management is activated by a specific software utility that must be resident in
the system that is driving the display. This software must support the VESA DPMS hardware
interface to the display and must be specifically written for each graphics controller. Most Lenovo
monitors have the necessary power-saving circuitry built into them as standard features.
CRT
• Lenovo E75
Lenovo Monitors
Lenovo markets both CRT and flat panel TFT monitors.
Current Lenovo CRT monitors:
• Lenovo E75
Current Lenovo flat panel TFT monitors:
• ThinkVision L151
• ThinkVision L171p
• ThinkVision L174
• ThinkVision L190x
• ThinkVision L193p
• ThinkVision L197 Wide
• ThinkVision L200p Wide
• ThinkVision L220x Wide ThinkVision L220x Wide
PC
Analog signal
Analog CRT
15-pin D-sub
Graphics Digital-to-analog
controller converter (DAC)
Analog LCD
Analog signal
15-pin D-sub Some image
quality lost
Digital-to-analog Analog-to-digital
converter (DAC) converter (ADC)
Monitor Connectors:
DVI Overview
DVI Connectors
In April 1999, the Digital Display Working Group (DDWG) released the Digital Visual Interface
(DVI) revision 1.0 specification, which defined new monitor connector types to incorporate digital
flat panel monitors. DVI defines connectors with implementations that allow backward
compatibility with analog CRTs and support for digital flat panel monitors.
The data format used by DVI is based on the PanelLink serial format devised by the semiconductor
manufacturer Silicon Image Inc. This uses Transition Minimized Differential Signaling (TMDS). A
single-link DVI consists of four twisted pairs of wire (red, green, blue, and clock) to transmit 24
bits per pixel. The timing of the signal almost exactly matches that of an analog video signal. The
picture is transmitted line by line with blanking intervals between each line and each frame, and
without packetization. No compression is used, and DVI has no provision for only transmitting
changed parts of the image so the whole frame is constantly retransmitted.
With a single-link DVI, the largest resolution possible at 60 Hz is 2.6 megapixels. The DVI
connector therefore has provision for a second link called dual-link DVI, containing another set of
red, green, and blue twisted pairs. When more bandwidth is required than is possible with a single-
link, the second link is enabled, and alternate pixels may be transmitted on each. Dual-link doubles
the bandwidth of the DVI interface such as needed to drive a 4-megapixel monitor (2560x1600).
The DVI specification mandates a fixed single-link cutoff point of 165 MHz, where all display
modes that require less than this must use single-link mode, and all those that require more must
switch to dual link mode. When both links are in use, the pixel rate on each may exceed 165 MHz.
The second link can also be used when more than 24 bits per pixel is required, in which case it
carries the least significant bits.
Like current analog VGA connectors, the DVI connector includes pins for the Display Data
Channel version 2 (DDC2B) that allows the graphics adapter to read the monitor's extended display
identification data (EDID).
DVI pins are not the standard cylindrical pins found on analog VGA connectors; they are flattened
and twisted to create a Low Force Helix (LFH) contact which provides a more reliable and stable
link.
• DVI-D only supports digital signaling
• DVI-A only supports analog signaling
• DVI-I supports both analog and digital signaling
• 15-pin D-shell only supports analog signaling
DVI-D (single-link) on PC
DVI-D (dual-link) on PC
DVI-I (single-link) on PC
DVI-I (dual-link) on PC
DVI-A on monitor
DVI-D Connector
DMS-59 Connector
The DMS-59 connector allows connection of a dual DVI-I cable or dual VGA cable. DMS-59 is used
to carry two digital DVI and/or two analog VGA video signals. A “Y-cable” splitter is needed to
convert DMS-59 interface to (digital) DVI-D or (analog) VGA. A DMS59 video card solution is
designed to address expansion card height restraints that exist in today’s small form factor PCs.
DMS59 Connector
(plug end)
DMS59 to Dual-VGA dongle allows two VGA DMS59 to Dual-DVI dongle allows two DVI
monitors to connect to the graphics adapter monitors to connect to the graphics adapter
Monitor Connectors:
DVI Connector Map
PC
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DVI-D connector ito en nd
at each cable end m on le ee
b l
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in e
1 5-p tem a ch ch
h s e a
wit n sy at n e
bl e o
rs s o
Requires r ca VI-A o r
(o D t
dongle le and ec cto
ng nn ne
Do end o
c o n
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I-D -A
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or
Monitor
© 2008 Lenovo
Dongle
Dongle
Typical monitor DB-15
(analog DB-15 to analog DVI-I)
(Analog)
Dongles get around mechanical differences; the signaling remains the same.
PC:
PC:
Monitor:
Digital DVI-D
(single-link)
Monitor Connectors:
High-bandwidth Digital Content Protection (HDCP)
© 2008 Lenovo
Monitor Connectors:
High Definition Multimedia Interface (HDMI)
© 2008 Lenovo
HDMI's initial success has come in the world of consumer electronics and digital TVs, where it is
now a de facto standard. HDMI is expected to become more widespread in higher-end PC graphics
adapters and PC monitors. It will primarily replace the DVI connector.
HDMI utilizes the High-bandwidth Digital Content Protection (HDCP) digital rights management
(DRM) specification. This HDCP specification is proprietary, requiring a license and royalty
payments. HDMI in conjunction with HDCP is also a required part of both the Blu-ray and HD-
DVD standards. As a result, any CE device that uses Blu-ray or HD-DVD standards must include
an HDMI connector.
The standard 19-pin Type A HDMI connector is backward-compatible with the single-link DVI to
carry digital video (DVI-I or DVI-D). This allows a DVI source to connect to an HDMI monitor, or
vice versa, with a compatible adapter or dongle, but the audio and remote control features of HDMI
would not operate. Also, without HDCP support in a monitor, the content will not display. A future
29-pin Type B connector will carry an expanded video channel for use with resolutions higher than
WQSXGA (3200x2048). Type B HDMI is backward compatible with dual-link DVI.
Monitor Connectors:
DisplayPort
DisplayPort Connector
© 2008 Lenovo
DisplayPort
DisplayPort is a digital audio and video interface for broad application in PCs, monitors,
televisions, and projectors. It also defines the internal connections between notebook PC graphics
chipsets and their associated LCD screens. DisplayPort is designed to replace DVI and eventually
VGA, making digital display connections easier, more readily available and more functional. The
DisplayPort digital interface was originally created as a cost-free alternative to HDMI.
Currently at version 1.1, DisplayPort is owned by the Video Electronics Standards Association
(VESA). VESA runs a compliance and interoperability program for DisplayPort connectors, cables
and devices. The VESA program ensures functional compatibility between products that carry the
DisplayPort logo. In January 2007, VESA announced that it is developing a DisplayPort
Interoperability Guideline that recommends how best to provide DisplayPort, DVI and HDMI
connectivity for consumer PCs via the DisplayPort connector and simple cable adapters. The
Interoperability Guideline will describe how DisplayPort products may be designed to enable full
compatibility with HDMI products, providing a clear blueprint for display connectivity
convergence within the home.
DisplayPort adds capabilities to support High Bandwidth Digital Content Protection (HDCP) for
viewing protected content such as high definition movies on optical media. HDCP version 1.3 for
DisplayPort uses 128-bit AES encryption and is provided by the Digital Content Protection (DCP)
LLC. This version allows products supporting either DVI or HDMI, and DisplayPort, to share a
common encryption key set. This copy-protection is licensed separately.
The DisplayPort connector supports one to four data pairs via the main link carrying both audio and
clock signals with a transfer rate of 1.62 or 2.7 Gb/s. Video signals use 8 or 10 bit pixel format per
color channel. A bi-directional auxiliary channel runs at a constant 1 MB/s that serves as Main Link
management and device control using VESA EDID and VESA MCCS standards. The video signal
is not compatible with DVI or HDMI. Full bandwidth is supported over a 3 meter cable with
reduced bandwidth to 1080p on a 15 meter cable. It is hot-pluggable.
A single DisplayPort connector can support multiple monitors if the monitors support daisy
chaining. DisplayPort supports up to six 1080i displays with daisy chaining with its packet-based
signal.
Summary:
Graphics Architecture
Review Quiz
Objective 1
1. In order to reach a specific resolution and refresh rate other than VGA, all of the following
graphics processing elements must support the desired objective except which of the following?
a. Monitor
b. System bus
c. Device driver
d. Graphics controller
2. A monitor has 1280x1024 resolution. What does the number 1024 represent?
a. 1024 vertical units
b. 1024 horizontal units
c. 1024 diagonal units
d. 1024 triads
4. A vendor that advertises a 24-bit color graphics controller has a controller that can display how
many simultaneous colors?
a. 256
b. 65,536
c. 16.7 million
d. 33.4 million
5. What converts the digital signal in a PC to the analog signal understood by the monitor?
a. Video memory
b. Rambus DRAM
c. Video feature connector
d. Digital-to-analog converter (DAC)
6. What is the advantage of a discrete graphics solution over an integrated graphics controller?
a. Less heat
b. Better performance
c. Lower cost
d. Use of an adapter slot
7. What term refers to special chips that allow PCs to display images from all sides with an illusion
of depth?
a. Digital-to-analog converter (DAC)
b. Bitblt
c. Direct3D
d. 3D graphics
8. What is a way to see more applications by having unique images on all monitors attached to a
system?
a. Cloning
b. Multi-monitoring
c. Direct 3D
d. 16.7 million color depth
Objective 2
Objective 3
Objective 4
Objective 5
13. A graphics controller with a Digital Video Interface (DVI-D) connector will work best with
which monitor?
a. Analog CRT
b. Digital LCD with an analog-to-digital converter
c. Digital LCD that accepts a digital signal
d. Analog CRT with a DVI connector
Objective 6
14. What connector provides a completely digital signal from a PC to supported monitors?
a. Voltage Regulator Module (VRM)
b. Digital Visual Interface (DVI)
c. Very Large Memory (VLM)
d. Flat Display (FD)
15. How would a graphics controller with a DVI-I connector interface with a traditional analog DB-
15 monitor connector?
a. A dongle is required to connect the DVI-I connector to the DB-15 connector on the
monitor.
b. The monitor DB-15 connector will attach directly to a DVI-I connector.
c. The graphics connector must be converted to a DVI-A connector.
d. The graphics controller will connect to the analog monitor but no signal is possible
because it is an analog monitor.
Answer Key
1. B
2. A
3. D
4. C
5. D
6. B
7. D
8. B
9. A
10. B
11. D
12. D
13. C
14. B
15. A