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Eca PDC Lab Manual
Eca PDC Lab Manual
Eca PDC Lab Manual
Work Book
Name:
Reg.No:
Branch:
Class: Section:
1
Electronic Circuit Analysis & Pulse and Digital circuit Lab
IARE-ECE Department
CERTIFICATE
LAB Incharge
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Part: 1
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Part: 2
b) The steady state output waveform of clampers for a square wave input
8. Response of Schmitt Trigger circuit for loop gain less than and greater than one
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
5
Electronic Circuit Analysis & Pulse and Digital circuit Lab
INDEX
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
8 Response of Schmitt Trigger circuit for loop gain less than and 132
greater than one
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO- 1
AIM:
d) Capacitor. 22 F. 1
e) Inductor. 50mH 1
0-100mA
2. D.C milli ammeter 1
Cathode Ray Oscilloscope. (0-20)MHz 1
3.
Function Generator. 0.1 Hz-10 1
4. MHz
BNC Connector 2
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
5.
Connecting Wires 5
6. 5A
THEORY:
Power amplifiers are mainly used to deliver more power to the load. To deliver more power it requires
large input signals, so generally power amplifiers are preceded by a series of voltage amplifiers. In
class-A power amplifiers, Q-point is located in the middle of DC-load line. So output current flows for
complete cycle of input signal. Under zero signal condition, maximum power dissipation occurs across
the transistor. As the input signal amplitude increases power dissipation reduces. The maximum
theoretical efficiency is 50%.
CIRCUIT DIAGRAM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPECTED GRAPH:
Bandwidth=fH – fL
TABULAR FORM:
Vin = 150 mV
1 100
2 200
3 400
4 800
5 1K
6 2K
7 4K
8 8K
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
9 10K
10 20K
11 40K
12 80K
13 100K
14 200K
CALCULATIONS:
PROCEDURE:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PRECAUTIONS:
RESULT:
VIVA QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO- 2
AIM:
To study class C power amplifier and to determine its efficiency.
APPARATUS:
1. Physitech class C power amplifier trainer.
2. Signal generator
3. Milli ammeter(0-50mA).
4. BNC probes and connecting wires.
THEORY :
Class-C amplifiers conduct less than 50% of the input signal and the distortion at the output is high,
but high efficiencies (up to 90%) are possible. The usual application for class-C amplifiers is in RF
transmitters operating at a single fixed carrier frequency, where the distortion is controlled by a tuned
load on the amplifier. The input signal is used to switch the active device causing pulses of current to
flow through a tuned circuit forming part of the load.
The class-C amplifier has two modes of operation: tuned and unturned. The diagram shows a waveform
from a simple class-C circuit without the tuned load. This is called untuned operation, and the analysis
of the waveforms shows the massive distortion that appears in the signal. When the proper load (e.g.,
an inductive-capacitive filter plus a load resistor) is used, two things happen. The first is that the output's
bias level is clamped with the average output voltage equal to the supply voltage. This is why tuned
operation is sometimes called a clamper. This allows the waveform to be restored to its proper shape
despite the amplifier having only a one-polarity supply. This is directly related to the second
phenomenon: the waveform on the center frequency becomes less distorted. The residual distortion is
dependent upon the bandwidth of the tuned load, with the center frequency seeing very little distortion,
but greater attenuation the farther from the tuned frequency that the signal gets.
The tuned circuit resonates at one frequency, the fixed carrier frequency, and so the unwanted
frequencies are suppressed, and the wanted full signal (sine wave) is extracted by the tuned load. The
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
signal bandwidth of the amplifier is limited by the Q-factor of the tuned circuit but this is not a serious
limitation. Any residual harmonics can be removed using a further filter.
The active element conducts only while the drain voltage is passing through its minimum. By this
means, power dissipation in the active device is minimized, and efficiency increased. Ideally, the active
element would pass only an instantaneous current pulse while the voltage across it is zero: it then
dissipates no power and 100% efficiency is achieved. However practical devices have a limit to the
peak current they can pass, and the pulse must therefore be widened, to around 120 degrees, to obtain
a reasonable amount of power, and the efficiency is then 60-70%
CIRCUIT DIAGRAM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPECTED GRAPH:
Bandwidth=fH – fL
1 100
2 200
3 400
4 800
5 1K
6 2K
7 4K
8 8K
9 10K
10 20K
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
11 40K
12 80K
13 100K
14 200K
CALCULATIONS:
OutputPower Pout
η= x100 = x100
Inputpower Pin
PROCEDURE:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
RESULT:
VIVA QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO- 3
SINGLE TUNED VOLTAGE AMPLIFIER
AIM:
1. To study & plot the frequency response of a Single Tuned voltage amplifier.
2. To find the resonant frequency.
3. To calculate gain and bandwidth.
d) Capacitor. 10F 2
22 F. 1
0.022 F. 1
0.033F. 1
e) Inductor. 1mH 1
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
5. Connecting Wires 5A 5
CIRCUIT DIAGRAM:
EXPECTED WAVEFORM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
TABULAR COLUMN :
2 200
3 400
4 800
5 1K
6 2K
7 4K
8 8K
9 10K
10 20K
11 40K
12 80K
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
13 100K
14 200K
THEORY:
Tuned amplifiers are amplifiers involving a resonant circuit, and are intended for selective
amplification within a narrow band of frequencies. Radio and TV amplifiers employ tuned amplifiers
to select one broadcast channel from among the many concurrently induced in an antenna or transmitted
through a cable. Selected aspects of tuned amplifiers are reviewed in this note. Parallel Resonant Circuit
An idealized parallel resonant circuit, i.e. one described by idealized circuit elements, is drawn below.
input impedance of this configuration, shown below the circuit diagram, is readily obtained. A modest
algebraic restatement in convenient form also is shown. The significance of the definitions of the
'quality factor' Q and the resonant frequency ωo will become clear from the discussion. The influence
of the Q parameter on the tuned-circuit impedance for several values of Q is plotted below for a
normalized response.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PROCEDURE:
PRECAUTIONS: -
RESULT:
Bandwidth= _________
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Bandwidth= _________
VIVA QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
GRAPH:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO-4
To find practical frequency of a Hartley oscillator and to compare it with theoretical frequency
for L = 10mH and C = 0.01F, 0.033F and 0.047F.
0.033F 1
0.047F 1
d) Resistor 1
1K
1
10K
1
47K
e) NPN Transistor 1
BC 107
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CIRCUIT DIAGRAM:
HARTLEY OSCILLATOR
EXPECTED WAVEFORM:
TABULATIONS:
1 10 0.01
2 10 0.033
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
3 10 0.047
THEORY:
The Hartley oscillator is an electronic oscillator circuit in which the oscillation frequency is
determined by a tuned circuit consisting of capacitors and inductors, that is, an LC oscillator. The circuit
was invented in 1915 by American engineer Ralph Hartley. The distinguishing feature of the Hartley
oscillator is that the tuned circuit consists of a single capacitor in parallel with two inductors in series
(or a single tapped inductor), and the feedback signal needed for oscillation is taken from the center
connection of the two inductors.
The frequency of oscillation is approximately the resonant frequency of the tank circuit. If the
capacitance of the tank capacitor is C and the total inductance of the tapped coil is L then
However if the two coils are magnetically coupled the total inductance will be greater because of
mutual inductance k.
PROCEDURE:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
4. Now connect the capacitance to 0.033 F and 0.047F and calculate the frequency and
tabulate the readings as shown.
5. Find the theoretical frequency from the formula
1
f=
2 LT C
PRECAUTIONS:
RESULT:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO-4
c) Capacitor 0.01F 1
0.1F 1
100 F 1
0.001 1
0.0022 1
0.0033 1
d) Resistor 1K 1
1
1.5K
1
10K
1
47K
e) NPN Transistor 1
BC 107
CIRCUIT DIAGRAM:
COLPITTS OSCILLATOR
EXPECTED WAVEFORM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
TABULAR COLUMN:
1 5 0.01 0.001
2 5 0.01 0.0022
3 5 0.01 0.0033
THEORY:
A Colpitts oscillator, invented in 1918 by American engineer Edwin H. Colpitts,[1] is one of a number
of designs for LC oscillators, electronic oscillators that use a combination of inductors (L) and
capacitors (C) to produce an oscillation at a certain frequency. The distinguishing feature of the Colpitts
oscillator is that the feedback for the active device is taken from a voltage divider made of two
capacitors in series across the inductor.The frequency of oscillation is approximately the resonant
frequency of the LC circuit, which is the series combination of the two capacitors in parallel with the
inductor
The actual frequency of oscillation will be slightly lower due to junction capacitances and resistive
loading of the transistor.As with any oscillator, the amplification of the active component should be
marginally larger than the attenuation of the capacitive voltage divider, to obtain stable operation. Thus,
a Colpitts oscillator used as a variable frequency oscillator (VFO) performs best when a variable
inductance is used for tuning, as opposed to tuning one of the two capacitors. If tuning by variable
capacitor is needed, it should be done via a third capacitor connected in parallel to the inductor (or in
series as in the Clapp oscillator).
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PROCEDURE:
1
C1C 2
CT
f=
2 LC T Where
C1 C 2
and compare theoretical and practical values.
6. Plot the graph o/p voltage vs time period and practical frequency
PRECAUTIONS:
RESULT:
Hence, the frequency of oscillations of Colpitts oscillator is measured practically and compared with
theoretical values .
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
VIVA QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO 5
AIM: To study & plot the frequency response of a Darlington emitter follower circuit.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CIRCUIT DIAGRAM:
EXPECTED GRAPH:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
TABULAR COLUMN :
Vin = 50 mV
20
40
80
100
500
1000
2000
5000
10K
50K
100K
200K
400K
600K
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
800K
1000K
THEORY:
The Darlington transistor (often called a Darlington pair) is a compound structure consisting of two
bipolar transistors (either integrated or separated devices) connected in such a way that the current
amplified by the first transistor is amplified further by the second one. This configuration gives a much
higher common/emitter current gain than each transistor taken separately and, in the case of integrated
devices, can take less space than two individual transistors because they can use a shared collector.
Integrated Darlington pairs come packaged singly in transistor-like packages or as an array of devices
(usually eight) in an integrated circuit. A Darlington pair behaves like a single transistor with a high
current gain (approximately the product of the gains of the two transistors). In fact, integrated devices
have three leads (B, C and E), broadly equivalent to those of a standard transistor. A general relation
between the compound current gain and the individual gains is given by:
If β1 and β2 are high enough (hundreds), this relation can be approximated with:
Darlington pairs are available as integrated packages or can be made from two discrete transistors; Q1
(the left-hand transistor in the diagram) can be a low power type, but normally Q2 (on the right) will
need to be high power. The maximum collector current IC(max) of the pair is that of Q2. A typical
integrated power device is the 2N6282, which includes a switch-off resistor and has a current gain of
2400 at IC=10A.
A Darlington pair can be sensitive enough to respond to the current passed by skin contact even at safe
voltages. Thus it can form the input stage of a touch-sensitive switch.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PROCEDURE:
PRECAUTIONS:
RESULT:
Hence the frequency response Darlington emitter follower circuit has been studied and plotted
Gain: _____________________
Bandwidth: fH – fL = __________________
VIVA QUESTIONS:
1. What is the difference between emitter follower and Darlington pair ckt?
2. What is the value of i/p impedance of a typical Darlington pair ckt?
3. What is the value of o/p impedance of a typical Darlington pair ckt?
4. What is the value of current and voltage gain of a typical Darlington pair ckt?
5. Mention the applications of a Darlington pair ckt
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO: 6
MOS AMPLIFIER
AIM:
4.7 K 1
1M
2. Signal generator 0.1Hz-1MHz 1
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CIRCUIT DIAGRAM:
THEORY:
A common-source amplifier is one of three basic single-stage field-effect transistor (FET) amplifier
topologies, typically used as a voltage or transconductance amplifier. The easiest way to tell if a FET
is common source, common drain, or common gate is to examine where the signal enters and leaves.
The remaining terminal is what is known as "common". In this example, the signal enters the gate, and
exits the drain. The only terminal remaining is the source. This is a common-source FET circuit. The
analogous bipolar junction transistor circuit is the common-emitter amplifier. The common-source (CS)
amplifier may be viewed as a transconductance amplifier or as a voltage amplifier. As a
transconductance amplifier, the input voltage is seen as modulating the current going to the load. As a
voltage amplifier, input voltage modulates the amount of current flowing through the FET, changing
the voltage across the output resistance according to Ohm's law. However, the FET device's output
resistance typically is not high enough for a reasonable transconductance amplifier (ideally infinite),
nor low enough for a decent voltage amplifier (ideally zero). Another major drawback is the amplifier's
limited high-frequency response. Therefore, in practice the output often is routed through either a
voltage follower (common-drain or CD stage), or a current follower (common-gate or CG stage), to
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
obtain more favorable output and frequency characteristics. The bandwidth of the common-source
amplifier tends to be low, due to high capacitance resulting from the Miller effect. The gate-drain
capacitance is effectively multiplied by the factor .
TABULAR COLUMN :
Vin = 50 mV
20
40
80
100
500
1000
2000
5000
10K
50K
100K
200K
400K
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
600K
800K
1000K
PROCEDURE:
PRECAUTIONS:
RESULT:
VIVA:
1. Draw the character sites of mosfet.
2. Define varies region of mosfet character sties.
3. Right the current equation for mosfet for varies region.
4. Define second order effect of a mosfet.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
SIMULATION LAB
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO: 1
CE AMPLIFIER
AIM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
5. Connecting Wires
5A 5
CIRCUIT DIAGRAM:
CE AMPLIFIER
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPECTED GRAPH:
Bandwidth = fH-fL
TABULAR COLUMN:
20
600
1K
2K
4K
8K
10K
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
20K
30K
40K
50K
60K
80K
100K
250K
500K
750K
1000K
THEORY:
The CE amplifier provides high gain & wide frequency response. The emitter lead is common to both
input and output circuits and is grounded. The emitter base is forward biased. The collector current is
controlled by the base current rather than emitter current. The input signal is applied to base terminal
of the transistor and amplifier output is taken across collector terminal. A very small change in base
current produces a much larger change in collector current. Frequency response of an amplifier is
defined as the variation of gain with respective frequency. The gain of the amplifier increases as the
frequency increases from zero till it becomes maximum at lower cut-off frequency and remains constant
till higher cut-off frequency and then it falls again as the frequency increases.
At low frequencies the reactance of coupling capacitor CC is quite high and hence very small part of
signal will pass through from one stage to the next stage.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
At high frequencies the reactance of inter electrode capacitance is very small and behaves as a short
circuit. This increases the loading effect on next stage and service to reduce the voltage gain due to
these reasons the voltage gain drops at high frequencies.
At mid frequencies the effect of coupling capacitors is negligible and acts like short circuit, where as
inter electrode capacitors acts like open circuit. So, the circuit becomes resistive at mid frequencies and
the voltage gain remains constant during this range.
PROCEDURE:
Gain, AV = ________dB.
VIVA QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO: 2
AIM:
1.5K 1
(d) Resistors 4.7 K 1
1
1M
THEORY:
The FET is a type of transistor commonly used for weak signal amplification. The
device can amplify analog or digital signals. It can also switch DC or function as an oscillator. In the
FET current flows along a semiconductor path called the channel. At one end of the channel, there is
an electrode called source. At the other end of the channel there is an electrode called the drain.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Frequency response of an amplifier is defined as the variation of gain with respective frequency. The
gain of the amplifier increases as the frequency increases from zero till it becomes maximum at lower
cut-off frequency and remains constant till higher cut-off frequency and then it falls again as the
frequency increases. At low frequencies the reactance of coupling capacitor CC is quite high and hence
very small part of signal will pass through from one stage to the next stage. At high frequencies the
reactance of inter electrode capacitance is very small and behaves as a short circuit. This increases the
loading effect on next stage and service to reduce the voltage gain due to these reasons the voltage gain
drops at high frequencies. At mid frequencies the effect of coupling capacitors is negligible and acts
like short circuit, where as inter electrode capacitors acts like open circuit. So, the circuit becomes
resistive at mid frequencies and the voltage gain remains constant during this range
CIRCUIT DIAGRAM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPECTED GRAPH:
TABULAR COLUMN:
Input = 50mV
Frequency Gain
(in Hz)
(in dB) =
20log10(Vo/Vi)
20
40
80
100
500
1000
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
5000
10K
50K
100K
200K
400K
600K
800K
PROCEDURE:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
RESULT:
VIVA QUESTIONS:
54
Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO- 3
AIM:
1. To plot the frequency response of a RC coupled amplifier with a pair of shunted emitter
capacitors of 10 μF and 100μF.
2. To calculate gain.
3. To calculate bandwidth.
2. Bode Plotter 1
0.1 Hz-10
3. Function Generator. MHz 1
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CIRCUIT DIAGRAM:
EXPECTED GRAPH:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
TABULAR FORM:
Vin = 50 mV
C=10μF C=100μF
S.No Frequency Gain(dB) Frequency Gain(dB)
(in Hz) 20 (in Hz) 20
log(Vo/ log(Vo/
Vi ) Vi )
1 100
2 200
3 400
4 800
5 1K
6 2K
7 4K
8 8K
9 10K
10 20K
11 40K
12 80K
13 100K
14 200K
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
15 300K
16 500K
17 700K
18 900K
19 1M
THEORY:
As the gain provided by a single stage amplifier is usually not sufficient to drive the load, so to achieve
extra gain multi-stage amplifier are used. In multi-stage amplifiers output of one-stage is coupled to the
input of the next stage. The coupling of one stage to another is done with the help of some coupling
devices. If it is coupled by RC then the amplifier is called RC-coupled amplifier.
Frequency response of an amplifier is defined as the variation of gain with respective frequency. The
gain of the amplifier increases as the frequency increases from zero till it becomes maximum at lower
cut-off frequency and remains constant till higher cut-off frequency and then it falls again as the
frequency increases. At low frequencies the reactance of coupling capacitor CC is quite high and hence
very small part of signal will pass through from one stage to the next stage.
At high frequencies the reactance of inter electrode capacitance is very small and behaves as a short
circuit. This increases the loading effect on next stage and service to reduce the voltage gain due to
these reasons the voltage gain drops at high frequencies.
At mid frequencies the effect of coupling capacitors is negligible and acts like short circuit, where as
inter electrode capacitors acts like open circuit. So, the circuit becomes resistive at mid frequencies and
the voltage gain remains constant during this range.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PROCEDURE:
PRECAUTIONS:
RESULT:
Hence, the frequency Response of RC coupled (2 stage) amplifier for 10μF and 100 μF is plotted.
2. For C=100μF
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
VIVA:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO-4
AIM:
To study and plot the frequency response of a current shunt and voltage series feedback amplifier.
1. a) DC Supply voltage. 12 V 1
b) NPN Transistor. BC 107 2
c) Resistors. 47kΩ 2
2.2KΩ 2
10kΩ 1
1k 2
d) Capacitor. 0.1 F. 1
22F. 3
3. Bode plotter 1
4. Function Generator. 0.1 Hz-10 MHz 1
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CIRCUIT DIAGRAM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPECTED GRAPH:
THEORY:
Feedback plays a very important role in electronic circuits and the basic parameters, such as input
impedance, output impedance, current and voltage gain and bandwidth, may be altered considerably
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
by the use of feedback for a given amplifier. A portion of the output signal is taken from the output of
the amplifier and is combined with the normal input signal and thereby the feedback is accomplished.
There are two types of feedback. They are i) Positive feedback and ii) Negative feedback. Negative
feedback helps to increase the bandwidth, decrease gain, distortion, and noise, modify input and output
resistances as desired. A current shunt feedback amplifier circuit is illustrated in the figure. It is called
a series-derived, shunt-fed feedback. The shunt connection at the input reduces the input resistance and
the series connection at the output increases the output resistance. This is a true current amplifier.
TABULAR FORM:
Input voltage = 50mv
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
400k
600k
800k
1M
PROCEDURE:
PRECAUTIONS:
RESULT:
Frequency responses for voltage series (with and without feedback amplifier),current
shunt (with and without capacitor are plotted)
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO-5
CASCODE AMPLIFIER
AIM:
2. Bode Plotter 1
0.1 Hz-10
3. Function Generator. MHz 1
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CIRCUIT DIAGRAM:
EXPECTED WAVEFORM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
THEORY:
Cascode amplifier is a cascade connection of a common emitter and common base amplifiers. It is
used for amplifying the input signals. The common application of cascade amplifier is for impedance
matching. The low impedance of CE age is matched with the medium of the CB sage.
TABULAR COLUMN:
Input = 50mV
Frequency Gain
(in Hz)
(in dB) =
20log10(Vo/Vi)
20
40
80
100
500
1000
5000
10K
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
50K
100K
200K
400K
600K
800K
PROCEDURE:
PRECAUTIONS:
RESULT:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Gain=
Bandwidth =fH – fL =
VIVA QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO-6
AIM:
To find practical frequency of a wein bridge oscillator and to compare it with theoretical frequency
R1=10k R2= 8.2k and C1,C2 for 0.01uf ,0.022uf & 0.033uf.
0.022F------ 2
0.033F---- 2
2
1K-----------
c) Resistor 3
10K---------
1
47K----------
1
8.2K---------
2
BC 107--------
d) NPN Transistor
e) Zener diode
5.1v 2
2 CRO 1
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CIRCUIT DIAGRAM:
EXPECTED WAVEFORM
THEORY:
The Wien bridge oscillator employs a balanced wien bridge as the feedback network. Two stage CE
amplifier provides 360o phase shift to the signal. So the wien bridge need not introduce any phase
shift to satisfy Barkausen criterion .The attenuation of the bridges calculated to be 1/3 at resonant
frequency. So the amplifier stage should provide a gain of exactly 3 to make loop gain unity. Since
the gain of two stage amplifier is the product of individual stages , overall gain becomes very high.
But the gain will be trimmed down to 3 by negative feedback network. The emitter resistors of both
stages are kept unbypassed . This provides a current series feedback which ensures the stability of
operating point and reduction of gain. Frequency of oscillation is given by f = 1/2πRC
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
TABULATIONS:
PROCEDURE:
f=
R1=10k R2= 8.2k and C1,C2 for 0.01uf ,0.022uf & 0.033uf. Compare theoretical and
practical values.
PRECAUTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
RESULT:
1. For C1 = 0.01F, & C2=0.01
VIVA QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO-7
AIM:
To find practical frequency RC phase shift oscillator and to compare it with theoretical frequency for
R=10K and C = 0.01F, 0.0022F & 0.0033F respectively
0.01F-------- 3
0.0022F------ 3
3
0.0033F----
c) Resistor 1
1K-----------
4
10K---------
1
47K----------
100K---------
1
BC 107--------
d) NPN Transistor 1
2 CRO 1
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CIRCUIT DIAGRAM:
EXPECTED WAVEFORM:
THEORY:
RC – phase shift oscillator has a CE amplifier followed by three sections of RC phase shift feedback
networks. The output of the last stage is return to the input of the amplifier.the values of R and C are
chosen such that the phase shift of each RC section is 600.thus,the RC ladder network produces a total
phase shift of 1800 between its input and output voltage for the given frequencies since CE amplifier
produces 1800 phase shift the total phase shift from the base of the transistor around the circuit and
back to the transistor will be exactly 3600 or 00.The frequency of oscillation is given by
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
F = 1/2ΠRC√6
PROCEDURE:
PRECAUTIONS:
RESULT:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
TABULAR COLUMN:
1 0.0022 10K
2 0.0033 10K
3 0.01 10K
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO- 8
AIM:
To study the frequency response of a series fed class-A power amplifier and calculate efficiency of
the amplifier circuit.
1. a) DC Supply voltage. 12 V 1
b) NPN Transistor. BC 107 1
c) Resistors. 560Ω 1
100KΩ 1
470Ω 1
d) Capacitor. 22 F. 1
e) Inductor. 50mH 1
2. D.C Milliammeter 0-100mA 1
3. Bode plotter 1
4. Function Generator. 0.1 Hz-10 MHz 1
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CIRCUIT DIAGRAM:
EXPECTED GRAPH:
THEORY:
Power amplifiers are mainly used to deliver more power to the load. To deliver more power it requires
large input signals, so generally power amplifiers are preceded by a series of voltage amplifiers. In
class-A power amplifiers, Q-point is located in the middle of DC-load line. So output current flows for
complete cycle of input signal. Under zero signal condition, maximum power dissipation occurs across
the transistor. As the input signal amplitude increases power dissipation reduces. The maximum
theoretical efficiency is 25%.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PROCEDURE:
2. Measure base, emitter and collector D.C voltages of both stages and compare against estimated
values.
3. Apply the input at input terminals of the circuit from the function generator.
4. Keep the input signal at constant frequency under mid frequency region and adjust the amplitude
such that output voltage undistorted.
RESULT:
The maximum input signal amplitude which produces undistorted output signal is _________
VIVA QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
TABULAR COLUMN:
1 100
2 200
3 400
4 800
5 1K
6 2K
7 4K
8 8K
9 10K
10 20K
11 40K
12 80K
13 100K
14 200K
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CALCULATIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT - 9
CLASS B POWER AMPLIFIER (COMPLEMENTARY SYMMETRY
AIM: To study the CLASS B Complementary Symmetry amplifier and to calculate its
efficiency.
1. a) DC Supply voltage. 12 V 1
b) NPN Transistor. BC 107 2
c) Resistors. 220KΩ 1
1KΩ 1
1Ω 1
18KΩ 2
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CIRCUIT DIAGRAM:
EXPECTED GRAPH:
THEORY:
Power amplifiers are designed using different circuit configuration with the sole purpose of delivering
maximum undistorted output power to load. Push-pull amplifiers operating either in class-B are class-
AB are used in high power audio system with high efficiency. In complementary-symmetry class-B
power amplifier two types of transistors, NPN and PNP are used. These transistors acts as emitter
follower with both emitters connected together.
In class-B power amplifier Q-point is located either in cut-off region or in saturation region. So, that
only 180o of the input signal is flowing in the output. In complementary-symmetry power amplifier,
during the positive half cycle of input signal NPN transistor conducts and during the negative half cycle
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PNP transistor conducts. Since, the two transistors are complement of each other and they are connected
symmetrically so, the name complementary symmetry has come
Theoretically efficiency of complementary symmetry power amplifier is 78.5%.
PROCEDURE:
2. Connect Milliammeter to (A) terminals and DRB to the RL terminals and fix RL=50Ω.
3. Apply the input voltage from the signal generator to the Vs terminals.
4. Connect channel 1 of CRO to the Vs terminals and channel 2 across the load.
5. By varying the input voltage, observe the maximum distortion less output waveform.
OBSERVATIONS: Vs=2v
10 KHz
CALCULATIONS:
Pin=Vcc x Idc
Vo
Idc= =
RL
2
Vo
Pout =
8 RL
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
VIVA
2.state the advantages of push pull class b power amplifier over class b power amplifier .
3. what is harmonic distortion how even harmonic is eliminated using push pull
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PULSE CIRCUITS
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Practical knowledge in electronic circuits and pulse circuits plays vital role in designing and developing
circuits for various applications. The PC lab was designed to give practical overview on different
amplifier circuits and pulse circuits. This Lab provides students with the opportunity to gain an
experience in connecting the circuits and studying the responses of these circuits. A software tool is
also provided for simulating the circuit.
This lab deals with the methods for the generation of pulse waveforms making use of semiconductor
devices like Diodes, Transistors and UJT’s. Pulse waveforms play a significant role in household
appliances like television radio and digital clocks. Their industrial applications include digital
instrumentation, Control Systems, digital Computers, data processing systems and CRO’s. The term
Pulse waveforms is popularly employed in electronics to refer to non-sinusoidal waveforms. These
waveforms play a vital role in electronic communication, and they are of immense help in pulse
Communication, television Engineering, radar, and telemetry.
Pulse waveforms change between the LOW and HIGH levels. A positive going pulse is one that goes from a normally
LOW logic level to a HIGH level and then back again. Digital waveforms are made up of a series of pulses.
Active LOW - if the state change occurs from a “HIGH” to a “LOW” at the clock’s pulses falling
edge.
Duty Cycle - this is the ratio of the clock width to the clock period.
Clock Width - this is the time during which the value of the clock signal is equal to a logic “1”, or
HIGH.
Clock Period - this is the time between successive transitions in the same direction, ie, between two
rising or two falling edges.
Clock Frequency - the clock frequency is the reciprocal of the clock period, frequency = 1/clock
period
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Most natural quantities that we see are analog and vary continuously. Analog systems can generally
handle higher power than digital systems Timing circuits networks composed of resistors, capacitors
and inductors are called linear network and they do not change the waveform of a sine wave when it is
transmitted through them. On the other hand when non-sinusoidal waveforms, (e.g. step, ramp,
exponential) are applied to the input of such networks the output signal may have very little resembles
with the input waveform. The action of a linear network in producing a waveform at its output different
from its input is called linear wave shaping. The wave shaping is used to perform any one of the
following functions.
Shaping circuits may be either series RC or series RL circuits. The series RC and RL circuits electrically
perform the mathematical operation of integration and differentiation. Therefore, the circuits used to
perform these operations are called integrators and differentiator. The differentiator circuits are used to
generate sharp narrow pulses either from distorted pulse waveform or from rectangular wave forms.
The integrator circuits are required to generate a voltage, which are required to generate a voltage,
which increases or decreases linearly with time.
The semiconductor Signal Diode is a small non-linear semiconductor devices generally used in
electronic circuits, where small currents or high frequencies are involved such as in radio, television
and digital logic circuits. The signal diode which is also sometimes known by its older name of the Point
Contact Diode or the Glass Passivated Diode, are physically very small in size compared to their
larger Power Diode cousins.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO:-1
LINEAR WAVE SHAPING
i) RC low pass circuit
AIM:
1. To design low pass RC circuits for different time constants and verify their responses for a
square wave input of given frequency.
2. To study the operation of low pass circuit as an integrator.
APPARTUS REQUIRED:
1. Resistor (100kΩ) - 1 No
2. Capacitors (0.1uF, 0.01uF & 0.001uF) - 1 No
3. Dual trace CRO - 1 No
4. Bread Board - 1 No
5. Signal Generator - 1 No
6. CRO Probes - 2 No
7. Connecting wires
CIRCUIT DIAGRAM:
THEORY:
Low Pass RCcircuit :The reactance of the capacitor depends upon the frequency of operation. At very
high frequencies, the reactance of the capacitor is zero. Hence the capacitor in fig.1.2 acts as short
circuit. As a result, the output will fall to zero. At low frequencies, the reactance of the capacitor is
infinite. So the capacitor acts as open circuit. As a result the entire input appears at the output. Since
the circuit allows only low frequencies, therefore it is called as low pass RC circuit.
Low – pass RC circuit as an integrator: In low pass circuit, if the time constant is very large in
comparison with the time required for the input signal to make an appreciable change, the circuit is
called an “integrator”. Under these circumstances the voltage drop across C will be very small in
comparison to the drop across R and we may consider that the total input Vi appears across R. ∴i = Vi/R
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
DESIGN:
b) RC >>T
c) RC<< T
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PROCEDURE:
V1
1 RC=T
V2
V1
2 RC>>T
V2
3 RC<<T V1
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Medium time
constant (RC=T)
REVIEW QUESTIONS:
1. Name the signals which are commonly used in pulse circuits and define any two of them?
2. Define linear wave shaping?
3. Define attenuator and types of attenuator?
4. Explain the fractional tilt of a high pass RC circuit. Write the Expression?
5. State the lower 3-db frequency of high-pass circuit?
6. Distinguish between the linear and non-linear wave shaping circuits.
7. Define Percentage Tilt and Rise time?
8. Show that a high pass circuit with a small time constant acts as differentiator?
9. Define Rise time? Give the relations between rise time and bandwidth?
10. Show that a low pass circuit with a time constant acts as Integrator?
11. Name a wave shaping circuit which produces a Ramp wave as an output by taking a step
signal as input and draw its output for a sinusoidal wave
12. Write the expressions for the output of a low pass circuit by a step and symmetrical square
waves?
13. Prove that for any periodic input wave form the average level of the steady state output signal
from an RC high pass circuit is always zero.
14. Explain the response of a high pass RC circuit to a step input signal?
15. Name a wave shaping circuit which produces a Ramp wave as an output by taking a step
signal as input and draw its output for a sinusoidal wave?
16. Write the expressions for the output of a low pass circuit by a step and symmetrical square
waves?
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
GRAPH:
RESULT: The characteristics of RC low pass circuit for different time constants are verified.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO:-1
LINEAR WAVE SHAPING
ii) RC high pass circuit
AIM:
1. To design high pass RC circuits for different time constants and verify their responses
for a square wave input of given frequency.
2. To find the % tilt of high pass RC circuit for long time constant.
3. To study the operation of high pass RC circuit as a differentiator
APPARTUS REQUIRED:
1. Resistor (100kΩ) - 1 No
2. Capacitors (0.1uF, 0.01uF & 0.001uF) - 1 No
3. Dual trace CRO - 1 No
4. Bread Board - 1 No
5. Signal Generator - 1 No
6. CRO Probes - 2 No
7. Connecting wires
CIRCUIT DIAGRAM:
RC Differentiator
THEORY:
High Pass RC circuit :The reactance of the capacitor depends upon the frequency of operation. At
very high frequencies, the reactance of the capacitor is zero. Hence the capacitor in fig.1.1 acts as short
circuit. As a result the entire input appears at the output. At low frequencies, the reactance of the
capacitor is infinite. So the capacitor acts as open circuit. Hence no input reaches the output. Since the
circuit allows only high frequencies, therefore it is called as high pass RC circuit.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPECTED WAVEFORMS:
a) RC=T
b) RC >>T
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
c) RC <<T
PROCEDURE:
Medium time
constant (RC=T)
Medium time
constant (RC=T)
REVIEW QUESTIONS:
GRAPH:
RESULT: The characteristics of RC High pass circuit for different time constants are verified
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO:-2(a)
NON LINEAR WAVE SHAPING
CLIPPERS
AIM:
To study the various clipper circuits and to plot the output waveforms for a sinusoidal input signal.
APPARATUS:
1. CRO (Dual Channel) - 1 No.
3. Breadboard - 1 No.
4. Diode (1N4007) - 2 No.
5. Resistor (1 KΩ) - 1 No.
6. D.C Power Supply (dual) - 2 No.
7. Connecting wires
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Negative Clipper
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Positive Clipper:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Negative Clipper
Slicer:
PROCEDURE: -
4. Observe the input and output waveforms on CRO and note down the readings.
5. Plot the graphs of input Vs output waveforms for different clipping circuits.
OBSERVATIONS:
Sl Type of Clipper Reference Theoretical Practical
No. Voltage Clipping Clipping
Voltage levels Voltage levels
0V
1 Series Positive Clipper 2V
-2V
0V
2 Series Negative Clipper 2V
-2V
0V
3 Shunt Positive Clipper 2V
-2V
0V
4 Shunt Negative Clipper 2V
-2V
5 Two level clipper
PRECAUTIONS: -
1. Avoid loose and wrong connections.
REVIEW QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
GRAPH:
RESULT: The characteristics of the different clippers using diodes are verified.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO:-2(b)
NON LINEAR WAVE SHAPING
CLAMPERS
AIM:
To study the various clamping circuits and to plot the output waveforms for a sinusoidal input
of given peak amplitude. (Choose f=1 kHz, Vp-p =8V)
APPARATUS:
THEORY: The process whereby the form of a sinusoidal signals are going to be altered by transmitting
through a non-linear network is called non-linear wave shaping. Non-linear elements in combination
with resistors and capacitors can function as clamping circuit. A Clamping circuit is one that takes an
input waveform and provides an output i.e a faithful replica of its shape, but has one edge clamped to
the voltage reference point. The clamping circuit introduces the d.c component at the output side, for
this reason the clamping circuits are referred to as d.c restorer or d.c reinserted.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CIRCUIT DIAGRAM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PROCEDURE:-
1. Connect the circuit as shown in figures (1-5)
2. Switch on the power supply and adjust the output of AF generator to 8V (peak to peak)
3. Square wave input and Observe the output waveforms on CRO and note down the
Readings.
4. Plot the graphs of input Vs output waveforms for different clamping circuits.
OBSERVATIONS:
Theoretical Practical
Reference Clamping Clamping
Sl No. Type of Clamper
Voltage reference reference
Voltage level Voltage level
0V
1 Positive Clamper 2V
-2V
0V
2 Negative Clamper 2V
-2V
PRECAUTIONS: -
REVIEW QUESTIONS:
5. Differentiate –ve clamping circuit from +ve clamping circuits in the above circuits?
6. Describe the charging and discharging of a capacitor in each circuit?
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
GRAPH:
RESULT: The characteristics of the different clampers using diodes are verified
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO: 3
TRANSISTOR AS A SWITCH
APPARTUS REQUIRED:-
1. Resistor – 2.2 KΩ, 68KΩ - 1 No
2. Transistor - BC 107 - 1 No
3. Dual trace CRO. - 1 No
4. Function generator. - 1 No
5. Probes - 2 No
6. Connecting wires.
CIRCUIT DIAGRAM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPECTED WAVEFORM:
THEORY: The transistor Q can be used as a switch to connect and disconnect the load RL from the
source VCC. When a transistor is saturated, it is like a closed switch from the collector to the emitter.
When a transistor is cut-off, it is like an open switch
VCE = VCC
Saturation: The point at which the load line intersects the IB = 0 curve is known as cut-off. At this
point, base current is zero and collector current is negligible small i.e., only leakage current ICEO exists.
At cut-off, the emitter diode comes out of forward bias and normal transistor action is lost. The
transistor appears like a closed switch.
VCE(sat) ˜ VCC
The intersection of the load line and the IB = IB(sat) is called saturation. At this point base current is IB(sat)
and the collector current is maximum. At saturation, the collector diode comes out of reverse bias, and
normal transistor action is again lost.
PROCEDURE:-
1. Connect the circuit as shown in figure.
2. Switch on the power supply and observe the output of the function generator on CRO.
Adjust input signal amplitude such that output signal peak-to peak value is less than the
Saturation level.
3. Observe output waveforms on CRO and note down the readings.
4. Plot the graphs between input and output waveforms at a given input frequency.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
Note:-
Rise Time: - It is the time taken to rise 10% of the Max value of the signal to 90% of
the Max value of the signal.
Fall Time: - It is the taken to fall 90% of the Max value of the signal to 10% of the
Max value of the signal.
Delay Time: - It is the time taken to rise from 0% to10% of the Max value of the signal.
Storage Time: - It is the time taken to fall from 100% to 90% of the Max value of the
Signal.
Turn ON Time: - It is the sum of Delay time and Rise time.
Turn OFF Time: - It is the sum of Storage time and fall time.
PRECAUTIONS: -
REVIEW QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
GRAPH:
EXPERIMENT NO: 4
BISTABLE MULTIVIBRATOR
AIM: To study the characteristics of bistable multivibrator using transistors.
APPARATUS REQUIRED:
1. CRO (Dual Channel) - 1 No.
2. Function Generator - 1 No.
3. CDS - 1 No.
5. Resistor (1 KΩ, 39 KΩ,3.9,10) - 2 No.
6 Capacitors (100 pF) - 2 No
7. Transistor (BC 107) - 2 No.
8. Diodes
9. Regulated D.C Power Supply (dual) - 1 No.
10. Connecting wires
CIRCUIT DIAGRAM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPECTED WAVEFORMS:
THEORY:A Bistable circuit is one which can exist indefinitely in either of two stable states
and which can be induced to make an abrupt transition from one state to the other by means
of external excitation.
The Bistable circuit is also called as Bistable multivibrator, Eccles Jordon circuit, Trigger circuit, Scale-
of-2 toggle circuit, Flip-Flop & Binary. A Bistable Multivibrator is used in a many digital operations
such as counting and the storing of binary information. It is also used in the generation and processing
of pulse-type waveform. They can be used to control digital circuits and as frequency dividers. There
are two outputs available which are complements of one another. i.e. when one output is high the other
is low and vice versa .
Operation: When VCC is applied, one transistor will start conducting slightly more than that of the
other, because of some differences in the characteristics of a transistor. Let Q2 be ON and Q1 be OFF.
When Q2 is ON, The potential at the collector of Q2 decreases, which in turn will decrease the potential
at the base of Q1 due to potential divider action of R1 and R2. The potential at the collector of Q1
increases which inturn further increases the base to emitter voltage at the base of Q2. The voltage at the
collector of Q2 further decreases, which inturn further reduces the voltage at the base of Q1. This action
will continue till Q2 becomes fully saturated and Q1 becomes fully cutoff.
Thus the stable state of binary is such that one device remains in cut-off and other device remains at
saturation. It will be in that state until the triggering pulse is applied to it. It has two stable states. For
every transition of states triggering is required. At a time only one device will be conducting.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
even none charge. Hence transistor cannot come out of saturation to cut-off. Until all such charges are
removed. The interval during which conduction transfer one transistor to other is called as the transition.
PROCEDURE:-
1. Connect the circuit as shown in Figure.
2. Observe the output of the square wave oscillator-using Oscilloscope.
3. Connect the output of square oscillator to the trigger input Of Bistable Circuit and observe output
waveforms using Oscilloscope.
4. By varying input signal (Trigger) frequency, observe both input and corresponding output Waveforms
Using Oscilloscope.
5. Plot the graph for input and output waveforms at different input (Trigger) frequencies.
OBSERVATIONS:
S.no Time period Voltage
1
2
PRECAUTIONS: -
1. Avoid loose and wrong connections.
REVIEW QUESTIONS :
4. Mention the name of different kinds of triggering used in the circuit shown?
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
GRAPH:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO:-5
ASTABLE MULTIVIBRATOR
AIM: To study the characteristics of Astable Multivibrator using transistors.
APPARATUS REQUIRED :
1. CRO (Dual Channel) - 1 No.
3. Breadboard - 1 No.
8. Connecting wires
.
CIRCUIT DIAGRAM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPECTED GRAPH:
THEORY: The Astable circuit has two quasi-stable states. Without external triggering signal
the astable configuration will make successive transitions from one quasi-stable state to the other.
The astable circuit is an oscillator. It is also called as free running multivibrator and is used to
generate “Square Wave”. Since it does not require triggering signal, fast switching is
possible.
Operation: When the power is applied, due to some importance in the circuit, the transistor Q2 conducts
more than Q1 i.e. current flowing through transistor Q2 is more than the current flowing in transistor
Q1. The voltage VC2 drops. This drop is coupled by the capacitor C1 to the base by Q1 there by reducing
its forward base-emitter voltage and causing Q1 to conduct less. As the current through Q1 decreases,
VC1 rises. This rise is coupled by the capacitor C2 to the base of Q2. There by increasing its base- emitter
forward bias. This Q2 conducts more and more and Q1 conducts less and less, each action reinforcing
the other. Ultimately Q2 gets saturated and becomes fully ON and Q1 becomes OFF. During this time
C1 has been charging towards VCC exponentially with a time constant T1 = R1C1. The polarity of C1
should be such that it should supply voltage to the base of Q1. When C1 gains sufficient voltage, it
drives Q1 ON. Then VC1 decreases and makes Q2 OFF. VC2 increases and makes Q1 fully saturated.
During this time C2 has been charging through VCC, R2, C2 and Q1 with a time constant T2 = R2C2. The
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
polarity of C2 should be such that it should supply voltage to the base of Q2. When C2 gains sufficient
voltage, it drives Q2 On, and the process repeats.
Design Procedure:
The period T is given by
T = 1.38 RC
T = 1.38 RC
R= KΩ
VCC −VCESAT
RC = =
IC max
TABLE:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PROCEDURE:-
1. Connect The Circuit As Shown In Figure 1.
2. Observe The Output Of The Circuit Using Oscilloscope and measure the time Period Of The
Signal And Compare It With Theoretical Value By Varying Dc source V (5V to 10V) in steps
(take minimum two readings).
3. Plot the output waveforms on the graph paper for one set of values.
4. Repeat the steps from 1 to 3 with timing capacitor 0.01μF.
5. Connect the circuit as shown in figure 2.
6. Repeat the steps from 1 to 4.
PRECAUTIONS: -
REVIEW QUESTIONS:
1. What are the other names of Astable Multivibrator?
3. Is it possible to change time period of the waveform with out changing R & C?
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
GRAPH:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO:-6
MONOSTABLE MULTIVIBRATOR
AIM : To study the characteristics of Monostable Multivibrator using transistors.
APPARATUS REQUIRED:
1. CRO (Dual Channel) - 1 No.
3. CDS - 1 No.
7. Connecting wires
CIRCUIT DIAGRAM:-
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
CASE 1:
CASE 2:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
THEORY:-
The Monostable circuit has one permanently stable and one quasi-stable state. In the
monostable configuration, a triggering signal is required to induce a transition from the stable state to
the quasi-stable state. The circuit remains in its quasi-stable for a time equal to RC time constant of the
circuit. It returns from the quasi-stable state to its stable state without any external triggering pulse. It
is also called as one-shot a single cycle, a single step circuit or a univibrator.
Operation:
Assume initially transistor Q2 is in saturation as it gets base bias from VCC through R. coupling from
Q2 collector to Q1 base ensures that Q1 is in cutoff. If an appropriate negative trigger pulse applied at
collector of Q1 (VC1) induces a transition in Q2, then Q2 goes to cutoff. The output at Q2 goes high. This
high output when coupled to Q1 base, turns it ON. The Q1 collector voltage falls by IC1 RC1 and Q2 base
voltage falls by the same amount, as voltage across a capacitor ‘c’ cannot change instantaneously.
The moment, a –ve trigger is applied VC1, Q2 goes to cutoff and Q1 starts conducting. There is a path
for capacitor C to charge from VCC through R and the conducting transistor Q1. The polarity should be
such that Q2 base potential rises. The moment, it exceeds Q2 base cut-in voltage, it turns ON Q2 which
due to coupling through R1 from collector of Q2 to base of Q1, turns Q1 OFF. Now we are back to the
original state i.e. Q2 On and Q1 OFF. Whenever trigger the circuit into the other state, it cannot stay
there permanently and it returns back after a time period decided by R and C.
DESIGN:-
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
OBSERVATIONS:
PROCEDURE:-
1. Connect the circuit as shown in figure.
2. Observe the output of the Square wave generator-using oscilloscope.
3. Connect the output of square oscillator to the trigger input of monostable circuit and also
Connect diode to the collector of the Q1.observe trigger spikes at Q1 collector using
Oscilloscope.
4. Connect one of the timing capacitor C to the circuit (say C=0.01μF) and observe the monostable at
collector of Q2 using oscilloscope.
5. Measure and note the pulse width of output signal and compare with the theoretical value (T=1.1RC).
6. By varying trigger input frequency, observe the corresponding output waveforms.
7. Plot the graph for input and output waveforms at different input frequencies.
8. Repeat the steps from 4 to 6 for timing capacitor C=0.1μF.
PRECAUTIONS: -
1. Avoid loose and wrong connections.
REVIEW QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
GRAPH:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO: 7
SCHMITT TRIGGER
AIM: To observe and note down the output waveforms of Schmitt trigger using transistors..
APPARATUS REQUIRED:
CIRCUIT DIAGRAM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPECTED WAVEFORMS:
THEORY:
In digital circuits fast waveforms are required i.e, the circuit remain in the active region for a very short
time (of the order of nano seconds) to eliminate the effects of noise or undesired parasitic oscillations
causing malfunctions of the circuit. Also if the rise time of the input waveform is long, it requires a
large coupling capacitor. Therefore circuits which can convert a slow changing waveform(long rise
time) in to a fast changing waveform (small rise time) are required. The circuit which performs this
operation is known as “Schmitt Trigger”.
In a Schmitt trigger circuit the output is in one of the two levels namely low or high. When the
output voltage is raising the levels of the output changes. When the output passes through a specified
voltage V1 known as Upper trigger level, similarly when a falling output voltage passes through a
voltage V2 known as lower triggering level. The level of the output changes V1 is always greater than
V2.The differences of these two voltages is known as “Hysteresis”.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
TABLE:
PROCEDURE:
1. Connect a triangle wave signal from an external function generator to the input of the level
changer.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
2. Connect the output of the level changer to the input of the Schmitt trigger.
3. Connect CH1 input of CRO to the input signal and CH2 to the output of the schmitt trigger.
4. Adjust the amplitude of the input signal to such a level that we observe square wave at the
output.
5. Note down the points of input where the output is high (UTP) and low (LTP) and note that
both the levels are not one and the same.
6. Find Re1 value and compare it with the theoretical value.
7. Repeat the steps 3 to 6 with different types of signals (sine, ramp etc).
8. From the above observations we can notice that Schmitt trigger converts any arbitrary
waveform into a square/Rectangle wave.
CALCULATIONS:
Calculation of UTP:
(V 'VBE 2 ) Re (h fe 1)
VEN (hfe of 2N 2369 is 50)
Rb Re (h fe 1)
V’ and Rb is the Thevenins equivalent voltage and resistance between base of Q2 and ground when
Q1 is in cut-off.
Vcc R2 R2 ( Rc1 R1
V ' = Rb
Rc1 R1 R2 Rc1 R1 R2
Calculation of LTP:
Re
LTP VBE1 (V 'Vr 2 )
aR Re
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
R2
a (a=Voltage ratio from collector of Q1 to base of Q2 )
R1 R2
R2 ( Rc1 R1
R (Where R is the Thevenins Equivalent Resistance when Q2 is
Rc1 R1 R2
in cut-off)
PRECAUTIONS:
REVIEW QUESTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
GRAPH:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO: 9
UJT RELAXATION OSCILLATOR
AIM: To obtain a sawtooth waveform using UJT and test its performance as an oscillator.
APPARATUS REQUIRED:
CIRCUIT DIAGRAM :
R1 V CC =12V
47 KΩ
E B2
2N2646
B1
R2
100Ω
C ? 1. Emitter 2. Base1 3. Base2
0.1 µF
? Figure:5
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
THEORY:
A Unijunction transistor (UJT), as the very implies, has only one p-n junction, unlike a BJT which
has two p-n junctions’.
R B2
IE
V BB
R B1 V1
VE
Figure:1 -
RB1 is the resistance between base B1 and the emitter, and it is basically a variable resistance, its value
being dependent upon the emitter current IE.
RB2 is the resistance between base B2 and the emitter, and the value is fixed.
This value of the emitter voltage which makes the diode conduct is termed as peak voltage, and it is
denoted as VP.
We have VE = V? + V1,
It is obvious that if VE < VP, the UJT is OFF, and
if VE < VP, the UJT is ON.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
VE
VP Peak Point
Negative
resistance
region
VV
Valley Point
IE
0 IP IV
Figure 3.
The main application of UJT is in switching circuits wherein rapid discharging of capacitor is very
essential. Having understood the basic of UJT, we shall next study the working of UJT relaxation
oscillator.
R B2 R
B2 E
+
B1
C Vs
R B1
Figure:4
The UJT sweep circuit shown in the figure 4 consists of a UJT, a capacitor and a resistor arranged as
shown.
We studied that a UJT is OFF as long as VE < VP, the peak voltage. Hence initially when the UJT is
OFF, the capacitor C charges through the resistance R from the supply voltage V.
It is seen that when the capacitor voltage VS rises to the value VP the UJT readily conducts. When the
UJT becomes ON, the capacitor discharges and its voltage falls. When the voltage falls to the valley
point VV, the UJT becomes OFF and the capacitor charges again to VP.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
This cycle of charging and discharging of the capacitor C repeats, and as a result, a saw tooth
wave form of voltage across C is generated.
PROCEDURE:
1. Connect the circuit as shown in figure with designed values.
2. Note down the voltages and frequencies across C& R2 .
3. The time period of the output wave form is noted and is compared with theoretical value
T = R1 ? C[ ln {(VBB – VV) / (VBB – VP)}]
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
GRAPH:
RESULT: Sawtooth waveform using UJT and test its performance as an oscillator is verified.
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
EXPERIMENT NO: 10
APPARATUS REQUIRED:
1. Resistors (10KΩ) – 4 No.
2. Resistors (1KΩ) - 1 No
3. Capacitor (1000µF) - 1 No
4. Capacitor (0.01µF) - 1 No
5. Diode (IN4148) - 1 No
6. Transistors ( 2N2222) - 2 No
7.. Dual CRO - 1 No.
8. Connecting wires.
CIRCUIT DIAGRAM:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
THEORY: The input to Q1 is the gating waveform. Before the application of the gating waveform, at
t = 0, transistor Q1 is in saturation. The voltage across the capacitor C and at the base of Q2 is VCE(sat).
To ensure Q1 to be in saturation for t = 0, it is necessary that its current be at least equal to iCE / hFE so
that Rb < hfeR. With the application of the gating waveform at t = 0, Q1 is driven OFF. The current iC1
now flow into C and assuming units gain in the emitter follower V0 ? VCCt . When the sweep RC starts,
the diode is reverse biased, as already explained above, the current through R is supplied by C1. The
current VCC / R through C and R now flows from base to emitter of Q2.if the output V0 reaches the
voltage VCC in a time TS / Tg, then from above we have TS = RC.
EXPECTED WAVEFORMS:
F = 800Hz F = 3KHz
OBSERVATIONS:
PROCEDURE:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
PRECAUTIONS:
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Electronic Circuit Analysis & Pulse and Digital circuit Lab
GRAPH:
146