Digital Design Interview Questions - All In1: Only-Vlsi

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Digital Design
Interview
Questions - All
in 1
January 20, 2009
1.
How do you SHARE
convert a XOR
gate into a buffer and a Labels
inverter (Use only one XOR Interview Questions

gate for each)?
only-vlsi.blogspot.com/2009/01/digital-design-interview-questions.html 1/36
Answer
2. Implement an 2-input
AND gate using a 2x1 mux.
Answer
3. What is a multiplexer?
Answer
4. What is a ring counter?

Answer
A ring counter is a type of

counter composed of a
circular shift register. The

output of the last shift
register is fed to the input of

the rst register. For
example, in a 4-register
counter, with initial register
values of 1100, the

repeating pattern is: 1100,
0110, 0011, 1001, 1100, so

on.
5. Compare and Contrast
Synchronous and
Asynchronous reset.
Answer
Synchronous reset logic will
synthesize to smaller ip-

ops, particularly if the reset
is gated with the logic

generating the d-input. But
in such a case, the

combinational logic gate
count grows, so the overall
gate count savings may not

be that signi cant. The clock
works as a lter for small

reset glitches; however, if
these glitches occur near the

active clock edge, the Flip-
op could go metastable. In
some designs, the reset must
be generated by a set of
internal conditions. A
synchronous reset is
recommended for these
types of designs because it

will lter the logic equation
glitches between clock.

Problem with synchronous
resets is that the synthesis
tool cannot easily

distinguish the reset signal
from any other data signal.
Synchronous resets may
need a pulse stretcher to
guarantee a reset pulse
width wide enough to

ensure reset is present
during an active edge of the
clock, if you have a gated
clock to save power, the

clock may be disabled
coincident with the
assertion of reset. Only an
asynchronous reset will

work in this situation, as the
reset might be removed
prior to the resumption of
the clock. Designs that are
pushing the limit for data

path timing, can not afford
to have added gates and
additional net delays in the
data path due to logic

inserted to handle
synchronous resets.
Asynchronous reset: The

major problem with
asynchronous resets is the
reset release, also called
reset removal. Using an

asynchronous reset, the
designer is guaranteed not
to have the reset added to
the data path. Another
advantage favoring
asynchronous resets is that

the circuit can be reset with
or without a clock present.
Ensure that the release of
the reset can occur within

one clock period else if the
release of the reset occurred
on or near a clock edge then
ip- ops may go into

metastable state.
6. What is a Johnson
counter?
Answer
7. An assembly line has 3 fail
safe sensors and one
emergency shutdown
switch.The line should keep
moving unless any of the
following conditions arise:
(1) If the emergency switch

is pressed
(2) If the senor1 and sensor2
are activated at the same
time.
(3) If sensor 2 and sensor3
are activated at the same

time.
(4) If all the sensors are
activated at the same time
Suppose a combinational
circuit for above case is to be
implemented only with
NAND Gates. How many
minimum number of 2 input

NAND gates are required?
Answer
8. In a 4-bit Johnson counter

How many unused states are
present?
Answer
4-bit Johnson counter:
0000, 1000, 1100, 1110,

1111, 0111, 0011, 0001,
0000.
8 unused states are present.
9. Design a 3 input NAND
gate using minimum number

of 2 input NAND gates.
Answer
10. How can you convert a
JK ip- op to a D ip- op?
Answer
Connect the inverted J input

to K input.
11. What are the differences

between a ip- op and a
latch?
Answer
12. What is the difference

between Mealy and Moore
FSM?
Answer
13. What are various types

of state encoding
techniques? Explain them.
Answer
One-Hot encoding: Each

state is represented by a bit
ip- op). If there are four
states then it requires four
bits (four ip- ops) to

represent the current state.
The valid state values are

1000, 0100, 0010, and
0001. If the value is 0100,

then it means second state is
the current state.
One-Cold encoding: Same

as one-hot encoding except
that '0' is the valid value. If

there are four states then it
requires four bits (four ip-

ops) to represent the
current state. The valid state
values are 0111, 1011,

1101, and 1110.
Binary encoding: Each state

is represented by a binary
code. A FSM having '2 power

N' states requires only N
ip- ops.
Gray encoding: Each state is

represented by a Gray code.
A FSM having '2 power N'

states requires only N ip-
ops.
14. De ne Clock Skew ,

Negative Clock Skew,
Positive Clock Skew.

Answer
Clock skew is a phenomenon

in synchronous circuits in
which the clock signal (sent

from the clock circuit)
arrives at different
components at different
times. This can be caused by
many different things, such

as wire-interconnect length,
temperature variations,
variation in intermediate
devices, capacitive coupling,
material imperfections, and
differences in input
capacitance on the clock
inputs of devices using the

clock.
There are two types of clock
skew: negative skew and

positive skew. Positive skew
occurs when the clock
reaches the receiving

register later than it reaches
the register sending data to
the receiving register.
Negative skew is the

opposite: the receiving
register gets the clock
earlier than the sending

register.
15. Give the transistor level

circuit of a CMOS NAND
gate.
Answer
16. Design a 4-bit

comparator circuit.
Answer
17. Design a Transmission
Gate based XOR. Now, how

do you convert it to XNOR
(without inverting the
output)?
Answer
18. De ne Metastability.
Answer
19. Compare and contrast

between 1's complement
and 2's complement

notation.
Answer
20. Give the transistor level

circuit of CMOS, nMOS,
pMOS, and TTL inverter
gate.
Answer
21. What are set up time and

hold time constraints?
Answer
22. Give a circuit to divide
frequency of clock cycle by

two.
Answer
23. Design a divide-by-3
sequential circuit with 50%

duty circle.
Answer
24. Explain different types
of adder circuits.
Answer
25. Give two ways of

converting a two input
NAND gate to an inverter.
Answer
26. Draw a Transmission

Gate-based D-Latch.
Answer
27. Design a FSM which

detects the sequence 10101
from a serial line without

overlapping.
Answer
28. Design a FSM which

detects the sequence 10101
from a serial line with

overlapping.
Answer
29. Give the design of 8x1
multiplexer using 2x1

multiplexers.
Answer
30. Design a counter which
counts from 1 to 10 ( Resets

to 1, after 10 ).
Answer
31. Design 2 input AND, OR,
and EXOR gates using 2

input NAND gate.
Answer
32. Design a circuit which

doubles the frequency of a
given input clock signal.
Answer
33. Implement a D-latch

using 2x1 multiplexer(s).
Answer
34. Give the excitation table

of a JK ip- op.
Answer
35. Give the Binary,

Hexadecimal, BCD, and
Excess-3 code for decimal
14.
Answer
36. What is race condition?

Answer
37. Give 1's and 2's

complement of 19.
Answer
38. Design a 3:6 decoder.

Answer
39. If A*B=C and C*A=B

then, what is the Boolean
operator * ?
Answer
40. Design a 3 bit Gray

Counter.
Answer
41. Expand the following:

PLA, PAL, CPLD, FPGA.
Answer
42. Implement the functions:

X = A'BC + ABC + A'B'C' and
Y = ABC + AB'C using a PLA.
Answer
43. What are PLA and PAL?

Give the differences
between them.
Answer
44. What is LUT?

Answer
45. What is the signi cance

of FPGAs in modern day
electronics? (Applications of
FPGA.)
Answer
46. What are the differences

between CPLD and FPGA.
Answer
47. Compare and contrast

FPGA and ASIC digital
designing.
Answer
48. Give True or False.
(a) CPLD consumes less

power per gate when
compared to FPGA.
(b) CPLD has more
complexity than FPGA
(c) FPGA design is slower
than corresponding ASIC
design.
(d) FPGA can be used to
verify the design before
making a ASIC.
(e) PALs have programmable
OR plane.
(f) FPGA designs are
cheaper than corresponding
ASIC, irrespective of design
complexity.
Answer
49. Arrange the following in

the increasing order of their
complexity:
FPGA,PLA,CPLD,PAL.
Answer
50. Give the FPGA digital

design cycle.
Answer
51. What is DeMorgan's

theorem?
Answer
52. F'(A, B, C, D) = C'D +

ABC' + ABCD + D. Express F
in Product of Sum form.
Answer
53. How many squares/cells

will be present in the k-map
of F(A, B, C)?
Answer
54. Simplify F(A, B, C, D) = S (

0, 1, 4, 5, 7, 8, 9, 12, 13)
Answer
55. Simplify F(A, B, C) = S (0,

2, 4, 5, 6) into Product of
Sums.
Answer
56. The simpli ed

expression obtained by
using k-map method is
unique. True or False.
Explain your answer.

Answer
57. Give the characteristic

tables of RS, JK, D and T ip-
ops.
Answer
58. Give excitation tables of

RS, JK, D and T ip- ops.
Answer
59. Design a BCD counter
with JK ip- ops

Answer
60. Design a counter with

the following binary
sequence 0, 1, 9, 3, 2, 8, 4
and repeat. Use T ip- ops.
Answer
LABELS: INTERVIEW
QUESTIONS
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January 20, 2009

inverter (Use only one XOR Interview Questions

4. What is a ring counter?

A ring counter is a type of

circular shift register. The

register is fed to the input of

values of 1100, the

0110, 0011, 1001, 1100, so

5. Compare and Contrast

Synchronous reset logic will

synthesize to smaller ip-

is gated with the logic

in such a case, the

count grows, so the overall

gate count savings may not

works as a lter for small

these glitches occur near the

types of designs because it

glitches between clock.

resets is that the synthesis

tool cannot easily

from any other data signal.

Synchronous resets may

need a pulse stretcher to

guarantee a reset pulse

width wide enough to

during an active edge of the

clock, if you have a gated

clock to save power, the

coincident with the

assertion of reset. Only an

asynchronous reset will

reset might be removed

prior to the resumption of

the clock. Designs that are

pushing the limit for data

to have added gates and

additional net delays in the

data path due to logic

Asynchronous reset: The

asynchronous resets is the

reset release, also called

reset removal. Using an

designer is guaranteed not

to have the reset added to

the data path. Another

asynchronous resets is that

or without a clock present.

Ensure that the release of

the reset can occur within

release of the reset occurred

on or near a clock edge then

ip- ops may go into

7. An assembly line has 3 fail

safe sensors and one

moving unless any of the

following conditions arise:

(1) If the emergency switch

(2) If the senor1 and sensor2

are activated at the same

are activated at the same