DAC Design

EE247
Lecture 14
• Data Converters
– Data converter testing (continued)
• DNL & SNR, INL & SFDR
• Effective number of bits (ENOB)
– D/A converter design
• Architectures
• Performance
– Static
– Dynamic
EECS 247- Lecture 14 Data Converters:Testing - DAC Design © 2007 H.K. Page 1
Summary Last Lecture

• Data Converters
– Static testing (continued)
• ………………..
• Histogram testing
– Dynamic tests
• Spectral testingÆ Reveals ADC errors associated with
dynamic behavior i.e. ADC performance as a function of
frequency
– Direct Discrete Fourier Transform (DFT) based
measurements utilizing sinusoidal signals
– DFT measurements including windowing
INL & SFDR
DNL & SNR
INL & SFDR DNL & SNR

• Depends on "shape" of INL Assumptions:
• DNL pdf Æuniform
• Rule of Thumb: • No missing code
SFDR ≅ 20 log(2B/INL) 2
1 ⎛⎜ 2 N Δ ⎞⎟
2 ⎜⎝ 2 ⎟⎠
– E.g. 1LSB INL, 10b SQNR = 2
Æ SFDR≅60dB Δ DNL2
+
12 3
Uniform DNL?
250
# of occurrences
200
150
100
50
0
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
DNL
• DNL distribution of 12-bit ADC test chip

• Not quite uniform...
Effective Number of Bits (ENOB)
• Is a 12-Bit converter with 68dB SNDR really a

12-Bit converter?
• Effective Number of Bits (ENOB)

SNDR − 1.76dB
ENOB =
6.02dB
68 − 1.76
= = 11.0Bits
6.02
ENOB
• At best, we get "ideal" ENOB only for zero
thermal noise, zero DNL, zero INL
• Low noise design is costly Æ 4x penalty in

power per (ENOB-) bit or 6dB extra SNDR
• Rule of thumb for good performance /power

tradeoff: ENOB < N-1
ENOB Survey
R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on

Selected Areas in Communications, pp. 539-50, April 1999
Example: ADC Spectral Tests
SFDR
SDR
SNR
Ref: W. Yang et al., "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR
at Nyquist input," IEEE J. of Solid-State Circuits, Dec. 2001
D-to-A Converter Design
D/A Converter Transfer Characteristics

MSB LSB
• An ideal digital-to-analog b1 b2 b3 bn
converter: ……..…
Vo or Io
– Accepts digital inputs D/A
b1-bn
– Produces either an Nomenclature:
analog output voltage or
N = # of bits
current
VFS = f u l l s cal e o u tp u t
– Assumption
• Uniform, binary Δ = mi n . s t ep s iz e → 1L SB
digital encoding VFS
Δ=
• Unipolar output 2N
V
ranging from 0 to VFS o r N = lo g2 F S → r es ol u ti o n
Δ
D/A Converters
• D/A architecture examples
– Resistor string DAC
– Charge Redistribution DAC
– Current source type
• Static performance
– Limited by component matching
– Architectures
• Unit element
• Binary weighted
• Segmented
– Dynamic element matching
• Dynamic performance
– Limited by timing errors causing glitches
D/A Converters
• Comprises voltage or charge or

current based elements
• Examples for above three categories:

– Resistor string Æ voltage
– Charge redistribution Æ charge
– Current source type Æ current
Resistor String DAC
Voltage based: Vref
A B-bit DAC requires: 2B R
resistors in series R
All resistors equal
R
Æ Generates 2B R
equally spaced
R
voltages ready to
be chosen based R
on the digital input R
word
R
3-Bit Resistor String DAC
R-String DAC
Example
Vref
Example:
• Input code: 7Vref /8
[d2 d1 d0]=101
6Vref /8
Æ Vout= 5Vref /8
5Vref /8
• Assuming switch 4Vref /8 Vout =
resistance << R: 5Vref /8
3Vref /8 C
τsettling = (3R||5R) x C 2Vref /8
=0.23 x 8RC
Vref /8
R
R-String DAC
• Advantages:
– Takes full advantage of availability Vref
of almost perfect switches in MOS
technologies
– Simple, fast for <8-10bits
– Inherently monotonic
– Compatible with purely digital
technologies
• Disadvantages:
– 2B resistors & ~2x2B switches for B C
bits Æ High element count & large
area for B >10bits
– High settling time for high resolution
DACs:
τmax ~ 0.25 x 2B RC
Ref:
M. Pelgrom, “A 10-b 50-MHz CMOS D/A Converter with 75-W Buffer,” JSSC, Dec. 1990, pp. 1347
R-String DAC
•Choice of resistor value: Vref
–Since maximum output settling
time:
τmax ~ 0.25 x 2B RC
–Choice of resistor value directly
affects DAC maximum
operating speed
C
–Power dissipation: function of
Vref2/ (Rx2B)
Æ Tradeoff between speed

and power dissipation
R-String DAC
• Resistor type: Vref
– Choice of resistive material
important
– Diffusion type R Æ high temp.

co. & voltage co.
• Results in poor INL/DNL
– Better choice is poly resistor

C
beware of poly R 1/f noise
– At times, for high-frequency &

high performance DACs, metal
R (beware of high temp. co.) or
thin film R is used
R-String DAC
Layout Considerations
• Number of resistor segments Æ 2B
–E.g. 10-bit R-string DAC Æ1024 resistors
• Low INL/DNL dictates good R matching

R-String Layout
.. ..
.. ..
• Layout quite a challenge
–Good matching mandates all R segments
either vertical or horizontal - not both
–Matching of metal interconnect and contacts
–Need to fold the string
• Difficult to match corner segments to rest
• Could result in large INL/DNL
ner
Cor
R-String DAC
Including Interpolation
Resistor string DAC Vref
+ Resistor string interpolator increases
resolution w/o drastic increase in
complexity
e.g. 10bit DACÆ (5bit +5bitÆ 2x25=26 #
of Rs) instead of direct 10bitÆ210
Vout
Considerations:
Main R-string loaded by the
interpolation string
Large R values for interpolating
stringÆ less loading but lower speed
Can use buffers
R-String DAC
Including Interpolation
Vref
Use buffers to prevent

loading of the main
ladder
Issues:
Æ Buffer DC offset
Æ Buffer limited
bandwidth effect on
overall speed
Charge Based: Serial Charge Redistribution DAC
Simplified Operation
Nominally C1=C2
• Conversion sequence:
– Initialize: Discharge C2 & charge C1 to VREF Æ S2& S4 closed
– Charge share: close S1Æ VC2=VC1=VREF/2
Serial Charge Redistribution DAC

Simplified Operation (Cont’d)
Nominally C1=C2
– Next cycle
• If S3 closed VC1=0 then when S1 closes VC1 = VC2 = VREF/4
• If S2 closed VC1=VREF then when S1 closes VC1 =VC2 =VREF/2+VREF/4
• Nominally C1=C2
– Discharge C1 & C2Æ S3&
S4 closed
– For each bit in succession
beginning with LSB, b1:
• S1 open- if bi=1 C1
precharge to VREF if bi=0
discharged to GND
• S2 & S3 & S4 open- S1
closed- Charge sharing C1
& C2
Æ ½ of precharge on C1
+½ of charge
previously stored on
C2Æ C2

Example: Input Code 101
LSB
MSB
b3 b2 b1
• Example input code 101Æ output (1/8 +0/8 +4/8 )VREF =5/8 VREF
• Very small area
• N redistribution cycles for N-bit conversion Æ quite slow
Parallel Charge Scaling DAC
• DAC operation based on capacitive voltage division
Vout
Cy Cx C Cx
Vout = Vref
Cx + Cy + C
Vref
Æ Make Cx & Cy function of incoming DAC digital word
Parallel Charge Scaling DAC

reset
Vout
2(B-1) C 8C 4C 2C C C
bB-1 (msb) b3 b2 b1 b0 (lsb)
Vref
B −1
• E.g. “Binary weighted” ∑ bi 2 i C
Vout = i =0 Vref
• B+1 capacitors & switches 2B C
(Cs built of unit elements
Æ 2B units of C)
Charge Scaling DAC
Example: 4Bit DAC- Input Code 1011
reset a- Reset phase b- Charge phase Vout
Vout
8C 4C 2C C C 8C 4C 2C C C
b3 b2
b3 b2 b1 b1 b0 (lsb)
b0 (lsb)
Vref Vref
20 C + 21 C + 23C 11
Vout = Vref = Vref
24 C 16
Charge Scaling DAC

reset CP
Vout
2(B-1) C 8C 4C 2C C C B −1

∑b 2 C i
i
Vout = i =0
Vref
2 B C + CP
Vref
• Sensitive to parasitic capacitor @ output

– If Cp constant Æ gain error
– If Cp voltage dependant Æ DAC nonlinearity
• Large area of caps for high DAC resolution (10bit DAC ratio
1:512)
• Monotonicity depends on element matching (more later)
Parasitic Insensitive
Charge Scaling DAC
CI
reset CP
-
2(B-1) C 8C 4C 2C C
Vout
+
Vref
B −1 B −1
∑ bi 2i C B
∑ bi 2i
Vout = i =0 Vref , CI = 2 C → Vout = i =0 Vref
CI 2B
• Opamp helps eliminate the parasitic capacitor effect by producing virtual

ground at the sensitive node since CP has zero volts at start & end
– Issue: opamp offset & speed
Charge Scaling DAC

Incorporating Offset Compensation
CI S2
reset
reset CP S1
-
S3 Vos
2(B-1) C 8C 4C 2C C reset Vout
+
Vref
• During reset phase:
– Opamp disconnected from capacitor array via switch S3
– Opamp connected in unity-gain configuration (S1)
– CI Bottom plate connected to ground (S2)
– Vout ~ - Vos Æ VCI = -Vos
• This effectively compensates for offset during normal phase
Charge Scaling DAC
Utilizing Split Array
reset 8/7C
+
C C 2C 4C C 2C 4C
- Vout
b0 b1 b2 b3 b4 b5
Vref
∑ all LSB arra y C
Cse rie s = C
∑ a ll MS B a rr ay C
• Split arrayÆ reduce the total area of the capacitors required for high
resolution DACs
– E.g. 10bit regular binary array requires 1024 unit Cs while split array
(5&5) needs 64 unit Cs
– Issue: Sensitive to parasitic capacitor
Charge Scaling DAC
• Advantages:
– Low power dissipation Æ capacitor array does not dissipate DC power
– Output is sample and held Æ no need for additional S/H
– INL function of capacitor ratio
– Possible to trim or calibrate for improved INL
– Offset cancellation almost for free
• Disadvantages:
– Process needs to include good capacitive material Æ not
compatible with standard digital process
– Requires large capacitor ratios
– Not inherently monotonic (more later)
Segmented DAC
Resistor Ladder (MSB) & Binary Weighted Charge Scaling (LSB)
• Example: 12bit
DAC
– 6-bit MSB DACÆ
R- string reset
– 6-bit LSB DAC Æ Vout
binary weighted 32 C 16C 8C 4C 2C C C
charge scaling ...
... b1 b0
• Complexity much ... b5 b4 b3 b2
lower compared to .
full R-string
– Full R stringÆ
6-bit
4096 resistors
binary weighted
– Segmented Æ 64 charge redistribution DAC
R + 7 Cs (64 unit 6bit
caps) resistor
ladder Switch
Network
Current based DAC

Unit Element Current Source DAC
……………
Iout
Iref Iref Iref Iref Iref

……………
• “Unit elements” or thermometer

• 2B-1 current sources & switches
• Suited for both MOS and BJT technologies
• Monotonicity does not depend on element matching
• Output resistance of current source Æ gain error
– Cascode type current sources higher output resistance Æ less gain
error
Current Source DAC
Unit Element R
…………… -
Vout
+
Iref Iref Iref Iref

……………
• Output resistance of current source Æ gain error problem

Æ Use transresistance amplifier
- Current source output held @ virtual ground
- Error due to current source output resistance eliminated
- New issues: offset & speed of the amplifier
Current Source DAC

Binary Weighted
……………
Iout
2B-1 Iref 4 Iref 2Iref Iref

……………
• “Binary weighted”
• B current sources & switches (2B-1 unit current
sources but less # of switches)
• Monotonicity depends on element matching
R-2R Ladder Type DAC
• R-2R DAC Basics
R V/2
– Simple R network I/2 I/2
divides both I
V
voltage & current 2R 2R
by 2
Increase # of bits by replicating circuit
R-2R Ladder DAC
Iout
VB
2R 2R 2R 2R 2R 2R
R R R R
VEE
Emitter-follower added to convert to high output impedance current

sources
Æ Series switch resistance does not impair performance
R-2R Ladder DAC
How Does it Work?
Consider a simple 3bit R-2R DAC:
Iout
VB 4Aunit 2Aunit Aunit Aunit
2R 2R 2R 2R
R R
VEE
R-2R Ladder DAC

How Does it Work?
Simple 3bit DAC:
1- Consolidate first two stages:
IT I2 I1+IT
I3 I2 I1 I3
VB Q3 Q2 Q1 QT VB Q3 Q2
4Aunit 2Aunit Aunit Aunit 4Aunit 2Aunit 2Aunit
2R 2R 2R 2R 2R 2R R
R R R R
VEE VEE
R-2R Ladder DAC
How Does it Work?
Simple 3bit DAC-
2- Consolidate next two stages:
I1+IT I2+I1+IT
I3 I2 I3
VB Q3 Q2 VB Q3 Q2
4Aunit 2Aunit 2Aunit 4Aunit 4Aunit
2R 2R R 2R R
R R R
VEE VEE
I I I
I3 = I2 + I1 + IT → I3 = T ot al , I2 = T ot a l , I1 = To t al
2 4 8
R-2R Ladder DAC

How Does it Work?
Consider a simple 3bit R-2R DAC:
Iout
VB 4Aunit 2Aunit Aunit

Aunit
4I 2R 2I 2R I 2R I 2R
R R
VEE
4I 2I
Ref: B. Razavi, “Data Conversion System Design”, IEEE Press, 1995, page 84-87
R-2R Ladder DAC
RTotal
R
-
+ Vout
VB
16I 2R 8I 2R 4I 2R 2I 2R I 2R I 2R
R R R R
VEE
16I 8I 4I 2I
Transresistance amplifier added to:
- Convert current to voltage
- Generate virtual ground @ current summing node so that output
impedance of current sources do not cause error
- Issue: error due to opamp offset
R-2R Ladder DAC

Opamp Offset Issue
out = V in ⎛ 1 +
Vos
R ⎞ R
os ⎜ ⎟
⎝ R T ot al ⎠
RTotal
If R T ota l = l a r g e, -
out in
→ Vos ≈ Vos
+ Vout
If RT ota l = n o t l a rg e Vos
out in ⎛ 1 + R ⎞
→ Vos = Vos ⎜ RT ot al ⎟ Offset Model
⎝ ⎠
P r ob l em :
S i nce RT ota l i s co d e d ep en d an t
ou t
→ Vos w ou l d b e co de d ep en da n t
→ G i ves r i s e t o I N L & DN L
R-2R Ladder
Summary
• Advantages:
– Resistor ratios only x2
– Does not require precision capacitors
• Disadvantages:
– Total device emitter area Æ AEunitx 2B
Æ Not practical for high resolution DACs
– INL/DNL error due to amplifier offset
Static DAC Errors -INL / DNL

Static DAC errors mainly due to component mismatch
– Systematic errors
• Contact resistance
• Edge effects in capacitor arrays
• Process gradients
• Finite current source output resistance
– Random variations
• Lithography etc…
• Often Gaussian distribution (central limit theorem)
*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSC
Aug. 1989, pp. 1118-28.
Current Source DAC
DNL/INL Due to Element Mismatch
-
Vout
+
Iref Iref Iref Iref Iref
Iref -ΔI Iref +ΔI
• Simplified example:
– 3-bit DAC
– Assume only two of the current sources mismatched (# 4 & #5)
Current Source DAC

DNL/INL Due to Element Mismatch
seg men t[ m] − V [ L S B ] Analog

DN L[ m] = Output
V [ LSB] 7 Iref R
seg men t[ 4 ] − V [ L S B ] 6
DN L[ 4 ] =
V [ LSB]
5
( I − Δ I )R − IR
= 4
IR
DN L[ 4 ] = −Δ I / I [ LSB ] 3
( I + Δ I )R − IR 2
DN L[ 5] =
IR
1xIref R
DN L[ 5 ] = Δ I / I [ L S B ] Digital
Input
→ IN Lmax = −Δ I / I [ L S B ] 0
000 001 010 011 100 101 110 111
Component Mismatch
Probability Distribution Function
• Component parameters Æ Random variables
• Each component is the product of many fabrication steps

• Most fabrication steps includes random variations
ÆOverall component variation product of several random variables
ÆAssuming each of these variables have a uniform distribution:

ÆJoint pdf of a random variable affected by two uniformly
distribution is the convolution of the two uniform pdfs…….
pdf [f(x1)] pdf [f(x2)] pdf [f(x1,x2)]
* Æ
pdf [f(x1,x2)] pdf [f(x3,x4)] pdf [f(xm,xn)] Gaussian pdf
..……..
* * Æ
Gaussian Distribution
0.4
Probability density p(x)
0.3
0.2
2 0.1
−(
x−μ )
1 2σ 2
p( x ) = e
2πσ 0
-3 -2 -1 0 1 2 3
where: (x-μ) /σ
μ is the expected value and
standard deviation :σ = E( X 2 ) − μ 2
σ 2 → variance
Yield
In most cases we are
0.4
Probability density
interested in finding the
0.3
percentage of
p(x)
components (e.g. R) 0.2
falling within certain 0.1
bounds: 0
P (− X ≤ x ≤ + X ) = 1
P(-X ≤ x ≤ +X)
95.4
2
0.8
+X −x 0.6 68.3
1
=
2π
∫
−X
e 2 dx 0.4 38.3
0.2
0
⎛ X ⎞ 0 0.5 1 1.5 2 2.5 3
= e rf ⎜ ⎟ X/σ
⎝ 2⎠
Yield
X/σ P(-X ≤ x ≤ X) [%] X/σ P(-X ≤ x ≤ X) [%]
0.2000 15.8519 2.2000 97.2193

0.4000 31.0843 2.4000 98.3605
0.6000 45.1494 2.6000 99.0678
0.8000 57.6289 2.8000 99.4890
1.0000 68.2689 3.0000 99.7300
1.2000 76.9861 3.2000 99.8626
1.4000 83.8487 3.4000 99.9326
1.6000 89.0401 3.6000 99.9682
1.8000 92.8139 3.8000 99.9855
2.0000 95.4500 4.0000 99.9937
Example
• Measurements show that the offset voltage of
a batch of operational amplifiers follows a
Gaussian distribution with σ = 2mV and μ = 0.
• Fraction of opamps with |Vos| < 6mV:

– X/σ = 3 Æ 99.73 % yield
• Fraction of opamps with |Vos| < 400μV:

– X/σ = 0.2 Æ 15.85 % yield
Component Mismatch
Example: Resistors layouted out
400
side-by-side
No. of resistors
300
……. ……. ΔR
200
R
100
After fabrication large # of
devices measured 0
& graphed Æ typically if 988 992 996 1000 1004 1008 1012
sample size large shape R[ Ω ]
is Gaussian E.g. Let us assume in this example 1000 Rs measured
& 68.5% within +-4OHM or +-0.4% of average
Æ 1σ for resistorsÆ 0.4%
Component Mismatch
Example: Two resistors 0.4
Probability density p(x)

layouted out side-by-side 0.35
0.3
0.25 ΔR
0.2
R
0.15
R1 + R2 0.1
R= 0.05
2
0
dR = R1 − R2 −3σ −2σ −σ 0 σ 2σ 3σ
dR
For typical technologies & geometries R
1 1σ for resistors Æ 0.02 to 5%
σ dR
2
∝
Are a
R In the case of resistors σ is a function of area
DNL Unit Element DAC

E.g. Resistor string DAC: 2B − 1
∑o Ri Vref
Δ = Rm ed ia n I ref whe re Rm edia n =
B
2 Iref
Δi = Ri I re f
Δi − Δm e dian
DNLi =
Δme dian
Ri − R
=
me dian
=
dR
≈
dR Δi = Ri I ref
R R Ri
me dian m edia n
σ D NL = σ dRi
Ri
DNL of unit element DAC is
independent of resolution!
E.g. Resistor string DAC:
Example:
If σdR/R = 0.4%, what
σ D NL = σ dR i
DNL spec goes into
Ri the datasheet so that
99.9% of all converters
meet the spec?
To first order Æ DNL of unit element DAC is independent of resolution!

Note similar results for other unit-element based DACs
Yield
X/σ P(-X ≤ x ≤ X) [%] X/σ P(-X ≤ x ≤ X) [%]
0.2000 15.8519 2.2000 97.2193

0.4000 31.0843 2.4000 98.3605
0.6000 45.1494 2.6000 99.0678
0.8000 57.6289 2.8000 99.4890
1.0000 68.2689 3.0000 99.7300
1.2000 76.9861 3.2000 99.8626
1.4000 83.8487 3.4000 99.9326
1.6000 89.0401 3.6000 99.9682
1.8000 92.8139 3.8000 99.9855
2.0000 95.4500 4.0000 99.9937
E.g. Resistor string DAC: Example:
If σdR/R = 0.4%, what DNL spec
goes into the datasheet so that
99.9% of all converters meet
σ D NL = σ dR i
the spec?
Ri Answer:
From table: for 99.9%
Æ X/σ = 3.3
σDNL = σdR/R = 0.4%
3.3 σDNL = 1.3%
ÆDNL= +/- 0.013 LSB
DAC INL Analysis

Ideal Variance
N A=n+E n n.σε2
B B=N-n+E N-n (N-n).σε2

Output [LSB]
E
E = A-n r =n/N N=A+B
n A = A-r(A+B)
= A (1-r) -B.r
Æ Variance of E:
n N=2B-1
Input [LSB]
σE2 =(1-r)2 .σΑ2 + r 2 .σB2
=N.r .(1-r).σε2
DAC INL
σINL/σε
2 ⎛ n⎞ (2B-1)0.5/2
σE = n ⎜ 1 − ⎟ ×σ ε 2
⎝ N⎠
dσ E 2
T o f i nd m a x . v aria n c e : =0
dn
→ n=N /2
• Error is maximum at mid-scale (N/2):
1
σ I NL = 2B − 1 σ ε 0
2 0 0.5 1
with N = 2B − 1 n/N
• INL depends on DAC resolution and element matching σε
• While σDNL = σε is to first order independent of DAC resolution and is
only a function of element matching
Ref: Kuboki et al, TCAS, 6/1982
Untrimmed DAC INL

Example:
1 B Assume the following requirement for a

σ INL ≅ 2 −1σε
2 DAC:
σINL = 0.1 LSB
⎡σ ⎤
B ≅ 2 + 2 log2 ⎢ INL ⎥ Then:
⎣ σε ⎦
σε = 1% Æ B = 8.6
σε = 0.5% Æ B = 10.6
σε = 0.2% Æ B = 13.3
σε = 0.1% Æ B = 15.3
Simulation Example
12 Bit converter DNL and INL
2
DNL [LSB]
-0.04 / +0.03 LSB

1 σε = 1%
B = 12
0
Random #
-1
generator used
500 1000 1500 2000 2500 3000 3500 4000
in MatLab
bin
2
-0.2 / +0.8 LSB

INL LSB]
1
Computed INL:
0 σINL = 0.3 LSB
-1
(midscale)
500 1000 1500 2000 2500 3000 3500 4000
bin

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EE247

Summary Last Lecture

INL & SFDR DNL & SNR

• DNL distribution of 12-bit ADC test chip

• Is a 12-Bit converter with 68dB SNDR really a

• Effective Number of Bits (ENOB)

• Low noise design is costly Æ 4x penalty in

• Rule of thumb for good performance /power

R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on

Example: ADC Spectral Tests

D/A Converter Transfer Characteristics

• Comprises voltage or charge or

• Examples for above three categories:

3-Bit Resistor String DAC

Æ Tradeoff between speed

– Diffusion type R Æ high temp.

– Better choice is poly resistor

– At times, for high-frequency &

• Low INL/DNL dictates good R matching

Use buffers to prevent

Serial Charge Redistribution DAC

Serial Charge Redistribution DAC

Æ Make Cx & Cy function of incoming DAC digital word

Parallel Charge Scaling DAC

bB-1 (msb) b3 b2 b1 b0 (lsb)

Charge Scaling DAC

bB-1 (msb) b3 b2 b1 b0 (lsb)

• Sensitive to parasitic capacitor @ output

• Opamp helps eliminate the parasitic capacitor effect by producing virtual

Charge Scaling DAC

bB-1 (msb) b3 b2 b1 b0 (lsb)

Charge Scaling DAC

Current based DAC

Iref Iref Iref Iref Iref

• “Unit elements” or thermometer

Iref Iref Iref Iref

• Output resistance of current source Æ gain error problem

Current Source DAC

2B-1 Iref 4 Iref 2Iref Iref

Increase # of bits by replicating circuit

R-2R Ladder DAC

Emitter-follower added to convert to high output impedance current

VB 4Aunit 2Aunit Aunit Aunit

R-2R Ladder DAC

4Aunit 2Aunit Aunit Aunit 4Aunit 2Aunit 2Aunit

4Aunit 2Aunit 2Aunit 4Aunit 4Aunit

R-2R Ladder DAC

VB 4Aunit 2Aunit Aunit

R-2R Ladder DAC

Static DAC Errors -INL / DNL

Iref Iref Iref Iref Iref

Iref -ΔI Iref +ΔI

Current Source DAC

seg men t[ m] − V [ L S B ] Analog

• Each component is the product of many fabrication steps

ÆAssuming each of these variables have a uniform distribution:

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• Fraction of opamps with |Vos| < 6mV:

• Fraction of opamps with |Vos| < 400μV:

Probability density p(x)

DNL Unit Element DAC

To first order Æ DNL of unit element DAC is independent of resolution!

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ÆDNL= +/- 0.013 LSB