Digital Logic Design

Chapter 4

Sequential Circuits

0
 Sequential Circuits
• Most digital systems like digital watches, digital phones,
personal computers, digital traffic light controllers and so on
require memory elements.
• Memory elements are Combinational
digital circuits that can outputs Memory outputs
store and retrieve data
in the form of 1's and
0's.
Combinational Memory
• The output of the logic elements
systems with memory
depends not only on
present inputs but also
on what has happened
in the past External inputs

Sequential circuit = Combinational logic + Memory Elements

1
 Sequential Circuits
 There are two types of sequential circuits:
 synchronous: outputs change only at specific time

 asynchronous: outputs change at any time

Inputs Outputs
Combinational
Circuit

Flip-flops
Clock
Inputs Outputs
Combinational
Circuit
Memory
Elements

2
 Memory Elements
 Memory element: a device which can remember value
indefinitely, or change value on command from its
inputs.

Memory Q
Command element Stored value

 Characteristic table: Q(t): current state

Q(t+1) or Q+: next state
Command Q(t) Q(t+1)
(at time t)
Set X 1
Reset X 0
Memorise / 0 0
No Change 1 1

3
Latch vs Flip-Flops
 A latch is a type temporary data storage device(memory
element) that have two possible states( i.e. it is bistable
device).
 A flip-flop is synchronous bistable device(memory element)
that changes state at specified point.
 Similarity: Both are bistable devices.
 Differences: Latches are level sensitive devices and flip-
flops are edge sensitive devices.
 In other words, Latches are Asynchronous and Flip-flops
are synchronous devices.
 Latches are the building block of Flip-flops.
4
Set-Reset (S-R) Latch

 Complementary outputs: Q and Q'.

 When Q is HIGH, the latch is in SET state.
 When Q is LOW, the latch is in RESET state.
 For active-HIGH input S-R latch (NOR gate latch) ,
 R=HIGH (and S=LOW) a RESET state
 S=HIGH (and R=LOW) a SET state
 both inputs LOW a no change
 both inputs HIGH a Q and Q' both LOW (invalid)!

S Q

R Q’
5
 S-R Latch

 For active-LOW input S'-R' latch (also known as

NAND gate latch),
● R'=LOW (and S'=HIGH) a RESET state
● S'=LOW (and R'=HIGH) a SET state
● both inputs HIGH a no change
● both inputs LOW a Q and Q' both HIGH (invalid)!

S
Q

R Q'

6
S-R Latch

 Characteristics table for active-high input S-R latch:

S R Q Q'
No change. Latch S Q
0 0 NC NC
remained in present state.
1 0 1 0 Latch SET. R
Q'
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.

 Characteristics table for active-low input S'-R' latch:

S' R' Q Q'
S Q
1 1 NC NC No change. Latch
remained in present state.
R
0 1 1 0 Latch SET. Q'
1 0 0 1 Latch RESET.
0 0 1 1 Invalid condition.

7
 S-R Latch
 SR Latch implementation
S R Q0 Q Q’
0 0 0 0 1 Q = Q0

R
0 0
Q

S Q
0 1

Initial Value

8
 S-R Latch
 SR Latch implementation
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R
0 1
Q

S Q
0 0

9
 S-R Latch
 SR Latch implementation
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 0
Q

S Q
0 1

10
 S-R Latch
 SR Latch implementation
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 1 0 1 1 0 1 Q=0
Q

S Q
0 0

11
 S-R Latch
 SR Latch implementation
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1

S Q
1 1

12
 S-R Latch
 SR Latch implementation
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 1 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0

13
 S-R Latch
 SR Latch implementation
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1 0 Q=0
0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 0

14
 S-R Latch
 SR Latch implementation
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 1 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0

15
 S-R Latch
 SR Latch implementation
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0
S Q
1 0

16
 Exercise
 Construct the characteristics table for the following
S R Q0 Q Q’
0 0 0
0 10
S Q

R Q
0 0

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S-R Latch (Active-high and Active-low)

S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S R Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
Q 1 0 0 Reset
R Q0 No change
1 1
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SR Latch with Control Input (Gated SR Latch)
 The operation of the basic SR latch can be modified by
providing an additional control input that determines when the
state of the latch can be changed.
 It consists of the basic SR latch and two additional AND/NAND
gates.
R R S S
Q Q
C C
S Q R Q
S R

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid 19
 Controlled Latches
D Latch (D = Data)
Timing Diagram
 D latch is designed to eliminate the
indeterminate state in SR latch by making sure
C
that inputs S and R are never equal to 1 at the
same time D
D S
Q Q
C
R Q
t
Output may
C D Q change
0 x Q0 No change
1 0 0 Reset
1 1 1 Set 20
 Controlled Latches

 D Latch (D = Data) Timing Diagram

S
C
D
Q
C D
R Q
Q

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

21
 Graphic Symbols for latches

• A latch is designated by a rectangular block with inputs on the

left and outputs on the right. One output designates the normal
output, and the other designates the complement output.

22
Latch Circuits: Not Suitable

 Latch circuits are not suitable in synchronous logic

circuits.
 When the enable/control signal is active, the excitation
inputs are gated directly to the output Q.
 Thus, any change in the excitation input immediately causes a
change in the latch output.
 The problem is solved by using a special timing control
signal called a clock to restrict the times at which the states
of the memory elements may change.
 This leads us to the edge-triggered memory elements
called flip-flops.

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Memory Elements
 Memory element with clock: Flip-flops are memory
elements that change state on clock signals.

Memory Q
command element stored value

clock

 Clock is usually a square wave.

Positive pulses

Positive edges Negative edges

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Edge-Triggered Flip-flops

 Controlled latches are level triggered

 Flip-flops: synchronous bistable devices

 Output changes state at a specified point on a triggering
input called the clock.
CLK Positive Edge

CLK Negative Edge

 Change state either at the positive edge (rising edge) or at

the negative edge (falling edge) of the clock signal.
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S-R Flip-flop
R Q
Pulse
CLK transition LATCH
detector
S Q’

The pulse transition detector.

CLK'
CLK'
CLK CLK* CLK CLK*

CLK
CLK
CLK'
CLK'

CLK*
CLK*
Positive-going transition Negative-going transition
(rising edge) (falling edge)

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Edge-Triggered Flip-flops

 S-R, D and J-K edge-triggered flip-flops. Note the “>”

symbol at the clock input.

S Q D Q J Q
C C C
R Q' Q' K Q'

Positive edge-triggered flip-flops

S Q D Q J Q
C C C
R Q' Q' K Q'

Negative edge-triggered flip-flops

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S-R Flip-flop

 S-R flip-flop: on the triggering edge of the clock pulse,

 S=HIGH (and R=LOW) a SET state
 R=HIGH (and S=LOW) a RESET state
 both inputs LOW a no change
 both inputs HIGH a invalid

 Characteristic table of positive edge-triggered S-R flip-flop:

S R CLK Q(t+1) Comments
0 0 X Q(t) No change
0 1  0 Reset
1 0  1 Set
1 1  ? Invalid

X = irrelevant (“don’t care”)

 = clock transition LOW to HIGH

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S-R Flip-flop

 It comprises 3 parts:
 a basic NAND/NOR latch

 a pulse-steering circuit

 a pulse transition detector (or edge detector) circuit

 The pulse transition detector detects a rising (or falling)

edge and produces a very short-duration spike.

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S-R Flip-flop

The pulse transition detector.

S
Q
Pulse
CLK transition
detector
Q'
R

CLK' CLK'
CLK CLK* CLK CLK*

CLK CLK

CLK' CLK'

CLK* CLK*

Positive-going transition Negative-going transition

(rising edge) (falling edge)

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 Edge-Triggered D Flip-Flop

• The first latch is called the master and the second the slave.
• The circuit samples the D input and changes its output Q only at
the negative-edge of the controlling clock.

D 110011…
Y 110011…
Q ? 1 1 0 0 1 ….
CLK
31
 Edge-Triggered D Flip-Flop
 When the clock is 0, the output of the inverter is 1.
● The slave latch is enabled, and its output Q is equal to the master output Y.
● The master latch is disabled because Clk=0.

 When the clock is 1,

● the data from the external D input are transferred to the master.
● The slave, however, is disabled because its enable/control input is equal to 0.
● Any change in the input changes the master output at Y, but cannot affect the
slave output.
 When the clock pulse returns to 0, the master is disabled and is isolated from
the D input. At the same time, the slave is enabled and the value of Y is
transferred to the output of the flip-flop at Q. 32
 Edge-Triggered D Flip-Flop

 Master-Slave D Flip-Flop
D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C

Master Slave
CLK
CLK

D
Looks like it is negative
edge-triggered QMaster

QSlave
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 Edge-Triggered D Flip-Flop

 It is also possible to design positive edge triggered D- Flip flop.

 This is done by adding inverter at input control of the master
latch.
 Such a flip-flop is triggered with a negative pulse, so that the
negative edge of the clock affects the master and the positive edge
affects the slave and the output terminal.

D Q D Q

Q Q

Negative Edge
Positive Edge

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D Flip-flop

 Application: Parallel data transfer.

To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2
and Q3 for storage.
D Q Q1 =
CLK X*
X Q'
Combinational Y D Q Q2 =
logic circuit
Z CLK Y*
Q'

D Q Q3 =
Transfer CLK Z*
Q'
* After occurrence of negative-going transition

35
 JK Flip-Flop

• There are three operations that can be performed with a flip-

flop: set it to 1, reset it to 0, or complement its output.
• The JK flip-flop performs all three operations.
• The circuit diagram of a JK flip-flop constructed with a D flip-
flop and gates.

J
D Q Q
K
CLK Q Q

36
 JK Flip-Flop
• The J input sets the flip-flop to 1, the K input resets it to 0, and when
both inputs are enabled, the output is complemented.
• This can be verified by investigating the circuit applied to the D input:
D = J Q` + K` Q

Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
J K CLK Q(t+1) Comments 1 0 1 0
1 1 0 1
0 0  Q(t) No change
1 1 1 0
0 1  0 Reset
1 0  1 Set
1 1  Q(t)' Toggle
37
T-Flip-Flop
• The T(toggle) flip-flop is a complementing flip-flop and can be
obtained from a JK flip-flop when inputs J and K are tied together.

T J Q D Q
T

K Q Q

D = JQ’ + K’Q T Q
D = TQ’ + T’Q = T  Q
Q

38
Flip-Flop Characteristic Tables

D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q
1 Q’(t) Toggle
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 Flip-Flop Characteristic Equations

 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
J Q 0 0 1 1 J KQ
0 1 0 0 0 1 0 0
0 1 1 0 1 1 0 1
K Q
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ’ + K’Q

40
Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q
1 Q’(t)
41
 Exercise
 A PN flip-flop has four operations: clear to 0, no change,
complement, and set to 1, when inputs P and N are 00, 01, 10, and
11, respectively.
(a) Tabulate the characteristic table.
(b) Derive the characteristic equation.
(c) Show how the PN flip-flop can be converted to a D flip-flop.

Solution (c) Connect P and N to D inputs

by using the characteristic
equation that is determined at b.

42
 Analysis of Clocked Sequential Circuits

 The analysis of a sequential circuit consists of obtaining a

table or a diagram for the time sequence of inputs, outputs,
and internal states.
 It is also possible to write Boolean expressions that describe
the behavior of the sequential circuit.

 The behavior of a clocked sequential circuit can be described

algebraically by means of state equations.
 A state equation specifies the next state as a function of the
present state and inputs.

43
 State Equation
• A state equation is an algebraic expression that specifies the
condition for a flip-flop state transition.
• The left side of the equation with (t+1) denotes the next state of the
flip-flop one clock edge later.
• The right side of the equation is Boolean expression that specifies
the present state and input conditions that make the next state equal
to 1.

A(t+1) = A(t) x(t) + B(t) x(t)

• The time sequence of inputs, outputs, and flip-flop states can be

enumerated in a state table (sometimes called transition table).

44
 Analysis of Clocked Sequential Circuits

 State Equations
x
A
A(t+1) = DA D Q

= A(t) x(t)+B(t) x(t) Q

=Ax+Bx
D Q B
B(t+1) = DB
CLK Q
= A’(t) x(t)
y
= A’ x
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’
45
 Analysis of Clocked Sequential Circuits

 State Table (Transition Table)

Present Next x
Input Output D Q A
State State
A B x A B y Q

0 0 0 0 0 0
D Q B
0 0 1 0 1 0
CLK
0 1 0 0 0 1 Q

0 1 1 1 1 0 y

1 0 0 0 0 1
1 0 1 1 0 0
A(t+1) = A x + B x
1 1 0 0 0 1
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t t+1 t 46
 Analysis of Clocked Sequential Circuits

 State Table (Transition Table)

x
Present Next State Output D Q A
State x=0 x=1 x=0 x=1
Q
A B A B A B y y
0 0 0 0 0 1 0 0
D Q B
0 1 0 0 1 1 1 0
CLK
1 0 0 0 1 0 1 0 Q

1 1 0 0 1 0 1 0 y

t t+1 t A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
47
 Analysis of Clocked Sequential Circuits

 State Diagram
 The information available in a state table can be represented
graphically in the form of a state diagram.
 In this type of diagram, a state is represented by a circle, and
the (clock-triggered) transitions between states are indicated by
directed lines connecting the circles
AB input/output
 The binary number inside each circle identifies the state of
the flip-flops.
 The directed lines are labeled with two binary numbers
separated by a slash which represents input and output during
the present state.
48
 Analysis of Clocked Sequential Circuits

 State Diagram Present Next State Output

State x=0 x=1 x=0 x=1
A B A B A B y y
AB input/output
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0
1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0
00 10
x
D Q A
0/1
Q
1/0 0/1 1/0
D Q B

CLK Q
01 11
y

1/0 49
 Analysis of Clocked Sequential Circuits

 D Flip-Flops
Example: x D Q A
Present Next
y
Input
State State CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A  x  y
0 1 0 1
0 1 1 0
1 0 0 1 01, 10
1 0 1 0
00, 11 0 1 00, 11
1 1 0 0
1 1 1 1 01, 10
50
 Analysis of Clocked Sequential Circuits

 JK Flip-Flops J Q A

Example: x K Q

Present Next Flip-Flop

I/P J Q B
State State Inputs
A B x A B JA KA JB KB K Q
0 0 0 0 1 0 0 1 0
CLK
0 0 0 0 0 1
0 0 1 JA = B KA = B x’
0 1 0 1 1 1 1 1 0
JB = x’ KB = A  x
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 A(t+1) = JA Q’A + K’A QA
1 0 1 1 0 0 0 0 0 = A’B + AB’ + Ax
1 1 0 0 0 1 1 1 1 B(t+1) = JB Q’B + K’B QB
1 1 1 1 1 1 0 0 0 = B’x’ + ABx + A’Bx’
51
 Analysis of Clocked Sequential Circuits

 JK Flip-Flops J Q A

x K Q
Example:
Present Next Flip-Flop J Q B
I/P
State State Inputs
K Q
A B x A B JA KA JB KB
0 0 0 0 1 0 0 1 0 CLK

0 0 1 0 0 0 0 0 1 1 0 1
0 1 0 1 1 1 1 1 0 00 11
0 1 1 1 0 1 0 0 1
0
1 0 0 1 1 0 0 1 1 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1 0 0 0
1
1 1 1 1 1 1
52
 Analysis of Clocked Sequential Circuits
x A
 T Flip-Flops T Q y

R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0
TA = B x TB = x
0 1 1 1 0 1 1 0
y =AB
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
1 1 0 1 1 0 0 1
1 1
B(t+1) = TB Q’B + T’B QB
1 1 1 0 0 1
=xB 53
 Analysis of Clocked Sequential Circuits
x A
 T Flip-Flops (Counter) T Q y

R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0 0/0 0/0
0 1 1 1 0 1 1 0 00 1/0 01
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0 1/1 1/0
1 1 0 1 1 0 0 1 11 10
1 1
0/1 0/0
1 1 1 0 0 1 1/0
54
 Flip Flop Operating Characteristics

55
 Flip Flop Operating Characteristics


56
 Flip Flop Operating Characteristics


57
 Flip Flop Operating Characteristics
 The Hold Time: is the minimum interval required for
the logic levels to remain on the inputs after the
triggering edge of the clock pulse in order for the
levels to be reliably clocked into the flip-flop.

58
 Flip Flop Operating Characteristics
Set-up Time: is the minimum interval required for the
logic levels to be maintained constantly on the inputs (J
and K, or D) prior to the triggering edge of the clock
pulse in order for the levels to be reliably clocked into
the flip-flop.

59
 Flip Flop Operating Characteristics


60
 Application of Flip-Flops

 Frequency Division
● When a pulse waveform is applied to the clock input of a J-
K flip-flop that is connected to toggle, the Q output is a
square wave with half the frequency of the clock input.

61
Application of Flip-Flops

● The Q output of the second flip-flop is one-fourth the

frequency of the original clock input.
● This is because the frequency of the clock is divided by 2
by the first flip-flop.
● The Q out put of the second flip-flop is the frequency of the
clock divided by 4, or the frequency of Q1 divided by 2.

62
 Application of Flip-Flops

 Parallel Data Storage

● It is common to take several bits of data on parallel lines
and store them simultaneously in a group of flip-flops.

63
 Exercise
 A sequential circuit with two D flip-flops A and B, two inputs, x
and y; and one output z is specified by the following next-state
and output equations

a) Draw the logic diagram of the circuit.

b) List the state table for the sequential circuit.
c) Draw the corresponding state diagram.
Reading Assignment: 1. State Reduction, Implication table &
State assignment
2. Timing Circuits (Bistable, Astable and
Monostable)
3. Asynchronous Preset and Clear Inputs 64