Rajiv Gandhi University of Knowledge Technologies

(Department of Electronics and Communication Engineering)

Assessment Test – 1,2 (A.Y.2019-20)
Year/Sem: E2-SEM1 Date: 24-08-2019
Subject: VLSI Time: 40 Minutes
Subject Code: EC2103 Max. Marks: 20 Marks

Answer the following question. Each question carries one mark. (20 X 1 = 20 M)

1. What is the default value for reg data type

a. 0
b. 1
c. z
d. x
2. -10 % 3 evalutes to
a. -1
b. 1
c. X
d. None
3. If x=41b1100 then x<<2 is
a. 41b1000
b. 41b0000
c. 41b0011
d. 41b0110
4. If A=11b1, B=21b01, C=21b00, Y = {4{A},2{B},C} equals
a. 10100
b. 110100
c. 1111010100
d. 0001011111
5. Which of the following is the highest level of abstraction provided by Verilog HDL
a. Switch level
b. Algorithmic level
 c. Gate level
d. Dataflow level
6. Finite state machines are used for
a. Deterministic test patterns
b. Algorithmic test patterns
c. Random test patterns
d. Pseudo random test patterns
7. Which of the following statements is/are true
a. Mealy modal depends on present states
b. Moore modal depends on present states
c. Mealy modal depends on inputs
d. None of above
8. While converting Moore machine to Mealy Machine the number of states
a. Increases
b. Decreases
c. Can not be determined
d. Remains same
9. The number of possible states in detecting the sequence 11011 with overlap by Mealy
machine is
a. 3
b. 5
c. 4
d. 6
10. If a sequential circuit has 29 states then number of flipflops required to implement that
circuit is
a. 6
b. 7
c. 8
d. 5
11. A clocked Moore sequential circuit has an output Z=1 if the total number of 0’s received
is an even number greater than zero, provided that two consecutive 1’s have been
received. Specify output sequence for the given sequence 00001010110000
a. 110100100100000
 b. 01011001110000
c. 00100011000110
d. None
12. In which of state machines, change in input reflects change in output with one clock cycle
later
a. Mealy
b. Moore
c. Both a and b
d. None
13. Which of following is not bitwise operator
a. !
b. ~
c. &
d. ^
14. 11 % -2 evaluates to
a. -1
b. X
c. +1
d. Z
15. Which of the following represents case equality
a. ===
b. ==
c. =
d. None
16. If we design a sequential circuit with 11 flipflops then maximum possible states are
a. 1026
b. 2048
c. 2024
d. All of above
17. The state transition diagram for the logic circuit shown is

a.

b.

c.

d.
18. The state diagram of a finite state machine (FSM) is designed to detect an overlapping
sequence of three bits is shown in fig. The FSM has an input ‘In’ and an output ‘Out’. The
initial state of the FSM is S0. If the input sequence is 10101101001101, starting with the
left-most bit, then the number times ‘Out’ will be 1 is

a. 4
b. 3
c. 5
d. 6

19. The default value of a Net is

a. 1
b. 0
c. X
d. Z
20. Which of following keyword is used to define constants in module
a. Trireg
b. Integer
c. Parameter
d. Real
KEY:

1. d
2. a
3. b
4. c
5. b
6. b
7. b
8. d
9. b
10. d
11. d
12. b
13. a
14. c
15. a
16. b
17. d
18. a
19. d
20. c