1.

Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 1/129

1. Introduction to the Design

of Analog Integrated Circuits

Francesc Serra Graells

francesc.serra.graells@uab.cat
Departament de Microelectrònica i Sistemes Electrònics
Universitat Autònoma de Barcelona

paco.serra@imb-cnm.csic.es
Integrated Circuits and Systems
IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 2/129

1 CMOS Technologies

2 From the Idea to the Chip

3 Device Modeling for Analog Design

4 The Operational Amplifier and its FoMs

5 Lab Proposal

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 3/129

1 CMOS Technologies

2 From the Idea to the Chip

3 Device Modeling for Analog Design

4 The Operational Amplifier and its FoMs

5 Lab Proposal

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 4/129

1971-2016 data collected from:

Moore's Law
1 oct / 2 year
wikipedia.org/wiki/Transistor_count
Oracle SPARC M7
10G
Xbox One
Number of transistors Intel 61-Core Xeon IBM POWER8
Apple A8
per chip doubles every
Intel 2-Core Intel
Itanium 2 8-Core i7
24 months 1G IBM POWER6 Apple A7
Intel 4-Core i7
AMD K10
1 oct / 1 year Intel Itanium 2 Intel Pentium D

AMD K8
100M

Microprocessor Transistor Count

Intel Pentium 4 Intel Atom
AMD K7 ARM A9
AMD K6 Pentium III
10M
Intel Pentium Pro Pentium II
Intel Pentium AMD K5

Intel 80486
MIPS R4000
1M
TI Explorer ARM 7
Intel 80386 ARM 3
Intel 80286 Intel i960
Motorola 68020 ARM 9
100k
Motorola
68000 Intel 80186
Intel ARM 2 ARM 6
8086 8088 ARM 1
Zilog
http://dx.doi.org/10.1109/N-SSC.2006.4785860 10k Z80 WDC 65C02
Gordon E. Moore, 8085
Cramming More Components onto Integrated Circuits, 8080
Electronics Magazine, 38(8):114–117, Apr 1965 3 dec / 20 years
Intel 4004

1k
1970 1980 1990 2000 2010 2020
Date of Introduction

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 5/129

Technology nodes
Moore's Law
2004 2006 2008 2010
90nm 65nm 45nm 32nm
Number of transistors
per chip doubles every Front-end
24 months of line
(FEOL)
Thanks to scaling, not at
chip (yield!), but at GEN1 GEN2 GEN1 GEN2
transistor (litho) level SiGe-strained High-k
Silicon metal gate

Typ. reticle size

Low-resistance layer

1.2-nm SiO2 dielectric Work-function metal

(5 atomic layers!)
3nm-Hafnium dielectric

25mm 625mm2 Silicon substrate

25mm

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 6/129

Technology nodes
Moore's Law
2004 2006 2008 2010
90nm 65nm 45nm 32nm
Number of transistors
per chip doubles every Front-end
24 months of line
(FEOL)
Thanks to scaling, not at
chip (yield!), but at GEN1 GEN2 GEN1 GEN2
transistor (litho) level SiGe-strained High-k
Silicon metal gate

Typ. reticle size

Low-resistance layer

1.2-nm SiO2 dielectric Work-function metal

(5 atomic layers!)
3nm-Hafnium dielectric

25mm 625mm2 Silicon substrate

25mm
Back-end
of line
(BEOL)
intel.com
7M, Al 9M, low-k, Cu

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 7/129

Technology nodes
More Moore
2012 2014 2017 2019
22nm 14nm 10nm 7nm
Number of transistors
per chip doubles every
24 months ???

Thanks to scaling, not at

chip (yield!), but at GEN1 GEN2 - Triple patterning?
transistor (litho) level TriGate/FinFET - FDSOI?
and double patterning - EUV lithography?
- Gate-all-around/nanowire?
Metal Gate Metal Gate

Fin optimization

Si Substrate Si Substrate

- Air gaps?
intel.com
>10M, ultra low-k

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 8/129

More Moore
intel.com

Number of transistors
per chip doubles every
24 months

Thanks to scaling, not at

chip (yield!), but at
transistor (litho) level

Cut-off frequency increases,

but not exploited due to RF and wavelength
power limitations → parallelism

isscc.org itrs.net

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 9/129

More Moore
18"
450mm
Number of transistors
12"
per chip doubles every 300mm
24 months 8"
6" 200mm
4" 150mm
Thanks to scaling, not at 2"
100mm

chip (yield!), but at 50mm

1970 1975 1980 1991 2001 2020?
transistor (litho) level

Cut-off frequency increases,

8"
but not exploited due to RF and
power limitations → parallelism wafer
diameter
Cost/transistor
improved also due to 12"
wafer scaling (capacity)

intel.com

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 10/129

More Moore
Number of transistors
per chip doubles every
24 months

Thanks to scaling, not at

chip (yield!), but at
transistor (litho) level

Cut-off frequency increases,

but not exploited due to RF and
power limitations → parallelism

Cost/transistor
improved also due to
wafer scaling (capacity)

Small is beautiful, but what to do Oracle SPARC 4.1-GHz 32-core M7 processor in

with so many, inexpensive and 13-metal 20-nm FinFET TSMC technology
super fast devices? featuring 10-billion transistors

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 11/129

More than Moore

Diversification of
technology applications
Society trends

Ubiquitous computing Personal health Driver

Biosensors
Health monitoring monitoring

Not only signal Transport Smart

key Telematics
Autom. fare
collection
processing but:
Power Ultra low Hybrid electric Smart
Smart sensing Energy efficiency power driving metering

Wireless communications
Smart sensor Motor management
Power control Security tags Crash free
E-blister E-gov

Wireless Ultra low

Communication connectivity power
Multi-domain
integrated systems: Infotainment
Wideband
tuning
Connected
car
Physics
Chemistry
ng

n
e
er

l
l

ca
ia
Markets

iv
io

io
si

um

tr
Biology

ot
at

at
i
es

ed
us
om
ic

ic
s
oc

M
on

d
un

tif
In
ut
Pr

en
Medicine
C
m

A
om

Id
a
at
D

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 12/129

More than Moore

Diversification of
technology applications

Ubiquitous computing

Not only signal

processing but:
Smart sensing
Wireless communications
Power control

Multi-domain
integrated systems:
Physics New challenges (beside miniaturization):
Chemistry CMOS technologies with extra process modules
Biology Advanced mixed-signal circuit design (A/D/RF/MEMS/power...)
Medicine
Application-specific packaging

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 13/129

Silicon Wafer
Polished monocrystalline slice

Periodic atomic lattice Flat side

CMOS technologies Bipolar technologies

p n
{100} {100}
Doping type
<110>
Crystalline plane
p n
{111} {111}

~5Å lattice spacing

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 14/129

Silicon Wafer
Polished monocrystalline slice

Periodic atomic lattice Flat side

wikipedia.org
Obtained from cylindrical ingots

Melting of Introduction Beginning of Crystal Formed crystal

polysilicon of the seed the crystal pulling at (1m to 2m)
at 1425oC crystal growth 25mm/h with a residue
(99.9999999% purity) of melted silicon
Czochralski method

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 15/129

Silicon Wafer
Polished monocrystalline slice

Periodic atomic lattice Flat side

Obtained from cylindrical ingots

200-µm to 750-µm thicknesss
Grinding, slicing and polishing Bulk, epitaxial, Silicon-on-insulator (SOI)

Diameter grinding Flat grinding Wafer slicing

Slurry Head

Edge rounding Two-side lapping Chemical etching Surface polishing

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 16/129

Wafer Processing idesa-training.org

Patterning areas
Resist
using photolithography Resist coat
Substrate

Mask
Exposure

Positive tone Negative tone

Develop

Processing (e.g. etching)

Resist strip

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 17/129

Wafer Processing idesa-training.org

Patterning areas
using photolithography UV Light/Laser

Resist Mask

1. Vapor prime 2. Spin coat 3. Soft bake 4. Alignment

and exposure

5. Post-expsure bake 6. Develop 7. Hard bake 8. Inspection

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 18/129

Wafer Processing
Patterning areas
using photolithography Slit

Light source

Lenses

Mask 5:1 shrinking

Wafer
10µm
Photoresist
Contact Proximity Scanning projection

Simple equipment No direct contact High resolution

Limited mask lifetime Resolution >3µm Expensive and slower

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 19/129

Wafer Processing
Patterning areas
Light Source
using photolithography Reference Mark

Stepper equipment
Alignment Laser
Reticle Stage
Reticle

Interferometer
Laser Projection Lens

X
Interferometer
Mirror Set
Wafer
Wafer Stage

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 20/129

Wafer Processing
Patterning areas
using photolithography

Name Wavelength (nm) Application feature

Light source
size (µm)
G-line 436 0.50
Mercury Lamp H-line 405
I-line 365 0.35 to 0.25
XeF 351
XeCl 308
Excimer Laser KrF (DUV) 248 0.25 to 0.15
ArF 193 0.18 to 0.13
Fluorine Laser F2 157 0.13 to 0.1

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 21/129

Wafer Processing Channeling

Patterning areas
using photolithography

Adding materials:
Ion implantation

Depth control
Density

Density

Density
Lattice damage
Depth Depth Depth

Lateral effect Shadowing

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 22/129

Wafer Processing
Patterning areas Doping applications
using photolithography

Adding materials:
Ion implantation

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 23/129

Wafer Processing e.g. Si doping (hours, 800oC to 1200oC)

Patterning areas
using photolithography

Adding materials: Diffusion profile

Ion implantation
Diffusion 10

Thin-film growing
Thin-film deposition
ry
o Cd
00
1,2 o d r y
1.0 C
00
e.g. SiO2 oxidation (hours, 700oC to 1200oC)

O xide thickness ( m)
1
1 o dry
,
et C
Cw o
, 0 00
00 t 1 y
1,2 o C we o C
dr
Q uartz tube 00 t 90
0
1,1 o we
C
00
Si wafers 1,0
0.1

et
w
Flow o C
0 (100)
controller 90

R esistance-heated furnace 0.01

O 2 N2 H 2O 0.1 1.0 10 100
O xidation time (h)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 24/129

Wafer Processing
Patterning areas
using photolithography

Adding materials: Material selectivity

Ion implantation Undercut
Diffusion
Thin-film growing
Photoresist
Thin-film deposition Film
Substrate
Removing materials:
Cleaning Anisotropic Isotropic
(dry etching) (wet chemical etching)
Etching

e.g. physical/chemical
reactive ion etching (RIE)
for micromachining

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 25/129

Wafer Processing Slurry Dispenser

Pressure
Membrane
Patterning areas Wafer Holder
using photolithography
Wafer
Retaining Ring Slurry

Adding materials:
Polishing Pad
Ion implantation
Platen
Diffusion
Thin-film growing
Thin-film deposition

Removing materials:
Cleaning
Etching
Chemical-mechanical
planarization (CMP)

Thermal treatment:
Annealing
Reflowing
Alloying e.g. 6-metal 0.18µm BEOL

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 26/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design

FEOL stages: Starting wafer

General cleaning
N and P wells
Si

Initial pad oxidation (314Å to 415Å)

Photoresist
Nitride deposition (1050Å to 1300Å)
NTUB photolithography

Si
SiO2

Si3N4

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 27/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
Initial pad oxidation (314Å to 415Å)
Photoresist
FEOL stages: Nitride deposition (1050Å to 1300Å)
NTUB photolithography
N and P wells
Si
SiO2

Si3N4

P P P P P P P
Nitride etching
N-well implantation

Si
SiO2

Si3N4

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 28/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design

P P P P P P P
FEOL stages: Nitride etching
N-well implantation
N and P wells

Si
SiO2

Si3N4

Well-oxide grow (3500Å to 4500Å)

B B B B B B B
P B
P B
P
Nitride stripping
P-well implantation

Si
SiO2

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 29/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
Well-oxide grow (3500Å to 4500Å)
FEOL stages:
B B B B B B B
P B
P B
P
Nitride stripping
P-well implantation
N and P wells

Si
SiO2

Oxide stripping
P-well (7µm) N-well (5µm) drive-in
and oxide grow (1500Å to 1750Å)
Oxide stripping

P-well
Si N-well

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 30/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
Oxide stripping
P-well (7µm) N-well (5µm) drive-in
FEOL stages: and oxide grow (1500Å to 1750Å)
N and P wells Oxide stripping
Active areas P-well
Si N-well

Pad oxidation (150Å to 225Å)

Nitride deposition (1050Å to 1300Å)
GASAD photolithography

P-well
Si N-well
SiO2

Si3N4

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 31/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
Pad oxidation (150Å to 225Å)
Nitride deposition (1050Å to 1300Å)
FEOL stages: GASAD photolithography
N and P wells
Active areas P-well
Si N-well
SiO2

Si3N4

B B B B B B B
P B
P B
P B B

Nitride etching
Field implantation

P-well
Si N-well
SiO2

Si3N4

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 32/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
B B B B B B B
P B
P B
P B B

FEOL stages: Nitride etching

Field implantation
N and P wells
Active areas P-well
N-well
Si
SiO2

Si3N4

LOCOS* (10000Å to 11200Å)

Nitride etching

P-well
Si N-well
SiO2

*
LOCal Oxidation of Silicon M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 33/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design

FEOL stages: LOCOS* (10000Å to 11200Å)

Nitride etching
N and P wells
Active areas P-well
Si N-well
SiO2

Sacrifitial oxidation (850Å to 1050Å)

Gate implantation B B PB B B B
P
Pre-poly cleaning

P-well
Si N-well
SiO2

*
LOCal Oxidation of Silicon M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 34/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
Sacrifitial oxidation (850Å to 1050Å)
FEOL stages: Gate implantation B B PB B B B
P
Pre-poly cleaning
N and P wells
Active areas
PiP capacitor P-well
Si N-well
SiO2

POCl3 POCl3 POCl3 POCl3 POCl3 POCl3 POCl3 POCl3

PolySi deposition
(3200Å to 3800Å)
P-well
N-type doping
Si N-well
SiO2

PolySi
M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 35/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
POCl3 POCl3 POCl3 POCl3 POCl3 POCl3 POCl3 POCl3
FEOL stages:
N and P wells PolySi deposition
(3200Å to 3800Å)
Active areas N-type doping
P-well
PiP capacitor Si N-well
SiO2

PolySi

POLY0 photolithography

P-well
Si N-well
SiO2

PolySi

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 36/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design

POLY0 photolithography
FEOL stages:
N and P wells
P-well
Active areas Si N-well
SiO2
PiP capacitor
PolySi

PolySi etching
Sacrifitial oxide stripping

P-well
Si N-well
SiO2

PolySi

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 37/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
PolySi etching
FEOL stages: Sacrifitial oxide stripping
N and P wells
P-well
Active areas Si N-well
SiO2
PiP capacitor
PolySi
MOS gate

Gate-oxide growing (340Å to 390Å)

P-well
Si N-well
SiO2

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 38/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design

Gate-oxide growing (340Å to 390Å)

FEOL stages:
N and P wells
P-well
Active areas Si N-well
SiO2
PiP capacitor
MOS gate

PolySi deposition (4500Å to 5100Å)

POLY1 photolithography

P-well
Si N-well
SiO2

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 39/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
PolySi deposition (4500Å to 5100Å)
POLY1 photolithography
FEOL stages:
N and P wells
P-well
Active areas Si N-well
SiO2
PiP capacitor
MOS gate

PolySi etching

P-well
Si N-well
SiO2

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 40/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design

PolySi etching
FEOL stages:
N and P wells
P-well
Active areas Si N-well
SiO2
PiP capacitor
MOS gate
MOS source and drain P P P NPLUS photolithography
N-type doping

P-well
Si N-well
SiO2

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 41/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
P P P NPLUS photolithography
FEOL stages: N-type doping

N and P wells
Active areas P-well
N-well
Si
PiP capacitor SiO2

MOS gate
MOS source and drain
B B B
P
B B B
P
P-type doping

P-well
Si N-well
SiO2

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 42/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
B B B
P
B B B
P
FEOL stages: P-type doping

N and P wells
Active areas Si
P-well
N-well
PiP capacitor SiO2

MOS gate
MOS source and drain TEOS* deposition (12000Å to 13000Å)
N++(1µm) and P++(3µm) D/S diffusion
BEOL stages:
Interlevel oxide
P-well
Si N-well
SiO2

*
TEtraethyl OrthoSilicate M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 43/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
TEOS* deposition (12000Å to 13000Å)
N++(1µm) and P++(3µm) D/S diffusion
FEOL stages:
N and P wells
Active areas P-well
N-well
Si
PiP capacitor SiO2

MOS gate
MOS source and drain
WINDOW photolithography

BEOL stages:
Interlevel oxide
P-well
Contacts Si N-well
SiO2

*
TEtraethyl OrthoSilicate M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 44/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
WINDOW photolithography

FEOL stages:
N and P wells
Active areas Si
P-well
N-well

PiP capacitor SiO2

MOS gate
MOS source and drain Al metalization
METAL photolithography

BEOL stages: Al

Interlevel oxide
Contacts Si
P-well
N-well

Metal SiO2

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 45/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
Al metalization
METAL photolithography
FEOL stages: Al
N and P wells
Active areas P-well
Si N-well
PiP capacitor SiO2

MOS gate
MOS source and drain
Al etching
Al
BEOL stages:
Interlevel oxide
P-well
Contacts Si N-well
SiO2
Metal

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 46/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
Al etching
Al
FEOL stages:
N and P wells
P-well
N-well
Active areas Si
SiO2
PiP capacitor
MOS gate
Oxidation (4000Å)
MOS source and drain Nitride deposition (4000Å)
CAPS photolithography
BEOL stages:
Al Si3N4
Interlevel oxide
Contacts SiO2

Metal Si
P-well
N-well

Passivation and pads

M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 47/129

CNM25 Technology Example

2.5-µm polySi-insulator-polySi (PiP) 1M twin-well CMOS process:
4-inch wafers
22-mm x 22-mm (484mm2) stepper reticle
Wafer processing steps:
8-mask layout design
Oxidation (4000Å)
Nitride deposition (4000Å)
FEOL stages: CAPS photolithography
N and P wells
Al Si3N4
Active areas
PiP capacitor SiO2
P-well
MOS gate Si N-well

MOS source and drain

Wire-bonding pad Nitride etching
BEOL stages: Oxide etching

Interlevel oxide
Contacts
Metal
Passivation and pads
M. Zabala and A. Sánchez, IMB-CNM(CSIC)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 48/129

Modern Technologies
Poly gate Salicide Spacer
Advanced MOSFET
device structure D/S extension
Gate dielectric

Salicide

Heavily doped D/S Halo

Channel & well profiles

idesa-training.org

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 49/129

Modern Technologies
idesa-training.org

Advanced MOSFET
device structure
Local Oxidation
Device isolation of Silicon
LOCOS Bird's beak
Shallow Trench
Isolation
STI

Pad oxide growth + nitride deposition Pattern and etch Si3N4 and SiO2 Trench etch into Si
Si3N4 Si33NN44
Si Si3N4
SiO2 depth
= ~ 350 nm;
SiO2 SiO2 SiO2 “shallow”
Si Si Si

Deposition of trench filling oxide

(No thermal growth!)
SiO2 Oxide CMP polish step with stop on nitride Field oxide recess (HF dip)
Si3N4 Si3N4 Removal of nitride layer (H3PO4)

SiO2 SiO2 SiO2

Si Si Si

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 50/129

Modern Technologies
Advanced MOSFET
device structure Classical Al metallisation Damascene Cu metallisation
Device isolation 1) metal deposition 1) etching of oxide trenches
oxide
Cu interconnections metal
Lower resistivity oxide
Higher melting point
Lower thermal 2) etching of metal lines 2) metal deposition
expansion
metal
Lower electromigration

3) oxide gapfill + oxide CMP

oxide 3) metal CMP

idesa-training.org

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 51/129

Mixed-Signal Technology Modules

CMOS process options for each IC application:

Twin vs triple well

shallow trench S G D D G S B B S G D D G S B
isolation (STI) B

n- n- p- p- n- n- p- p-
P+ N+ N+ P+ P+ N+ P+ N+ N+ P+ P+ N+

P-well N-well P-well N-well

Deep N-well
P-sub

Gate-bootstrapping in SC circuits
(e.g. input samplers, charge pumps)

Isolation against substrate noise (half circuit)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 52/129

Mixed-Signal Technology Modules

CMOS process options for each IC application:

Twin vs triple well
Several MOSFET threshold-voltage families

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 53/129

Mixed-Signal Technology Modules

CMOS process options for each IC application:

Twin vs triple well
Several MOSFET threshold-voltage families
Metal-insulator-metal (MiM) and fringe linear capacitors
High-resistance polySi (HIPO) linear and low-TC resistors
Thick top metal for high-Q RF inductors

Differential
inductor

Triple MIM 4M fringe

capacitor capacitor

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 54/129

Mixed-Signal Technology Modules

CMOS process options for each IC application:

Twin vs triple well
Several MOSFET threshold-voltage families
Metal-insulator-metal (MiM) and fringe linear capacitors Anti-reflective
coating (ARC)
High-resistance polySi (HIPO) linear and low-TC resistors
Thick top metal for high-Q RF inductors

Linear varactors for continuous RF tuning P+ N+ P+

High-voltage (HV) and LDMOS transistors for power management P- N- P-

Lateral and vertical bipolar transistors for bandgap references P-sub

Anti-reflective coating and optimum doping profiles for CMOS image sensors (CIS)
Non-volatile memory (NVM) for chip ID, configuration, tunning...

Many modules = higher mask/process costs + difficult circuit design migration

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 55/129

Hybrid-Packaging Alternatives

Classic wire-bonding approach:

Sensor CMOS

Package/PCB

Monolithic solution (signal integrity, production)

Sensor needs to be CMOS compatible
Area costs
Wire-bonding costs for large arrays

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 56/129

Hybrid-Packaging Alternatives

Classic wire-bonding approach: Bump-bonding flip-chip:

Sensor CMOS

Package/PCB

Monolithic solution (signal integrity, production) Heterogeneous sensor/CMOS technologies

Sensor needs to be CMOS compatible Sensor area can be reused for circuits
Area costs Back-side sensing
Wire-bonding costs for large arrays Wire-bonding costs for large arrays

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 57/129

Hybrid-Packaging Alternatives

3D stacking with through-Silicon vias (TSV):

Sensor
CMOS side

Deep
Standard reactive-ion
wafer etching
thickness (DRIE) CMOS

Redistribution
layers (RDL) side
Package/PCB

Height/diameter < 20 Heterogeneous sensor/CMOS technologies

Typ. diameter 50μm to 100μm Sensor area can be reused for circuits
pF-range parasitic capacitance Front-side sensing
< 1-Ω series resistance Wire-bonding free

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 58/129

Hybrid-Packaging Alternatives

3D stacking with through-Silicon vias (TSV):

TSV downscaling by wafer

chemical-mechanical polishing (CMP):

CMOS side

Deep
Standard reactive-ion
wafer etching
thickness (DRIE)

Redistribution
layers (RDL) side

Height/diameter < 20
Typ. diameter 50μm to 100μm
pF-range parasitic capacitance
imec.be
< 1-Ω series resistance

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 59/129

1 CMOS Technologies

2 From the Idea to the Chip

3 Device Modeling for Analog Design

4 The Operational Amplifier and its FoMs

5 Lab Proposal

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 60/129

vs
IC Design Scenario
modeling - - exhaustive
cause/effect - - high speed
Synthesis vs analysis: simplification - - high precision
multi-disciplinar - - large database
Schematics Layout
Specifications
IR mVpp
CM R Upper >4 V
Lower <1
OR >3 Vpp
Vof f ±σ <10 mVrms
Pd Vin = 2.5V <1.5 mW
GD C >60 dB
CM RR D C >50 dB
+ dB

Synthesis Synthesis
P SRR D C >50
− >50
SR + >1.5 V/ µs
− >1.5
ts(1%) Vout = 2 → 3V <1500 ns
Vout = 3 → 2V <1500
f max Vout = OR KHz
TH D Vout = OR/ 2@10KHz <1 %
BW −3dB Hz
GB W >1 MHz
φm >50 deg
Vnieq 100Hz to 10MHz <1 mVrms
Area <0.025 mm2

Circuit Physical

Analysis Analysis

EDA tools do not design ICs!

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 61/129

Analog vs Digital

If it can be done by digital, don't use analog!

Analog IC design is complex...

Background in physics, electronics,
information and control theory,
signal processing, communications
Variety of state-of-the-art solutions
What is
High dependence from technology this?
Modeling skills
Complex EDA tools
Digital Analog
way way

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 62/129

Analog vs Digital Transdu

cer
s

If it can be done by digital, don't use analog! ADC

DAC AGC
Analog IC design is complex...
Preamp
Background in physics, electronics, μC Filter
information and control theory, μP
signal processing, communications Power DSP
FPGA LNA
manager
Variety of state-of-the-art solutions Memory

ply

Com
High dependence from technology Mixer

Sup
Reference

m
Modeling skills

u
PA

nic
Complex EDA tools PLL

a
VCO

tio
ns
...but still necessary!

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 63/129

Analog vs Digital Transdu

cer
s

If it can be done by digital, don't use analog! ADC

DAC AGC
Analog IC design is complex...
Preamp
Background in physics, electronics, μC Filter
information and control theory, μP
signal processing, communications Power DSP
FPGA LNA
manager
Variety of state-of-the-art solutions Memory

ply

Com
High dependence from technology Mixer

Sup
Reference

m
Modeling skills

u
PA

nic
Complex EDA tools PLL

a
VCO

tio
ns
...but still necessary! Temperature RF
sensing frontend

Touch Imager
screen Battery
Most modern ICs are manager
really mixed-signal Audio Magnetometer
input/output
Light sensing
Accelerometer

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 64/129

IC vs PCB
What can analog IC design offer compared to PCB?

Good Bad

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 65/129

IC vs PCB
What can analog IC design offer compared to PCB?

Good Bad

Small size and high density

Complex systems

High speed operation

Low power consumption

Heterogeneous SoC
(A/D/RF/MEMS/Power)

Low production costs

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 66/129

IC vs PCB
What can analog IC design offer compared to PCB?

Good Bad

Small size and high density Low observability/controllability

Complex systems Few device primitives

High speed operation Technology variability

(process and mismatching)
Low power consumption Complex modeling
Heterogeneous SoC High design costs
(A/D/RF/MEMS/Power) (EDA/personnel)

Low production costs High prototyping costs

Long design cycles

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 67/129

IC Flavors
cnm25modn( w=28,
l=6,
mx=4,
my=2,
common_d=False,
Each application may require a different IC solution: common_g=False,
common_s=True)

Full-custom
Density
Flexibility
Performance
Design time
EDA tools
Prototype costs
Target volume High
Mixed-mode A and D

Hand-drawn geometry
All layers customized
Application-specific IC
(ASIC) result

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 68/129

IC Flavors
Each application may require a different IC solution:
Full-custom Macro-cell
Density
Flexibility
Performance
Design time
EDA tools
Prototype costs
Target volume High High
Mixed-mode A and D A and D

Predefined macro blocks (ADC, memory...)

Automated routing
Magali 65-nm SoC for 4G communication with 22 IPs
All layers customized
Still an ASIC

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 69/129

IC Flavors
Each application may require a different IC solution:
Full-custom Macro-cell Standard-cell
Density
Flexibility
Performance
Row of cells
Design time
EDA tools
Prototype costs I/O
pad ring
Target volume High High High
Mixed-mode A and D A and D D

Gate level cells + automated routing

Regular floorplan
All layers customized
Still an ASIC Routing

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 70/129

IC Flavors
Each application may require a different IC solution:
Full-custom Macro-cell Standard-cell Gate-array
Density
Flexibility
Performance
Design time
EDA tools
Prototype costs
Target volume High High High Medium
Mixed-mode A and D A and D D D

Pre-built transistors/gates/IPs
Only routing layers customized
Structured ASIC

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 71/129

IC Flavors
Each application may require a different IC solution:
Full-custom Macro-cell Standard-cell Gate-array FPGA
Density
Flexibility
Performance
Design time
EDA tools
Prototype costs
Target volume High High High Medium Low
Mixed-mode A and D A and D D D D (A)

Programmable logic blocks

Programmable routing
Not an ASIC
Altera
Cyclone III

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 72/129

IC Flavors
Each application may require a different IC solution:
Full-custom Macro-cell Standard-cell Gate-array FPGA
Density
Flexibility
Performance
Design time
EDA tools
Prototype costs
Target volume High High High Medium Low
Mixed-mode A and D A and D D D D (A)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 73/129

Full-Custom Design
Fixed CMOS technology:
Materials and processes p+ n+ n+
p+ p+ n+

Vertical dimensions
p-well n-well

Analog design space:

Circuit topology non-linear!
Device horizontal sizing
Device biasing

Width
Length
Multiplicity

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 74/129

Full-Custom Design
Fixed CMOS technology:
Materials and processes p+ n+ n+
p+ p+ n+

Vertical dimensions
p-well n-well

Analog design space:

Circuit topology
Device horizontal sizing
Device biasing

other device cases:

Number of turns
Inner Diameter
Spacing
Width

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 75/129

Power consumption (lifetime, range...)

Full-Custom Design Silicon area (costs, packaging...)

Fixed CMOS technology:

Resources
ce
Materials and processes Performan
Vertical dimensions

Analog design space:

Circuit topology
Device horizontal sizing
Device biasing Figure of Merit (FoM)
1 E+07

Analog IC design 1 E+06

optimization rules 1 E+05

1 E+04
P/fsnyq [pJ]

1 E+03
e.g. ADC circuits 1 E+02
ISSCC 2013
1 E+01 VLSI 2013
ISSCC 1997-2012
VLSI 1997-2012
1 E+00 FOMW=10fJ/conv-step
FOMS=170dB
B. Murmann, ADC Performance Survey 1 E-01
http://www.stanford.edu/~murmann/adcsurvey.html 10 20 30 40 50 60 70 80 90 100 110 120
SNDR @ fin,hf [dB]

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 76/129

System Complexity
Analog IC designers deal with several hierarchy and abstraction levels

e.g. electrochemical
smart sensor

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 77/129

System Complexity
Analog IC designers deal with several hierarchy and abstraction levels

Top
down
Systems

switch (action) {
case SAMPLING: /* Sampling action */
OUTPUT_CHANGED(out) = FALSE;
*inp_mem = inp;
break;
case QUANTIZATION: /* Quantization action */
OUTPUT_CHANGED(out) = TRUE;
if (*inp_mem>inp_th) {
out = ONE;
OUTPUT_DELAY(out) = t_rise;
} else {

}
out = ZERO;
OUTPUT_DELAY(out) = t_fall; Circuits
OUTPUT_STATE(out) = out;
OUTPUT_STRENGTH(out) = STRONG;
*out_mem = out;
break;
case HOLDING: /* Holding action */
OUTPUT_CHANGED(out) = FALSE;
}

Devices
Bottom
up

Functional Electrical Physical

(Verilog/VHDL/SystemC-AMS, XSpice, Simulink) (SPICE) (FE simulators)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 78/129

System Complexity
Analog IC designers deal with several hierarchy and abstraction levels

Mixing different abstraction levels during design

Simulation speed up
switch (action) {
case SAMPLING: /* Sampling action */
OUTPUT_CHANGED(out) = FALSE;
*inp_mem = inp;
break;

Study of circuit
case QUANTIZATION: /* Quantization action */
OUTPUT_CHANGED(out) = TRUE;
if (*inp_mem>inp_th) {

non-ideal effects
out = ONE;
OUTPUT_DELAY(out) = t_rise;
} else {
out = ZERO;

Multi-level and multi-domain

OUTPUT_DELAY(out) = t_fall;
}
OUTPUT_STATE(out) = out;

simulation needed (single

OUTPUT_STRENGTH(out) = STRONG;
*out_mem = out;
break;

engine or glue approach)

case HOLDING: /* Holding action */
OUTPUT_CHANGED(out) = FALSE;
}

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 79/129

ASIC Development
Typical project scheduling: Custom library
test chips

M0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Specs Design Integration Testing Complete

system-on-chip (SoC)

Alignment with foundry fixed run calendar

Long design iterations (typ. 6M)

First complete prototype >18M

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 80/129

CMOS Technology Costs

Full-mask regular run 1 layer/mask

36-mask set

layer

25mm
depending on #1
process modules!

25mm Stepper
reticle
e.g. 0.15-μm 1P6M CMOS technology
Wafer map
Die size: < 625 mm2 ∅ 200mm

Mask costs: 100 k€

Processing costs: 2 k€/wafer
Samples: > 50 die/wafer
Intended for full production (> 200 wafer/year)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 81/129

CMOS Technology Costs

Full-mask regular run 1 layer/mask

36-mask set
Multi-project wafer (MPW) run
design
#1

25mm
design
#N

25mm Stepper
reticle
e.g. 0.15-μm 1P6M CMOS technology
Wafer map
Die size: > 4 mm2 ∅ 200mm

Mask and processing costs: 1 k€/mm2

Samples: < 100 die
Intended for prototyping

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 82/129

CMOS Technology Costs

4-MLM
Full-mask regular run 4 layer/mask
9-mask set
Multi-project wafer (MPW) run
Multi-layer mask (MLM) engineering run layer
#1 #2

12.5mm
#3 #4

12.5mm Stepper
reticle
e.g. 0.15-μm 1P6M CMOS technology
Wafer map
Die size: < 156 mm2 ∅ 200mm

Mask costs: 25 k€
Processing costs: 2 k€/wafer (6-wafer lots)
Samples: > 200 die/wafer
Intended for small series (< 100 wafer/year)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 83/129

CMOS Technology Costs

9-MLM
Full-mask regular run 9 layer/mask
4-mask set
Multi-project wafer (MPW) run
layer
Multi-layer mask (MLM) engineering run #1 #2 #3

#4 #5 #6

8.3mm
#7 #8 #9

8.3mm Stepper
reticle
e.g. 0.15-μm 1P6M CMOS technology
Wafer map
Die size: < 69 mm2 ∅ 200mm

Mask costs: 12 k€
Processing costs: 2 k€/wafer (6-wafer lots)
Samples: > 450 die/wafer
Intended for small series (< 100 wafer/year)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 84/129

CMOS Technology Costs

Full-mask regular run 1 layer/mask

36-mask set
Multi-project wafer (MPW) run
#1 block #2 #3
Multi-layer mask (MLM) engineering run

25mm
Wafer-scale stitching run #4 #5 #6

#7 #8 #9
25mm Stepper
reticle
e.g. 0.15-μm 1P6M CMOS technology
Wafer map
Die size: 150x150 mm2 ∅ 200mm

Mask costs: 100 k€

single
Processing costs: 2 k€/wafer chip
imagesensors.org
Samples: 1 die/wafer
Intended for limited series
Low yield (acceptable for imagers)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 85/129

1 CMOS Technologies

2 From the Idea to the Chip

3 Device Modeling for Analog Design

4 The Operational Amplifier and its FoMs

5 Lab Proposal

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 86/129

Bulk Enhancement MOSFET

Intrinsic and extrinsic model parts

B S G D

p+ n+ n+

p-well

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 87/129

Analytical (physical) vs
Bulk Enhancement MOSFET numerical (fitting) modeling
Intrinsic and extrinsic model parts
.MODEL MY_NMOS BSIM3V3 TYPE=N
+ VERSION=3.2 PARAMCHK=1
+ NSUB=2.161E+19 NCH=1.280E+17 XJ=1.500E-07 LINT=7.639E-04
+ WINT=3.669E-04 LL=0 LLN=0 LW=0 LWN=0 LWL=0 WL=-1.253E-10
+ WLN=1 WW=-2.595E-07 WWN=4.475E-01 WWL=0 DWG=0 DWB=0
+ TOX=3.800E-08 TOXM=3.800E-08 XT=1.000E-07 RDSW=3.580E+02
+ PRWB=6.678E-03 PRWG=4.740E-04 WR=4.148E-01
+ VTH0=7.874E-01 K1=1.233E+03 K2=-6.791E-02 K3=8.227E+03
+ K3B=-5.071E-01 W0=2.500E-06 NLX=0 DVT0=5.820E+00 DVT1=5.168E-01
+ DVT2=-2.594E-01 DVT0W=0 DVT1W=5.300E+06 DVT2W=-3.200E-02
+ A0=8.010E-01 B0=0 B1=0 A1=0 A2=1 AGS=1.006E-01 KETA=-1.385E-02
+ MOBMOD=1 U0=6.020E+02 VSAT=1.746E+08
+ UA=9.395E-07 UB=2.828E-15 UC=5.191E-08
+ DROUT=5.600E-01 PCLM=3.178E+03 PDIBLC1=4.811E+03
+ PDIBLC2=8.600E-03 PDIBLCB=0 PSCBE1=4.240E+08
+ PSCBE2=1.000E-05 PVAG=0 DELTA=1.000E-02
+ CDSC=2.953E-02 CDSCB=7.380E-03 CDSCD=-2.864E-03
+ NFACTOR=6.727E-01 CIT=0 VOFF=-6.277E-02

S
+ DSUB=5.600E-01 ETA0=0 ETAB=-1.653E-01
B G D + CAPMOD=3 DWC=3.669E-04 DLC=0 CLC=1.000E-07
+ CLE=6.000E-01 CF=0 ELM=2 ACDE=1 MOIN=15
+ NOFF=1 VOFFCV=0 XPART=6.000E-01 LLC=0
+ LWC=0 LWLC=0 WLC=-1.253E-10 WWC=-2.595E-07 WWLC=0
+ ALPHA0=2.725E-03 ALPHA1=-7.804E-01 BETA0=3.180E+01
+ JS=1.000E-04 JSW=0 NJ=1 IJTH=1.000E-01
+ CJ=5.000E-04 MJ=5.000E-01 PB=1
+ CJSW=5.000E-10 MJSW=3.300E-01 PBSW=1
p+ n+ n+ + CJSWG=5.000E-10 MJSWG=3.300E-01 PBSWG=1
+ CGSO=0 CGDO=0 CGBO=0 CGSL=0 CGDL=0 CKAPPA=6.000E-01
+ TNOM=27 KT1=-1.100E-01 KT1L=0 KT2=2.200E-02 AT=3.300E+04
+ UA1=4.310E-09 UB1=-7.610E-18 UC1=-5.600E-11 PRT=0 UTE=-1.5
p-well + XTI=3 TPB=0 TPBSW=0 TPBSWG=0 TCJ=0 TCJSW=0 TCJSWG=0
+ NOIMOD=1 KF=1.000E-17 AF=1.5 EF=1.5 NOIA=2.000E+29
+ NOIB=2.000E+29 NOIC=2.000E+29 EM=4.100E+07
+ XL=0 XW=0 PK1=1.711E-01 PK2=-6.688E-02
+ PUA=6.246E-04 PUB=-3.418E-12 LUC=1.519E-05
+ PUC=-5.063E-05 PAGS=2.532E-01 PRDSW=-1.071E+04
+ WVSAT=0 PVSAT=-1.800E+05 PVTH0=-1.644E-01

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 88/129

Analytical (physical) vs
Bulk Enhancement MOSFET numerical (fitting) modeling
Intrinsic and extrinsic model parts
.MODEL MY_NMOS BSIM3V3 TYPE=N
+ VERSION=3.2 PARAMCHK=1
+ NSUB=2.161E+19 NCH=1.280E+17 XJ=1.500E-07 LINT=7.639E-04
+ WINT=3.669E-04 LL=0 LLN=0 LW=0 LWN=0 LWL=0 WL=-1.253E-10
Process + WLN=1 WW=-2.595E-07 WWN=4.475E-01 WWL=0 DWG=0 DWB=0
+ TOX=3.800E-08 TOXM=3.800E-08 XT=1.000E-07 RDSW=3.580E+02
+ PRWB=6.678E-03 PRWG=4.740E-04 WR=4.148E-01
+ VTH0=7.874E-01 K1=1.233E+03 K2=-6.791E-02 K3=8.227E+03
Threshold + K3B=-5.071E-01 W0=2.500E-06 NLX=0 DVT0=5.820E+00 DVT1=5.168E-01
voltage + DVT2=-2.594E-01 DVT0W=0 DVT1W=5.300E+06 DVT2W=-3.200E-02
+ A0=8.010E-01 B0=0 B1=0 A1=0 A2=1 AGS=1.006E-01 KETA=-1.385E-02
+ MOBMOD=1 U0=6.020E+02 VSAT=1.746E+08
Mobility + UA=9.395E-07 UB=2.828E-15 UC=5.191E-08
+ DROUT=5.600E-01 PCLM=3.178E+03 PDIBLC1=4.811E+03
Output + PDIBLC2=8.600E-03 PDIBLCB=0 PSCBE1=4.240E+08
resistance + PSCBE2=1.000E-05 PVAG=0 DELTA=1.000E-02
+ CDSC=2.953E-02 CDSCB=7.380E-03 CDSCD=-2.864E-03
Subthreshold + NFACTOR=6.727E-01 CIT=0 VOFF=-6.277E-02

S
+ DSUB=5.600E-01 ETA0=0 ETAB=-1.653E-01
B G D + CAPMOD=3 DWC=3.669E-04 DLC=0 CLC=1.000E-07
SPICE
Charge + CLE=6.000E-01 CF=0 ELM=2 ACDE=1 MOIN=15
model + NOFF=1 VOFFCV=0 XPART=6.000E-01 LLC=0
+ LWC=0 LWLC=0 WLC=-1.253E-10 WWC=-2.595E-07 WWLC=0
Substrate + ALPHA0=2.725E-03 ALPHA1=-7.804E-01 BETA0=3.180E+01
+ JS=1.000E-04 JSW=0 NJ=1 IJTH=1.000E-01
Junction + CJ=5.000E-04 MJ=5.000E-01 PB=1
p +
n +
n + diode + CJSW=5.000E-10 MJSW=3.300E-01 PBSW=1
+ CJSWG=5.000E-10 MJSWG=3.300E-01 PBSWG=1
Overlap cap. + CGSO=0 CGDO=0 CGBO=0 CGSL=0 CGDL=0 CKAPPA=6.000E-01
+ TNOM=27 KT1=-1.100E-01 KT1L=0 KT2=2.200E-02 AT=3.300E+04
Thermal + UA1=4.310E-09 UB1=-7.610E-18 UC1=-5.600E-11 PRT=0 UTE=-1.5
p-well model + XTI=3 TPB=0 TPBSW=0 TPBSWG=0 TCJ=0 TCJSW=0 TCJSWG=0
Noise + NOIMOD=1 KF=1.000E-17 AF=1.5 EF=1.5 NOIA=2.000E+29
model + NOIB=2.000E+29 NOIC=2.000E+29 EM=4.100E+07
+ XL=0 XW=0 PK1=1.711E-01 PK2=-6.688E-02
Accurate results from electrical simulation Scaling
+ PUA=6.246E-04 PUB=-3.418E-12 LUC=1.519E-05
+ PUC=-5.063E-05 PAGS=2.532E-01 PRDSW=-1.071E+04

Too complex for hand design!

+ WVSAT=0 PVSAT=-1.800E+05 PVTH0=-1.644E-01

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 89/129

Bulk Enhancement MOSFET

Classic large signal I/V model: Linear Saturation
mode region

CLM
S

Non
linear
Channel
cut-off

Channel length modulation (CLM):

negligible for large signal, but critical in small signal

Pinch-off
Current factor voltage

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 90/129

Bulk Enhancement MOSFET Simple enough for hand design

Classic large signal I/V model: Body effect in stacked circuits?

G B

S Body effect
coefficient
Non
linear
Asymmetrical D/S model!

or ?

Channel length modulation (CLM):

negligible for large signal, but critical in small signal

Subthreshold operation?

Single expression wanted for

Pinch-off all regions with continuous
Current factor voltage derivatives (small signal)...

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 91/129

Bulk Enhancement MOSFET

Forward Reverse
EKV large signal I/V model:

G
http://ekv.epfl.ch Specific current Pinch-off voltage
Enz
Krummenacher D S
Vittoz
Subthreshold slope Inversion coefficient
B (1<n<2)

Weak inversion
Strong inversion
(subthreshold)
Conduction
Saturation
(forward)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 92/129

Bulk Enhancement MOSFET Forward saturation example

(neglecting CLM):

EKV large signal I/V model:

G
http://ekv.epfl.ch
Strong inversion
Enz
Krummenacher D S
Moderate
Vittoz

B
Weak

Simple enough for hand design

Symmetrical D/S expressions Leakage

Explicit body effect

Single expression from
strong to weak inversion and
from conduction to saturation
Continuous derivatives for
small signal parameters

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 93/129

Bulk Enhancement MOSFET

Classic small signal transconductance model:
D
D
Small signal
increments only G

G B

S S
B
Non-linear Linear
operating point equivalent circuit

Analog circuits biased through

current sources → op as a
function of drain current

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 94/129

Bulk Enhancement MOSFET

Classic small signal transconductance model:
D
D
Small signal
increments only G

G B

S S
B
Non-linear Linear
operating point equivalent circuit

Analog circuits biased through

current sources → op as a
function of drain current

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 95/129

Bulk Enhancement MOSFET

Classic small signal transconductance model:
D
D
Small signal
increments only G

G B

S S
B
Non-linear Linear
operating point equivalent circuit

Asymmetrical parameters and

non-explicit expressions...

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 96/129

Bulk Enhancement MOSFET

EKV small signal transconductance model:
D
G Small signal
increments only
G

D S

B S
B
Non-linear Linear
operating point equivalent circuit

Weak inversion (subthreshold) Strong inversion

Conduction
Saturation
(forward)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 97/129

Bulk Enhancement MOSFET

EKV small signal transconductance model:
D
G Small signal
increments only
G

D S

B S
B
Non-linear Linear
operating point equivalent circuit

Continuty between operating regions:

Equivalence between models:

Strong
Weak inversion
Best power
efficiency Moderate

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 98/129

Bulk Enhancement MOSFET

Quasi-static transcapacitance model: Input only elements:

G Small signal G
increments only

D S D S

B B
Non-reciprocal!

Conduction Fwd. Saturation

Moderate

Weak

Strong
inversion
Gate oxide cap.
3.9 (SiO2)

(e.g. n = 1.3)

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 99/129

Bulk Enhancement MOSFET

Small signal noise model: Uncorrelated phenomena:
OS interface Thermal
trapping agitation

Power spectral density (PSD) statistics:

Thermal (white) component:

-10dB/dec

Flicker Thermal
Flicker (pink) component:
Technology dependent
(NMOS >> PMOS)

Memory
effect

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 100/129

Bulk Enhancement MOSFET

Small signal noise model: Noise-aware analog IC design:
OS interface Signal
Thermal full scale
trapping agitation Signal-to-noise
ratio

Thermal (white) component:

Dynamic Power Dynamic Area

Flicker (pink) component: Range Range

Technology dependent
(NMOS >> PMOS)

Low-power Circuit design

Memory circuit design scalability
effect

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 101/129

Bulk Enhancement MOSFET

Extrinsic D/S diffusion diodes:

B S G D

p+ n+ n+
n+
p-well

p-well
Geometry parameters:
Reverse leakage current:

Depletion capacitance:

Bottom Side
plate walls

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 102/129

EKV Model Extraction

Sequential methodology to minimize errors:

PRELIMINARY WIDE WIDE NARROW NARROW

EXTRACTION LONG SHORT LONG SHORT

specific current specific current specific current final check

Extraction of
measurement measurement measurement and fine tuning
DL , DW , RSH
from several L
geometries
VP vs. VG VP vs. VG
VP vs. VG VP
VP vs.vs.
LETA VGVG WETA
LETA
VTO, GAMMA, PHI LETA , Q0 , LK

ID vs. VG ID vs. VD
KP , E0 UCRIT , LAMBDA
Narrow Wide
Long Long
IB vs. VG
IBA , IBB , IBN
W/L array of
transistors to
http://dx.doi.org/10.1109/ICMTS.1996.535636
adjust model
M.Baucher et al., An Efficient Parameter Extraction Methodology scalability
for the EKV MOST Model, IEEE ICMTS, Mar 1996 Narrow Short Wide Short

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 103/129

EKV Model Extraction

Sequential methodology to minimize errors:

PRELIMINARY WIDE WIDE NARROW NARROW

EXTRACTION LONG SHORT LONG SHORT

specific current specific current specific current final check

Extraction of
measurement measurement measurement and fine tuning
DL , DW , RSH
from several L
geometries
VP vs. VG VP vs. VG
VP vs. VG VP
VP vs.vs.
LETA VGVG WETA
LETA
VTO, GAMMA, PHI LETA , Q0 , LK

ID vs. VG ID vs. VD
KP , E0 UCRIT , LAMBDA
Narrow Wide
Long Long
IB vs. VG
IBA , IBB , IBN
W/L array of
transistors to
http://dx.doi.org/10.1109/ICMTS.1996.535636
adjust model
M.Baucher et al., An Efficient Parameter Extraction Methodology scalability
for the EKV MOST Model, IEEE ICMTS, Mar 1996 Narrow Short Wide Short

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 104/129

EKV Model Extraction

e.g. specific-current estimation:

Weak Strong
inversion inversion

http://dx.doi.org/10.1109/ICMTS.1996.535636
M.Baucher et al., An Efficient Parameter Extraction Methodology
for the EKV MOST Model, IEEE ICMTS, Mar 1996

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 105/129

EKV Model Extraction

e.g. specific-current estimation: e.g. threshold-voltage estimation:

GAMMA

Weak Strong
inversion inversion

PHI

V
G I
B
V =V
S P

http://dx.doi.org/10.1109/ICMTS.1996.535636
M.Baucher et al., An Efficient Parameter Extraction Methodology
for the EKV MOST Model, IEEE ICMTS, Mar 1996

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 106/129

Passive Components
Top plate
Not
Coplanar capacitors: stretchable!

Inter-layer Low-ohmic
thin insulator connectors Bottom plate

Electrical
permittivity
Overlap + fringing capacitance: [F/m]

Process
dependent

Typ. available CMOS structures:

Voltage Temp.
linearity indep.
MOS >1
PiP or MiM 1~10
PolySi-insulator-PolySi
Sandwitch techniques...
Metal-insulator-Metal
http://dx.doi.org/10.1109/EDL.1982.25610
C.P.Yuan and T.N.Trick, A Simple Formula for the Estimation of the Capacitance of Two-Dimensional Interconnects in VLSI Circuits, IEEE Electron Device Letters, 3(12):391-3, Dec 1982

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
 1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 107/129

Passive Components
Not
stretchable!
Serpentine resistors:

Low-ohmic Volume
connectors resistivity
[Ωm]

Square resistance: Process

dependent
Highly resistive
stripes Design
aspect ratio

Typ. available CMOS structures:

Voltage Temp.
linearity indep.
Well ~1k
Diffusion ~100
PolySi ~10
Highly
resistive Metal ~1m
PolySi HiPo 1k~10k

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 108/129

Technological Mismatching
Statistical Gaussian model:
Device
parameter
P?
Standard
deviation e.g. thickness
e.g. dopant gradient
General non-uniformity
Pelgrom Law
CMOS process
dependent

http://dx.doi.org/10.1109/JSSC.1989.572629
M.J.M.Pelgrom et al., Matching Properties of MOS Transistors, IEEE Journal Solid-State Circuits, 24(5):1433-9, Oct 1989

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 109/129

Technological Mismatching
Statistical Gaussian model:

Standard
deviation e.g. thickness
e.g. dopant gradient
General non-uniformity
Pelgrom Law
CMOS process
dependent

e.g. MOS differential pair: small-signal

uncorrelated
phenomena

M1 M2

http://dx.doi.org/10.1109/JSSC.1989.572629
M.J.M.Pelgrom et al., Matching Properties of MOS Transistors, IEEE Journal Solid-State Circuits, 24(5):1433-9, Oct 1989

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 110/129

Technological Mismatching
Statistical Gaussian model: M1 M2

Standard
deviation e.g. thickness
e.g. dopant gradient
General non-uniformity
Pelgrom Law
CMOS process
dependent

Weak Moderate Strong

inversion

Best area
e.g. MOS current mirror: small-signal
efficiency
uncorrelated
phenomena

Typically, VTH mismatch is dominant...

http://dx.doi.org/10.1109/JSSC.1989.572629
M.J.M.Pelgrom et al., Matching Properties of MOS Transistors, IEEE Journal Solid-State Circuits, 24(5):1433-9, Oct 1989

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 111/129

Technological Mismatching
Statistical Gaussian model:

Standard
deviation e.g. thickness
e.g. dopant gradient
General non-uniformity
Pelgrom Law NMOS VTH mismatching: 0.8mVµm × tox[nm]
CMOS process 50
dependent
45
Rule of thumb:

40
2.0µm 2.0µm

35 2.5µm

2.5µm
30

Analog design scalability?

AVTHN [mVµm]
25 1.6µm

Depletion 1.2µm
layer 20
0.8µm
0.6µm
Area
Precision
15
1.0µm
0.35µm
10 0.7µm
0.18µm

5 0.30µm
0.12µm 0.25µm
0
0 10 20 30 40 50 60
tox [nm]

http://dx.doi.org/10.1109/JSSC.1989.572629
M.J.M.Pelgrom et al., Matching Properties of MOS Transistors, IEEE Journal Solid-State Circuits, 24(5):1433-9, Oct 1989

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 112/129

1 CMOS Technologies

2 From the Idea to the Chip

3 Device Modeling for Analog Design

4 The Operational Amplifier and its FoMs

5 Lab Proposal

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 113/129

Universal Analog Building Block

Operational voltage amplifier (OpAmp) e.g. Instrumentation amplifier

Single ended
case study

Analog signal processing functions

Non-linear, temp. uncompensated...

e.g. I/V converter

As far as OpAmp
gain and bandwidth
Wanted are large enough
performance

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 114/129

Universal Analog Building Block

Operational voltage amplifier (OpAmp) CMOS OpAmp known as operational
transconductance amplifier (OTA)

Single ended
case study

Analog signal processing functions

Non-linear, temp. uncompensated...

e.g. switched capacitor (SC) filters

As far as OpAmp
gain and bandwidth
Wanted are large enough
performance

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 115/129

OpAmp Performance Parameters

Large signal static figures (ideal): Open-loop differential DC voltage

transfer curve (VTC) at constant CM:
Input range
Finite
Output range
Equivalent input offset
Open loop differential DC gain

Differential
input

Common
mode
input

supply voltage
Systematic Mismatching

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 116/129

OpAmp Performance Parameters

Large signal static figures (ideal): Input common-mode DC sweep:

Input range
Output range
Equivalent input offset
Open loop differential DC gain

Common mode range

Depending on feedback topology!

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 117/129

OpAmp Performance Parameters

Small signal dynamic figures (ideal): AC Bode diagram:
Open loop differential DC gain
Bandwidth -20dB/dec
Gain-bandwidth product
Phase margin

Equivalent input noise

-40

Frequency

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 118/129

OpAmp Performance Parameters

Small signal dynamic figures (ideal): AC Bode diagram:
Open loop differential DC gain
Bandwidth -20dB/dec
Gain-bandwidth product
Phase margin

Equivalent input noise

-40
Common mode rejection ratio

Frequency

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 119/129

OpAmp Performance Parameters

Small signal dynamic figures (ideal): AC Bode diagram:
Open loop differential DC gain
Bandwidth -20dB/dec
Gain-bandwidth product
Phase margin

Equivalent input noise

-40
Common mode rejection ratio
Power supply rejection ratio

Frequency

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 120/129

OpAmp Performance Parameters

Large signal dynamic figures (ideal) Transient step response:
Settling time Amplitude independance (linear behaviour)

Time

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 121/129

OpAmp Performance Parameters

Large signal dynamic figures (ideal) Transient step response:
Settling time Amplitude independance (linear behaviour)
Slew rate

Finite
power! Time

Amplitude dependence (non-linear behaviour)

Slope limit
[V/s]

Time

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 122/129

OpAmp Performance Parameters

Large signal dynamic figures (ideal) Transient harmonic response:
Settling time Amplitude independance (linear behaviour)
Slew rate

Maximum frequency

Finite
power! Time

Amplitude dependence (non-linear behaviour)

Time
Small/large
signal boundary

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 123/129

OpAmp Performance Parameters

Large signal dynamic figures (ideal) Transient harmonic response:
Settling time
Slew rate Amplitude
compression
Maximum frequency
Total harmonic distortion

Time
Slope
limitation

Both static and dynamic non-linearity = signal distortion

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 124/129

OpAmp FoMs
Quantitative design comparison
Useful in circuit optimization:

Design
modification

Optimization Electrical
rule simulation

Cost
evaluation

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 125/129

OpAmp FoMs
Quantitative design comparison Too many performance parameters!
Resources
Useful in circuit optimization: formance
Per

Design
modification

Optimization Electrical
rule simulation
Application specific FoMs...

Cost
evaluation

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 126/129

1 CMOS Technologies

2 From the Idea to the Chip

3 Device Modeling for Analog Design

4 The Operational Amplifier and its FoMs

5 Lab Proposal

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 127/129

My OpAmp in CNM25
V DD

V in+ +
V out
Two-stage Miller
V in- -

OpAmp design case V SS

V DD

Simple 2.5μm 2P2M

CMOS technology (CNM25) M8
M7
M5

G G
V in- V out
M1 M2 Ccomp
B T
D S D S

B B

B
M3 M4 M6
G T G VIA
WINDOW METAL
B B

V in+ V SS
D S D S
METAL2
NPLUS GASAD
POLY1
POLY0
NTUB

p+ n+ n+
p+ p+ n+
p-well n-well

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 128/129

My OpAmp in CNM25 Electrical

Initial specs

Choose one out simulation

of these three FoM!
IR mVpp
CM R Upper >4 V

Two-stage Miller
Lower <1
OR >3 Vpp
Vof f ±σ <10 mVrms

OpAmp design case

Pd Vin = 2.5V <1.5 mW
GD C >60 dB
CM RR D C >50 dB
P SRR D C + >50 dB
− >50
SR + >1.5 V/ µs

Simple 2.5μm 2P2M

− >1.5
ts(1%) Vout = 2 → 3V <1500 ns
Vout = 3 → 2V <1500
f max Vout = OR KHz

CMOS technology (CNM25)

TH D Vout = OR/ 2@10KHz <1 %
BW −3dB Hz
GB W >1 MHz
φm >50 deg
Vnieq 100Hz to 10MHz <1 mVrms
Area <0.025 mm2

OpAmp circuit optimzation

Full-custom analog Circuit
CMOS layout optimization

M7
M8 M5

M1 M2

M3 M4 M6

My layout

My schematic
Physical
verification
Mask
design

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells
1. Introduction to the Design of Analog ICs CMOS Idea-to-Chip Modeling OpAmp Lab 129/129

My OpAmp in CNM25 IC
functional
specifications
Physical design kit
(PDK)
Glade
Two-stage Miller Circuit-level
schematic
Device symbols
and netlisting rules
OpAmp design case Schematic
design SpiceOpus
Process and
Electrical

Simple 2.5μm 2P2M

mismatch
simulation device models

CMOS technology (CNM25) Glade

PCell-based and PCell layout
python netlist-driven layout generation code

OpAmp circuit optimzation Design rule Layer boolean ops

python
checker and rules script

Full-custom analog
CMOS layout
PCell extraction
Layout versus
gemini code and
Physical schematic
matching rules
design
Freeware and multi-OS fastcap
3D parasitics Technology

(MS Windows, Linux)

extraction cross section

EDA tools SpiceOpus

Post-layout
Parasitics models
simulation

Work at home Glade Tape-out Layer map table

and tutorial at lab...

Mask making
Wafer processing
http://www.cnm.es/~pserra/uab/damics/lab.html Screening IC
Dicing prototype
Semiconductor samples
Packaging
Foundry

Design of Analog and Mixed Integrated Circuits and Systems F. Serra Graells