8085 Interrupts New

10/29/2019 E6-B TKMCE Kollam 1
INTRODUCTION
 P execute instruction in sequence.
 Sometimes it become necessary to suspend normal sequence of execution

inorder to attend some urgent task.
 For e.g. When an I/O device is ready for data transfer, It will send an
interrupt signal to P . When interrupt occurs P will suspend normal
sequence of program execution and branches to a subroutine called
Interrupt Service Subroutine (ISS)
 An interrupt is an emergency signal that may be serviced as soon as

possible.
 So, in general, Interrupt is a process where an external device can get the
attention from the microprocessor.
 The process starts from the I/O device
 The process is asynchronous.

 What happens when P is interrupted ?
 When the P receives an interrupt signal, it suspends the normal
execution of program and branches to a subroutine called

Interrupt Service Subroutine (ISS) to respond to the incoming
interrupt.
 Each interrupt will most probably have its own ISS.
 When the interrupt signal arrives following sequence of
operation is to be carried out:

 The processor will break its normal routine
 Go to a different routine (ISS)
 Complete ISS
 Go back to the normal (main) routine

Interrupts in 8085 INTA
Interrupt
Save Send out

program Disable interupt
counter interrupts acknowledge
Main routine
Go to
service
Go back
routine
Get EI
original RET
program
counter Service routine

CLASSIFICATION OF INTERRUPTS
 Maskable Interrupts: Interrupt requests can be ignored or delayed if P is
doing some urgent tasks.
 Non-Maskable Interrupts: Interrupt requests cannot be ignored or delayed.
P must respond to a non maskable interrupts immediately.
 Vectored interrupts: Here, the address of the service routine (ISS) is
hard-wired. The address of the subroutine is already known to the
Microprocessor
 i.e. After occurrence of these interrupts ISS start from predefined
locations called vectored locations
 Non-vectored interrupts: Here, the address of the service routine needs
to be supplied externally by the device-external hardware.
 i.e., The device will have to supply the address of the subroutine to
the Microprocessor

Maskable & Nonmaskable INT

8085 INTERRUPT STRUCTURE
 There are 5 interrupt inputs:

 TRAP (Non-Maskable)- Priority 1
 RST7.5
 RST6.5
 RST5.5
 INTR
 If multiple interrupt occurs 8085

service them based on priority

8085 INTERRUPTS
 The INTR is the only non-vectored interrupt.
 RST 5.5, RST 6.5, RST 7.5, and TRAP are all
automatically vectored interrupts.
 INTR, RST 5.5, RST 6.5, and RST 7.5 are all
maskable interrupts.
 INTR is maskable using the EI/DI instructions.
 TRAP is the only non-maskable interrupt in the 8085

Enable & Disable the maskable interrupts
 The ‘EI’ instruction is a one-byte instruction and

is used to Enable the maskable interrupts.
 The ‘DI’ instruction is a one-byte instruction and

is used to Disable the maskable interrupts.
 The 8085 has a single Non-Maskable interrupt.

i.e., TRAP

 In short in 8085
Interrupt Name Maskable Vectored
INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes

8085 INTERRUPTS
TRAP
RST7.5
RST6.5
RST 5.5 8085
INTR
INTA

Vectored Interrupts in 8085
There are four interrupt inputs in 8085 that transfer the

operation immediately to a specific address:
▪ TRAP : vector location 0024
▪ RST 7.5: vector location 003C
▪ RST 6.5: vector location 0034
▪ RST 5.5: vector location 002C
▪ RST 7.5, RST 6.5 and RST 5.5 are maskable interrupts,
they are acknowledged only if they are not masked !

Masking RST 5.5, RST 6.5 and RST 7.5
 These three interrupts are masked at two
levels:
 Through the Interrupt Enable flip flop and
the EI/DI instructions.
 The Interrupt Enable flip flop controls the
whole maskable interrupt process.
 Through individual mask flip flops that
control the availability of the individual
interrupts.
 These flip flops control the interrupts
individually.
MASKABLE INTERRUPTS
RST7.5 Memory
RST 7.5
M 7.5
RST 6.5
M 6.5
RST 5.5
M 5.5
INTR
Interrupt
Enable
Flip Flop
10/29/2019 14 TKMCE Kollam

E6-B
Triggering Levels:
 RST 7.5 is positive edge sensitive.
 When a positive edge appears on the RST7.5 line, a logic 1

is stored in the flip-flop as a “pending” interrupt.
 Since the value has been stored in the flip flop, the line does
not have to be high when the microprocessor checks for the
interrupt to be recognized.
 The line must go to zero and back to one before a new
interrupt is recognized.
 RST 6.5 and RST 5.5 are level sensitive.
 The interrupting signal must remain present until the

microprocessor checks for interrupts.
Interrupts structure

Maskable/Vectored Interrupt
Process
1. The interrupt process should be enabled
using the EI instruction.
2. The 8085 checks for an interrupt during
the execution of every instruction.
3. If there is an interrupt, and if the interrupt
is enabled using the interrupt mask, the
microprocessor will complete the
executing instruction, and reset the
interrupt flip flop.
Process
4. The microprocessor then executes a call
instruction that sends the execution to the
appropriate location in the interrupt vector
table.
5. When the microprocessor executes the
call instruction, it saves the address of the
next instruction on the stack.
6. The microprocessor jumps to the specific
service routine.
Process
7. The service routine must include the
instruction EI to re-enable the interrupt
process.
8. At the end of the service routine, the RET
instruction returns the execution to where
the program was interrupted.

Process
 The Interrupt Enable flip flop is
manipulated using the EI/DI instructions.
 The individual masks for RST 5.5, RST 6.5
and RST 7.5 are manipulated using the
SIM instruction (Set Interrupt Mask).
 This instruction takes the bit pattern in the
Accumulator and applies it to the interrupt
mask enabling and disabling the specific
interrupts.
SIM Instruction
7 6 5 4 3 2 1 0
M5.5
M7.5
M6.5
MSE
SDO
R7.5
SDE
XXX
}
RST5.5 Mask
Serial Data Out 0 - Available
RST6.5 Mask
1 - Masked
RST7.5 Mask
Enable Serial Data Mask Set Enable

0 - Ignore bit 7 0 - Ignore bits 0-2
1 - Send bit 7 to SOD pin 1 - Set the masks according
to bits 0-2
Not Used Force RST 7.5 Flip Flop to reset

1-Not allowed
0-allowed
21
10/29/2019 E6-B TKMCE Kollam
SIM Instruction
 Bit 0 is the mask for RST 5.5, bit 1 is the mask

for RST 6.5 and bit 2 is the mask for RST 7.5.
 If the mask bit is 0, the interrupt is
available.
 If the mask bit is 1, the interrupt is masked.
 Bit 3 (Mask Set Enable - MSE) is an enable for

setting the mask.
 If it is set to 0 the mask is ignored, and the
old settings remain.
 If it is set to 1, the new setting are applied.
SIM Instruction
 Bit 4 of the accumulator in the SIM instruction
allows explicitly resetting the RST 7.5
memory even if the microprocessor did not
respond to it.
 Bit 5 is not used by the SIM instruction
 Bit 6 & Bit 7 is used for extra functionality
such as serial data transmission.

SIM Instruction
 Example: Set the interrupt masks so that RST5.5 is
enabled, RST6.5 is masked, and RST7.5 is enabled.
 First, determine the contents of the accumulator
- Enable 5.5 bit 0 = 0
- Disable 6.5 bit 1 = 1
- Enable 7.5 bit 2 = 0
- Allow setting the masks bit 3 = 1
0 0 0 0 1 0 1 0
- Don’t reset the flip flop bit 4 = 0
- Bit 5 is not used bit 5 = 0
- Don’t use serial data bit 6 = 0 Contents of accumulator are: 0A H
- Serial data is ignored bit 7 = 0
EI ; Enable interrupts including INTR

MVI A, 0A ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
SIM ; Apply the settings RST masks

Non Vectored Interrupt
1. The interrupt process should be enabled
using the EI instruction.
2. The 8085 checks for an interrupt during the
execution of every instruction.
3. If INTR is high, MP completes current
instruction, disables the interrupt and
sends INTA (Interrupt acknowledge) signal
to the device that interrupted .
4. INTA allows the I/O device to send a RST
instruction through data bus.
BUS IDLE (BI) Machine Cycle
 TRAP, RST5.5, RST6.5, and RST7.5
RST (internal)
((SP) – 1)  (PCH)
((SP) – 2)  (PCL)
(SP)  (SP) – 2
(PC)  restart address
The bus idle machine cycle is executed when extra time
or more time is needed for an internal operation of the
processor.During this cycle the status signals S0 ,S1 are
asserted low.The data ,address and control pins are
driven to high impedance state.The READY signal will not
be sampled by the processor in this cycle.

INTERRUPT ACKNOWLEDGE
(INA) Machine Cycle
 INTR ( 0 =< n =< 7 )
RST n
((SP) – 1)  (PCH)
((SP) – 2)  (PCL)
(SP)  (SP) – 2
(PC)  8*n

Multiple Interrupts
•Microprocessor can be interrupted again
before the completion of the ISS.
•As soon as the 1st interrupt arrives, all
maskable interrupts are disabled.
•They will only be enabled after the execution
of the EI instruction.
•If the EI instruction is placed early in the
ISR, other interrupt may occur before the ISR
is done.

The 8085 Interrupts
Interrupt Masking Triggerin
Maskable Vectored Memory
Name Method g Method
Level
INTR Yes DI / EI No No
Sensitive
RST 5.5 / DI / EI Level
Yes Yes No
RST 6.5 SIM Sensitive
DI / EI Edge
RST 7.5 Yes Yes Yes
SIM Sensitive
Level &
TRAP No None Yes No Edge
Sensitive
29
Exercises

Enable all interrupt of 8085
D7 D6 D5 D4 D3 D2 D1 D0
SOD
SOE
XXX
R7.5
MSE
M7.5
M6.5
M5.5
0 0 0 0 1 0 0 0
EI
MVI A,08
SIM

Mask all interrupt of 8085
D7 D6 D5 D4 D3 D2 D1 D0
SOD
SOE
XXX
R7.5
MSE
M7.5
M6.5
M5.5
0 0 0 0 1 1 1 1
EI
MVI A,0F
SIM

Enable RST 6.5 & Disable RST 5.5 &7.5
D7 D6 D5 D4 D3 D2 D1 D0
SOD
SOE
XXX
R7.5
MSE
M7.5
M6.5
M5.5
0 0 0 1 1 1 0 1
EI
MVI A,1D
SIM

Mask RST 6.5 & Unmask RST 5.5 &7.5
D7 D6 D5 D4 D3 D2 D1 D0
SOD
SOE
XXX
R7.5
MSE
M7.5
M6.5
M5.5
0 0 0 0 1 0 1 0
EI
MVI A,0A
SIM

Out 0 through SOD pin
D7 D6 D5 D4 D3 D2 D1 D0
SOD
SOE
XXX
R7.5
MSE
M7.5
M6.5
M5.5
0 1 0 0 0 0 0 0
EI
MVI A,40
SIM

Out 1 through SOD pin
D7 D6 D5 D4 D3 D2 D1 D0
SOD
SOE
XXX
R7.5
MSE
M7.5
M6.5
M5.5
1 1 0 0 0 0 0 0
EI
MVI A,C0
SIM

Pending Interrupts
•Since the 8085 has five interrupt lines,
interrupts may occur during an ISS and
remain pending.
•Using the RIM instruction, it is possible to
can read the status of the interrupt lines
and find if there are any pending interrupts.

RIM instruction: Read Interrupt Mask
 Load the accumulator with an 8-bit pattern
showing the status of each interrupt pin and
mask.
RST7.5 Memory
RST 7.5
M 7.5
7 6 5 4 3 2 1 0
M6.5
M5.5
M7.5
SDI
P6.5
P7.5
P5.5
IE
RST 6.5
M 6.5
RST 5.5
M 5.5
Interrupt Enable
Flip Flop

E6-B
7 6 5 4 3 2 1 0
M6.5
M7.5
M5.5
P6.5
SDI
P7.5
P5.5
IE
RST5.5 Mask
Serial Data In RST6.5 Mask
RST7.5 Mask
} 0 - Available
1 - Masked
RST5.5 Interrupt Pending

RST7.5 Interrupt Pending Interrupt Enable
Value of the Interrupt Enable
Flip Flop

E6-B
•Bits 0-2 show the current setting of the
mask for each of RST 7.5, RST 6.5 and RST
5.5 .They return the contents of the three
mask flip flops.
•Bit 3 shows whether the maskable interrupt
process is enabled or not.
It can be used by a program to
determine whether or not interrupts are
enabled.
•Bits 4-6 show whether or not there are
pending interrupts on RST 7.5, RST 6.5, and
RST 5.5 .
•Bit 7 is used for Serial Data Input.
The RIM instruction reads the value of
the SID pin on the microprocessor and
returns it in this bit.

 Load the accumulator with an 8-bit pattern
showing the status of each interrupt pin and
mask.
RST7.5 Memory
RST 7.5
M 7.5
7 6 5 4 3 2 1 0
M6.5
M5.5
M7.5
SDI
P6.5
P7.5
P5.5
IE
RST 6.5
M 6.5
RST 5.5
M 5.5
Interrupt Enable
Flip Flop

E6-B
7 6 5 4 3 2 1 0
M6.5
M7.5
M5.5
P6.5
SDI
P7.5
P5.5
IE
RST5.5 Mask
Serial Data In RST6.5 Mask
RST7.5 Mask
} 0 - Available
1 - Masked

RST7.5 Interrupt Pending Interrupt Enable
Value of the Interrupt Enable
Flip Flop

E6-B
•Bits 0-2 show the current setting of the

mask for each of RST 7.5, RST 6.5 and RST
5.5 .They return the contents of the three
mask flip flops.
•Bit 3 shows whether the maskable interrupt
process is enabled or not.
It can be used by a program to
determine whether or not interrupts are
enabled.
•Bits 4-6 show whether or not there are

pending interrupts on RST 7.5, RST 6.5, and
RST 5.5 .
•Bit 7 is used for Serial Data Input.
The RIM instruction reads the value of
the SID pin on the microprocessor and
returns it in this bit.

MEMORY MAPPING

 A µP Based system contain a mix of ROM and RAM
 ROM is used for holding permanent program
 RAM is used to hold user program and data
 Memory map is a guide to show how entire system
memory is allocated to RAM & ROM so that future
modification made easy.
 Eg. 4K RAM can built using
 4 nos of 1K RAM chips
 2 nos of 2K RAM chips
 Or by a single 4K RAM chips
 In 8085 we have 16 address line so that it can address
64K memory location
 To interface a particular memory chip with µP address
line in 8085 is partitioned as follows
‘n’ MSB ‘m’ LSB address
To address the chip
To decode and select the chip

 1K RAM requires 10 address line ie A0-A9
 So here n=6 MSB address line
 And m=10 LSB address line
 For decoding and selection of 1K RAM We can use
A10-A15

4K RAM using four 1K RAM chips
First 1K RAM CHIP 0000H------03FFH
Second 1K RAM CHIP 0400H------07FFH
Third 1K RAM CHIP 0800H------0BFFH
Fourth 1K RAM CHIP 0C00H------0FFFH
1K-----210
i.e. 10 address lines are required to interface 1k RAM ie A0-A9
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 03FF
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 03FF
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0400
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 07FF

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 03FF
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0400
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 07FF
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0800
0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0BFF

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 03FF
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0400
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 07FF
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0800
0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0BFF
0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0C00
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFF

Interfacing I/O Devices
 Using I/O devices data can be transferred between the
microprocessor and the outside world.
 This can be done in groups of 8 bits using the entire
data bus. This is called parallel I/O.
 The other method is serial I/O where one bit is
transferred at a time using the SID and SOD pins on
the Microprocessor.

Types of Parallel Interface
 There are two ways to interface 8085 with I/O devices
in parallel data transfer mode:
 Memory Mapped IO
 IO Mapped IO

Memory Mapped IO
• It considers them like any other
memory location.
 They are assigned a 16-bit address within
the address range of the 8085.
 The exchange of data with these devices
follows the transfer of data with memory.
The user uses the same instructions used
for memory.

IO Mapped IO
 It treats them separately from memory.
 I/O devices are assigned a “port number”
within the 8-bit address range of 00H to
FFH.
 The user in this case would access these
devices using the IN and OUT
instructions only.

IO mapped IO V/s Memory Mapped IO
Memory Mapped IO IO Mapped IO
 IO is treated as memory.  IO is treated IO.

 16-bit addressing.  8- bit addressing.
 More Decoder Hardware.  Less Decoder Hardware.
 Can address 216=64k  Can address 28=256
locations. locations.
 Less memory is available.  Whole memory address
space is available.

IO mapped IO V/s Memory Mapped IO
• Memory Mapped IO • IO Mapped IO
• Memory Instructions are • Special Instructions

used. are used like IN, OUT.
• Memory control signals • Special control signals
are used. are used.
• Arithmetic and logic • Arithmetic and logic
operations can be operations can not be
performed on data. performed on data.
• Data transfer b/w • Data transfer b/w
register and IO. accumulator and IO.
 Since several memory chips are connected to µP , an
address decoding circuit is employed to select required
memory chip. This decoding is usually performed
using 74LS138 decoder IC. It is a 3-8 decoder IC (active
low output)

BUFFER

INPUT OUTPUT PORT
 An I/O port is a place where loading and unloading of
data
 An input device is connected to µP through input port
 Data from input device is stored in temporarily in a
register. The out put of this register is connected to
data bus through a tri-state buffer.
 To read data from input device µP generate a device
select pulse using address line, RD and IO/M lines.
Thus address of the device is present on the address
bus only when buffer is get enabled.

8085 D0-D7 Tristate 8 – BIT INPUT
Processor buffer LATCH DEVICE
DEVICE Input Port

A0-A7 SELECT
IO/M LOGIC Device select pulse
RD

8085 8 – BIT OUTPUT
D0-D7
Processor Register DEVICE
DEVICE OUTPUT Port

A0-A7 SELECT
IO/M LOGIC
WR

Widely used
Programmable Peripheral Interface

8255
 40 pin IC operate on a single 5 Vdc supply
 It interface peripheral devices to the
microcomputer
 8255 contains 3 eight bit programmable I/O ports
namely Port A, Port B and Port C and a Control
Register
 Port C can be used as two 4 bit ports namely Port
Cupper(PC7-PC4) and Port C lower (PC3-PC0)
 Thus Total 4 ports are available ie. Two 8bit port
and two 4 bit ports
 DATA is transferred between µP and 8255
through DATA bus D0-D7
Control Groups and CWR format
 For the purpose of controlling the 4 I/O ports, they are
divided into two groups.
 Group A and Group B
 Group A contain Port A and Port Cupper
 Group B contain Port B and Port Clower
 Control Word format
D7 D6 D5 D4 D3 D2 D1 D0
Modes of Mode of Mode of Port A Port Mode of Port B Port
operation Port A Port A (I/O) Cupper Port B (I/O) C lower
(I/O) (I/O)

D0-D7
PA0-PA7
RESET
CS
PC4-PC7
82C55
A0
A1
PC0-PC3
RD
WR
Vcc PB0-PB7
GND

 RD and WR signals are used for indicating to 8255
whether read or write operation is to be performed
 8255 is selected only if CS is low
 Address lines A0 and A1 are used for selecting
 Control word register
 And one of the port
 Address lines A7 to A2 are decoded to provide CS signal
CS A1 A0 Address Selection
0 0 0 00 PORT – A
0 0 1 01 PORT – B
0 1 0 02 PORT – C
0 1 1 03 CONTROL REGISTER
1 X X -- 8255 is not selected
82C55

 When system power up , RESET signal applied to 8255
 And clear the control register and set all ports to input
port
 8255 will continue in this state until µP give a control
word in control register
 Control word determines the modes of operation of
8255

PA3 1 40 PB4
PA2 2 39 PB5
Pin diagram 8255

PA1 3 38 PB6
PA0 4 37 PB7
RD 5 36 WR
CS 6 35 RESET
GND 7 34 D0
A1 8 33 D1
A0 9 32 D2
3
PC7 10 31 D3
PC6 11 8255A 30 D4
3
PC5 12 29 D5
PC4 13 28 D6
PC0 14 27 D7
PC1 15 26 VCC
PC2 16 25 PB7
PC3 17 24 PB6
PB0 18 23 PB5
PB1 19 22 PB4
PB2 20 21 PB3

 Eg.
 IN 00H:- When this instruction is executed data is
transferred from port A to accumulator.
transferred from port B to accumulator.
transferred from port C to accumulator.
 OUT 03H:- When this instruction is executed content
of accumulator is transferred to control word register.

Programming 82C55

OPERATING MODES OF 8255
 Basically 8255 has 2 modes of operation

 I/O Mode
 BSR Mode
 I/O Mode can again classified as mode 0, mode 1 and
mode 2

Mode 0 (Simple I/O Mode)
 Mode 0 operation is applicable to all ports
 It is also known as Basic input output mode
 Here any port can be used as simple input or output
mode
 No control signals are required
 Control word for making all ports as output port is
D7 D6 D5 D4 D3 D2 D1 D0
=1 (I/O) (I/O)
1 0 0 0 0 0 0 0
8 0
 The following instruction will set all ports as output
 MVI A,80H; Control word in accumulator
 OUT 03H ; Control word in control word register
 Write an ALP to make port A as input and remining
ports as output port?
D7 D6 D5 D4 D3 D2 D1 D0
=1 (I/O) (I/O)
1 0 0 1 0 0 0 0
9 0
MVI A,90H; Control word in accumulator
OUT 03H ; Control word in control word register

Mode 1 (Strobed input output mode)
 Port A and B can be operated in this mode
 6 pins of port C are used for control of port A and B
 PC0,PC1 and PC2 are used for controlling port B when
it is operating as an input or output port
 PC3,PC4 and PC5 are used for controlling port A
operation

Mode 2 (Strobed bidirectional mode)
 Only Port A can be operated in this mode. It is
operated as bidirectional port
 When port A is operated in this mode port B can used
either in mode 0 or mode 1
 PC3 to PC7 are used for controlling port A operation

BIT- SET- RESET(BSR) Mode
 8255 has a bit set-reset capability for port C.
 Any bit of Port C can be set or cleared
 The control word format for BSR mode operation is
D7 D6 D5 D4 D3 D2 D1 D0
Modes of 1--for bit set

operation Bit to be set / reset 0--for bit reset
Not used
=0 000-------for bit0
001-------for bit1
-----
-----
111-------for bit0

To set bit 4 of port C Control word is
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 0 0 1
MVI A,09H
OUT 03H

To reset bit 7 of port C Control word is
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 1 1 0
MVI A,0EH
OUT 03H

8085 Interrupts New

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 Sometimes it become necessary to suspend normal sequence of execution

 An interrupt is an emergency signal that may be serviced as soon as

 The process starts from the I/O device

 The process is asynchronous.

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execution of program and branches to a subroutine called

 Each interrupt will most probably have its own ISS.

 When the interrupt signal arrives following sequence of

operation is to be carried out:

 Go to a different routine (ISS)

 Go back to the normal (main) routine

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Save Send out

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 There are 5 interrupt inputs:

 If multiple interrupt occurs 8085

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 The INTR is the only non-vectored interrupt.

 INTR is maskable using the EI/DI instructions.

 TRAP is the only non-maskable interrupt in the 8085

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 The ‘EI’ instruction is a one-byte instruction and

 The ‘DI’ instruction is a one-byte instruction and

 The 8085 has a single Non-Maskable interrupt.

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Interrupt Name Maskable Vectored

RST 5.5 Yes Yes

RST 6.5 Yes Yes

RST 7.5 Yes Yes

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There are four interrupt inputs in 8085 that transfer the

▪ TRAP : vector location 0024

▪ RST 7.5: vector location 003C

▪ RST 6.5: vector location 0034

▪ RST 5.5: vector location 002C

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 When a positive edge appears on the RST7.5 line, a logic 1

 The interrupting signal must remain present until the

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Enable Serial Data Mask Set Enable

Not Used Force RST 7.5 Flip Flop to reset

 Bit 0 is the mask for RST 5.5, bit 1 is the mask

 Bit 3 (Mask Set Enable - MSE) is an enable for

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EI ; Enable interrupts including INTR

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