International Technology Roadmap

for Semiconductors

2008 ITRS ORTC

[7/14-16 ITRS Meetings San Francisco]

A.Allan, Rev 1 (for 7/16 Public Conference Prep)

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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 Agenda
• Moore’s Law and More
• Technology Pacing Trends Update
– Physical and Printed GL Focus
• Summary

• Backup
– Function Size, Moore’s Law on Track
– Design On-Chip Frequency
– SICAS Technology, Wafer Generation Demand Update
– Definitions

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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 2008 ITRS Executive Summary Fig 5
[updated for 2007] [2008 –
Moore’s Law & More Update Definitions]
Functional
More Diversification (More than Moore)
than Moore: Diversification Facilitator:
Traditional Mart Graef
ORTC Models [Geometrical & Equivalent scaling]
Analog/RF
HV
Passives
HV
Passives
Sensors
Biochips
Baseline CMOS: CPU, Memory, Logic
Power Power Actuators
Miniaturization

Interacting with people

130nm
Moore)

and environment

90nm CCoo Non-digital content

nmtib System-in-package
niun
(More

in (SiP)
65nm g SS
ooC
Ca
Moore:

Information
annd
Scaling

45nm Processing dSSi

Pi:P
Digital content :HiHg
More

32nm hige
System-on-chip hr eV
(SoC) raV
lu
22nm ael S
uey
. sSt
. eym
. s SIP “White Paper”
V
tsem
Facilitator: s A&P TWG
Alan Allan Chair: Bill Bottoms
Beyond CMOS www.itrs.net/
Facilitator: papers.html
Jim Hutchby
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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 2007 ITRS “Moore’s Law and More”
Alternative Definition Graphic
Baseline RF HV Passives Sensors, Bio-chips,
CMOS Memory Power Actuators Fluidics

“More Moore”
“More than Moore”

Computing & Sense, interact,

Data Storage Empower

Heterogeneous Integration
System on Chip (SOC) and System In Package (SIP)

Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC) 4

Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 2008 ITRS “Beyond CMOS”
Baseline Ultimately Functionally Nanowire Ferromagnetic Spin Logic
CMOS Scaled CMOS Enhanced CMOS Electronics Logic Devices Devices

32nm 22nm 16nm 11nm 8nm

Multiple gate MOSFETs New State Variable
Channel Replacement Materials New Devices
Low Dimensional Materials Channels New Data Representation
New Data Processing
Algorithms

“More Moore” “Beyond CMOS”

Computing and Data Storage Beyond CMOS

Source: Emerging Research Device Working Group

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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 2007 - PIDS/FEP - Simplified Transistor Roadmap
[Examples of “Equivalent Scaling” from ITRS PIDS/FEP TWGs] – Update in 2009
poly metal
SiON high k gate stack
electrostatic control

bulk
planar 3D
MuGFET
MuCFET
PDSOI FDSOI

+ substrate + high µ
stressors engineering materials

65nm 45nm 32nm 22nm

[ ITRS DRAM/MPU Timing: 2007[7.5] 2010 2013 2016 ]

Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC) 6

Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 2007 Definition of the Half Pitch – 2008 unchanged
[No single-product “node” designation; DRAM half-pitch still litho driver; however,
other product technology trends may be drivers on individual TWG tables]

DRAM ½ Pitch
FLASH Poly Silicon ½ Pitch
= DRAM Metal Pitch/2
= Flash Poly Pitch/2
MPU/ASIC M1 ½ Pitch
Poly = MPU/ASIC M1 Pitch/2
Pitch Metal
Pitch

8-16 Lines
Typical flash Typical DRAM/MPU/ASIC
Un-contacted Poly Metal Bit Line
Source: 2005 ITRS - Exec. Summary Fig 2
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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 2008 - Unchanged
Fig 3
Production Ramp-up Model and Technology Cycle Timing
100M
Development Production 200K
10M
Volume (Parts/Month)

20K

Volume (Wafers/Month)
1M
2K
100K Alpha Beta Production
Tool Tool Tool 200

10K First Two

First Companies 20
1K Conf. Reaching
Papers Production 2

-24 -12 0 12 24
Source: 2005 ITRS - Exec. Summary Fig 3 Months
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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 2007 ITRS Product Technology Trends - [WAS]
Half-Pitch, Gate-Length
1000.0

Before 1998
.71X/3YR

After 1998 DRAM M1 1/2 Pitch

.71X/2YR
MPU M1
.71X/2.5YR MPU & DRAM M1
Product Half-Pitch, Gate-Length

100.0 & Flash Poly MPU M1 1/2 Pitch

.71X/3YR (2.5-year cycle)
(nm)

Flash Poly 1/2 Pitch

Flash Poly
.71X/2YR
10.0 MPU Gate Length -
Printed
Gate Length
.71X/3YR
MPUGate Length -
GLpr IS = Physical
1.6818 x GLph
Nanotechnology (<100nm) Era Begins -1999
1.0
1995 2000 2005 2010 2015 2020 2025
Year of Production

2007 - 2022 ITRS Range 9

Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 2008 ITRS Update - Technology Trends vs Actuals and Survey
Jeff Butterbaugh/FEP
GLphys Actuals
(leading):
1000
"More Moore" Kwok Ng/PIDS
Functional GLphys Survey
2.5-year Density (leading):
Cycle Complemente
Printed GL =
[.5^(1/5yrs)] d Glpr(nm) MPU (ITRS
Physical GL
by "Equivalent 05-07)
After 2019
Scaling" 2008
Performance/ Update
Power Mgt Glph(nm) MPU (ITRS
[Copper IC; 05-07)
nanometers (1e-9)

Strain Si; 2008

Update
Metal Gate/
100 Hi-K; M1 Half Pitch(nm)
UTB/FDSOI; MPU (ITRS 05-07)
MUG; etc.] [also DRAM M1 in
2008 Update]

3-year M1 Half Pitch(nm)

DRAM (ITRS 05-07)
Cycle
[.5^(1/6yrs)]
GLprinted =
[decreasing Poly Half Pitch(nm)
Flash (ITRS 07)
Etch ratio] [Litho Driver after
2007 ]
GLphysical = “32nm” 2yr GLph Proposal 2008
~0.71x/ 3.8yrs GLph delay “20nm” 3yr Update
GLph delay
10
2000 “45nm” 1yr 2005 2010 2015 “10nm” 5yr 2020 2025
GLph delay GLph delay
Work in Progress - Do Year Work in Progress - Do
Not Publish! 2007/08 ITRS: 2007-2022 Not Publish!

• GLphysical 2008 Update IS: 3.8yr cycle after 2007; enabled by “Equiv. Scaling”
• FEP and PIDS have proposed shifted/interpolated tables; full model redo in ‘09
• GLprinted parallel to MPU/DRAM M1 Half-Pitch; shrinking etch ratio to GLphy 10
Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 ORTC Summary – 2008 Update Status
• Flash Model un-contacted poly half-pitch trend
– Unchanged 2-year cycle* through 2008/45nm, then 3-year cycle* (2014/22.5; 2020/11.25); ;
– Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip
– PIDS Flash Survey Team to report status of survey data update and proposals in July meetings.
• DRAM Model stagger-contacted M1 half-pitch updated to the MPU 2.5-year cycle*
through 2010/45nm [affects 2007, 2008, 2009], then
– Unchanged 3-year cycle* beginning 2010/45nm (2016/22.5; 2022/11.25);
– Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip
• DRAM function size, function density, and chip size models have been updated to
latest Product 2.5-year cycle scaling rate;
– Only 2007-2009 years affected in 2008 Table Update.
– Unchanged 2010-2022
• MPU Model M1 stagger-contact half-pitch unchanged from 2007
– 2.5-year cycle* through 2010/45nm, then 3-year cycle* (2016/22.5; 2022/11.25).

• MPU/ASIC Printed Gate Length Updated

– 1.6818 Etch Ratio in 2007;
– Then variable Gpr/Gphy Etch Ratio (parallel to DRAM/MPU M1 Contacted Half Pitch) ‘07-’22.
• MPU/ASIC High-Performance Physical Gate Length
– 3.8-year cycle* beginning 2007 Performance and Power needs manage.
– FEP and Litho TWGs have agreed on new annual variable GLprinted/GLphysical ratio targets
– Slower On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS ORTC) - need
updated transistor and design model alignment by PIDS, FEP, and Design – 2009 Renewal.
– New drivers will be Ion/Width, CV/I – possibly add to ORTC - 2009 Renewal ORTC line items.

* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]

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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 ORTC Summary – 2008 Update Status (cont.)
• MPU/ASIC Low Operating Power Printed Gate Length
– TBD
• MPU/ASIC Low Standby Power Physical Gate Length [add to ORTC 1a,b]
– No Change 2007, 2008; two-year delay 2009-2011 from High Performance; one-year delay in
2012; and no delay 2013-2022.

• New 2008 “Moore’s Law and More” Working Groups and Definitions Work :
– “More Moore” (“Moore’s Law;” typically digital computing) Functional and Performance scaling is
enabled by both “Geometrical” and also “Equivalent” scaling technologies; Design “Equivalent
Scaling” to be added in 2008
– More than Moore “Functional diversification” text will be impacted (typically non-digital
sensing, interacting) system board-level migration/miniaturization is enabled by system-in-package
and system-on-chip
– “Beyond CMOS” definition will be added, focused on the Computing and Storage Logic
Switch transition and consensus options at “Ultimately Scaled CMOS”

• The average of the industry product “Moore’s Law” (2x functions/chip per 2 years) rate
forecast to continue throughout the latest 2007-2022 ITRS timeframe
• Total MOS Capacity (SICAS) growing at >16% CAGR (SICAS); new “<80nm” data
split out; and 300mm Capacity Demand has ramped to over 40% of Total MOS
• Industry Technology Capacity Demand (SICAS) – 1Q08 published status] continues on
a on 2-year cycle* rate at the leading edge.

* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]

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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 Backup
• Function Size; Moore’s Law on track
• Design Frequency (2007)
• SICAS Update (1Q08 data)
• Definitions

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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
Figure 9[’07] ITRS Product Function Size 2008 Update:
2007 ITRS Product Function Size Trends - [NO CHANGE to MPU and Flash;
Cell Size, Logic Gate(4t) Size Small change ’07-’09 to DRAM]
1.E+01
Past ÅÆ Future
Logic Gate: NO DRAM Cell Size (u2)
Design Area
Factor Improvement
1.E+00 (Only Scaling)
MPU SRAM Cell Size
SRAM: gradual (6t)(u2)
Design Area
Factor Improvement
Cell, Logic Gate Size

DRAM - Small
1.E-01 MPU Gate Size
Adjustments
(4t)(u2)
(um2 )

In 2008
DRAM 6f2 DRAM: 6f2 is last
Pull-in to ‘06 Design Area
Factor Improvement
Flash Cell Size (u2)
1.E-02 SLC

Flash: 4f2 Last Flash Eqv.bit Size(u2)

Design Physical Area 2bit MLC
Factor Improvement
1.E-03 (@ 2 MLC bits/physical cell area)
Flash cell area
Flash Eqv.bit Size(u2)
Reduced due to
2YR cycle Flash: (MLC @ 2 bits/cell = 4bit MLC - New
2f2 Equivalent Area Factor) (@ 4 MLC bits/physical cell area)
Extension
1.E-04
2000 2005 2010 2015 2020 2025
Year of Production Flash 4 bits/cell
1f2 Beginning 2010
14
2007 - 2022 ITRS Range
Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 Figure 10 ITRS Product Functions per Chip
2007 ITRS Product Technology Trends - [Unchanged for 2008]
Functions per Chip
1.E+03
Flash Bits/Chip (Gbits)
Multi-Level-Cell (4bit
Flash MLC MLC)
4 bits/chip
Added
Flash Bits/Chip (Gbits)
1.E+02 Multi-Level-Cell (2bit
MLC)
[ Giga (10^9) - bits, transistors ]

Flash Bits/Chip (Gbits)

Single-Level-Cell (SLC )
Product Functions/Chip

Flash SLC
1.E+01
Bits/chip
for 1-year DRAM Bits/Chip (Gbits)
Pull-in

1.E+00
MPU GTransistors/Chip
- high-performance (hp)
Moore’s Law
DRAM
1.E-01 Bits/chip
On MPU GTransistors/Chip
1-year Track! - cost-performanc (cp)
Delay;

Average Industry
1.E-02 "Moores Law“ :
1995 2000 2005 2010 2015 2020 2025 2x Functions/chip Per 2 Years
Year of Production

2007 - 2022 ITRS Range

15
Past Å Æ Future
Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 New Design TWG
2007 ITRS Frequency 2022
~14.3Ghz
Historical Data vs 2005 ITRS
And Proposed* Trend Ave ~8% CAGR
Past Å Æ Future

Actual
History vs ITRS
On-Chip? 2005/06 ITRS ~ 8%
CAGR

2007
~4.7Ghz

New Design TWG

2007 ITRS Final “IS”
Ave 8% CAGR

~ 21%
CAGR 2007 - 2022 ITRS Range

* Source: Various, per ITRS Design TWG ca August 2007

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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 Performance and Power Management
Enabled by “Equivalent Scaling”
D e s ig n M a x O n -C h ip C lo c k F re q u e n c y D e sig n
M a x.
In c lu d in g 2 0 0 5 IT R S a n d F in a l (A u g '0 7 ) 2 0 0 7 D e s ig n T W G F re q .
1 0 0 .0 2001
IT R S
2005/06 1 .1 7 x/ye a r
"G a p " D e la ye d (2 x/4 .5 yrs )
ITRS
b y 3 ye a rs
“WAS”
W A S /IS
in 2 0 0 5 IT R S Gamers D e sig n
“Clock-Doubling?” M a x.
F re q .
IS : D e sig n /A rch ite ctu re : re d u ctio n o f
2003
m a xim u m # 0 f in ve rte r d e la ys to fla t a t IT R S
1 2 b e g in n in g 2 0 0 7
W A S : (2 0 0 1 IT R S : fla t a t 1 6 a fte r 2 0 0 6 )
(Ghz)

1 0 .0
1 .2 9 x/ye a r E xtra p o la t
io n /In te rp
(2 x/2 .5 yrs)
o la tio n o f
2005
1 .4 1 x/ye a r W AS
(2 x/2 yrs ) New Design TWG IT R S
P ro p o sa l
2007 ITRS Final “IS”
Ave 8% CAGR F in a l M a x
O n -C h ip
P a s t < -----> F u tu re L o ca l
C lo c k
1 .0 F re q
1995 2000 2005 2010 2015 2020 2025 (A u g '0 7 )
Year

2007 Des TWG 2007 - 2022 ITRS Range

Actual History of
Average On-Chip
~ 21% CAGR 17
Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 ITRS
2007 “Fig 4” Technology Cycle Timing Compared to Actual Wafer Production Technology
Technology Capacity Distribution Cycle
[Updated >0.7μm
Through 720nm
10
W.P.C = Total W.P.C.=Total WorldWafer
Worldwide wide WaferProduction
ProductionCapacity* Sources:SICA
Capacity; S
Source: SICAS* 2Q07]
W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C W.P.C 0.7-0.4μm
2007 ITRS
Feature Size (Half Pitch) (μm)

510nm
MPU/ASIC
(2.5-yr Cycle)
0.4-0.3μm
360nm
1 SIA/SICAS
Data**:
1-yr 0.3- 0.2μm
delay from 255nm
ITRS Cycle
Timing
0.2- 0.16μm
to >20% of
MOS IC 180nm
0.1 Capacity
0.16-.12μm
127nm
= 2005/06 ITRS DRAM Contacted M1 Half-Pitch Actual
= 2007 ITRS DRAM Contacted M1 Half-Pitch Target
= 2007 ITRS Flash Uncontacted Poly Half Pitch Target <0.12μm

90nm
3-Year Cycle 2-Year Cycle 3-Yr Cycle
0.01
1997 1998
1997 1998 1999
1999 2000
2000 2001 2002 2003
2001 2002 2003 2004
2004 2005
2005 2006
2006 2007
2007 ---- 2010 Note: Includes
<80nm split-out
Year
Note: The wafer production capacity data are plotted from the Semiconductor Industry Association (SIA) Semiconductor Industry Capacity (ITRS 65nm)
Statistics (SICAS) 4Q data for each year, except 2Q data for 2007. to be added
The width of each of the production capacity bar corresponds to the MOS IC production start silicon area for that range In the 2008
of the feature size (y-axis). Data are based upon capacity if fully utilized. ITRS Upcate
** Source: The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity
Statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published 18by the
Semiconductor Industry Association (SIA), as of August, 2007. The detailed data are available to the public online at the SIA website, http://www.sia-
online.org/pre_stat.cfm . Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 SICAS 1Q08 Update (www.sia-online.org )
MOS Capacity by Dimensions >=0.7µ

100% <0.7µ >=0.4µ

90% <0.4µ >=0.3µ
80%
WSpW x1000

<0.3µ >=0.2µ
70%
60% <0.2µ >=0.16µ
50% <0.16µ >=0.12µ
40%
~33% ~33% <0.12µ
30%
20% <0.12µ >=0.08µ
10% 2yr Cycle
<0.08µ
~0.7x

0%
2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q
05 05 05 06 06 06 06 07 07 07 07 08
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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 SICAS 1Q08 Update (www.sia-online.org )
MOS Capacity by Wafer-size >16% CAGR

100% ~27Bcm2 ~39Bcm2

~4Bcm2/16%
90% ~5Bcm2/14%

80%
(8 inch equivalents)

70%
WSpW x1000

~18Bcm2/46%
60%
~17Bcm2/62%
50%
~16Bcm2/41%
40% < 200m
30%
20% ~6Bcm2/22% 200mm
10% 300mm
0%
2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q
20
05 05 05 06 06 06 06 07 07 07 07 08
Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 2007 ITRS Definitions:
“More Moore” and “More than Moore”
1. Scaling (“More Moore”)
a. Geometrical (constant field) Scaling refers to the continued shrinking of
horizontal and vertical physical feature sizes of the on-chip logic and memory
storage functions in order to improve density (cost per function reduction)
and performance (speed, power) and reliability values to the applications and
end customers.
b. Equivalent Scaling which occurs in conjunction with, and also enables,
continued Geometrical Scaling, refers to 3-dimensional device structure
(“Design Factor”) Improvements plus other non-geometrical process
techniques and new materials that affect the electrical performance of the
chip.

2. Functional Diversification (“More than Moore”)

Functional Diversification refers to the incorporation into devices of
functionalities that do not necessarily scale according to "Moore's Law," but
provide additional value to the end customer in different ways. The "More-
than-Moore" approach typically allows for the non-digital functionalities (e.g.
RF communication, power control, passive components, sensors, actuators)
to migrate from the system board-level into a particular package-level
(SiP) or chip-level (SoC) potential solution.
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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
 More than Moore Study Group 4/3/08

ORTC Summary – 2008 Update Status

Design TWG Proposed “More Moore” and “MtM” Text, 3 Apr 2008 Plenary v2a
[discussion leader – Andrew Kahng] – Proposal accepted at Koenigswinter.
• 1 = More Moore
– 1a = geometric scaling
– 1b = equivalent scaling
– 1c = Design equivalent scaling
– NEED: quantifiable, specific Design Technologies that deal with More Moore
– “Design equivalent scaling occurs in conjunction with Equivalent Scaling and continued
Geometric Scaling, and refers to design technologies that enable high performance, low
power, high reliability, low cost, and high design productivity.”
– “Examples (not exhaustive) are: Design for variability; low power design (sleep modes,
hibernation, clock gating, multi-VDD, ...); and homogeneous and heterogeneous multicore
SOC architectures.”
– Request: Please remove “b) Multi-core MPU architecture” from 2 (MTM Functional
Diversification)
• 2 = More than Moore
– NEED: Design technologies to enable functional diversification
– “Design technologies enable new functionality that takes advantage of More than Moore
technologies.”
– “Examples (not exhaustive) are: Heterogeneous system partitioning and simulation; software;
analog and mixed signal design technologies for sensors and actuators; and new methods
and tools for co-design and co-simulation of SIP, MEMS, and biotechnology.”
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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA
“Beyond CMOS” Definition

“Beyond CMOS” refers to emerging research devices, focused

on a “new switch*” used to process information, typically
exploiting a new state variable to provide functional scaling
substantially beyond that attainable by ultimately scaled CMOS.
Substantial scaling beyond CMOS is defined in terms of
functional density, increased performance, dramatically reduced
power, etc.

*The “New Switch” refers to an “information processing

element or technology”, which is associated with
compatible storage or memory and interconnect functions.

Examples of Beyond CMOS include: carbon-based nano-

electronics, spin-based devices, ferromagnetic logic, atomic
switch, NEMS switches, etc.
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Work in Progress – Do Not Publish ITRS 2008 Update Preparation – July, San Francisco, USA