module Adder (A, B, C, E,SUM);

input [3:0] A;

input [3:0] B;

input [3:0] C;

input [3:0] E;

output [3:0] SUM;

wire[3:0] SUM;

always@ (A or B or C or E)

begin

$dumpfile("dump.vcd");

$dumpvars(1);

SUM <=A+B+C+E;

end

endmodule

module Divider(SUM,reset, clock, Q);

input [3:0] SUM;

input reset, clock;

output [3:0] Q;

reg [3:0] Q;

reg [3:0] SUM;

always @ (posedge clock);

if (reset)

Q=0;

else

begin

Q[0] <<=SUM[1];

Q[1] <<=Q[2];

Q[2] <<=Q[3];
Q[3] <<=SUM[0];

end

endmodule

DESIGN

module Adder_test;

reg [3:0] A, B, C, E;

reg clock, reset;

wire[3:0] SUM;

module Adder(

.A(A),

.B(B),

.C(C),

.E(E),

.SUM(SUM),

);

module Divider(

.Q(Q),

.SUM(SUM),

.clock(clock),

.reset(reset)

);

always #10 clock=~clock;

initial

begin

clock=0;
 reset=0;

#50 reset=1;

#50 reset=0;

#10 A = 4'b0000;

#10 B = 4'b0001;

#10 C = 4'b0010;

#10 E = 4'b0011;

end

initial

begin

$monitor($time, " clock=%1b,reset=%1b,q=%4b",clock,reset,q);

end

endmodule