UNIVERSITY OF INFORMATION MID-TERM EXAMINATION II (2018-2019)

TECHNOLOGY COURSE: IC DESIGN WITH VERILOG HDL

COMPUTER ENGINEERING Time duration: 60 minutes
DEPARTMENT (Paper materials are allowed)

STUDENT NAME: ……………………………………ID: …………..ORDER:…

1. Question 1 (3 points)
a. Compare the Pros and Cons between Structural Model and Behavior Model when
using Verilog HDL to the design a circuit (2 points)
b. What differences between blocking assignment and non-blocking assignment? (1
points)

2. Question 2 (3 points)
Using Verilog HDL structural model to design the ModuleA with following functions:

C2 C1 C0 Operation
0 0 1 {Out, Cout} = In1 + In2
1 0 0 Out = |In1|
1 0 1 {Out, Cout} = In1 - In2
1 1 0 Out = Min (In1, In2)
1 1 1 Out = Max (In1, In2)

1
3. Question 3 (4 points)
Using Verilog HDL behavioral model to design the ModuleB with following functions:

Start Zero_One_Cnt Operation

0 X CntOut = 0
Done = 0
1 0 CntOut = Number bit “0” of In
Done = 1 when counting is finished
1 1 CntOut = Number bit “1” of In
Done = 1 when counting is finished

This examination’s learning outcomes (LO) (matching to subject syllabus’s

LO)
Question LO Description

1 G5 Understand and use specialized English terms

of the subject. Have ability to read
professional documents in foreign languages.

2 G1.2 Plan and design the block diagram of the

design from the statement of the problem.

3 G2 Know and apply different design flows of

HDL language to solve scientific problems.

Approved by Head of Subject Designed by